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/linux/drivers/media/platform/chips-media/wave5/
H A Dwave5-vpuerror.h18 #define WAVE5_SYSERR_QUEUEING_FAIL 0x00000001
19 #define WAVE5_SYSERR_ACCESS_VIOLATION_HW 0x00000040
20 #define WAVE5_SYSERR_BUS_ERROR 0x00000200
21 #define WAVE5_SYSERR_DOUBLE_FAULT 0x00000400
22 #define WAVE5_SYSERR_RESULT_NOT_READY 0x00000800
23 #define WAVE5_SYSERR_VPU_STILL_RUNNING 0x00001000
24 #define WAVE5_SYSERR_UNKNOWN_CMD 0x00002000
25 #define WAVE5_SYSERR_UNKNOWN_CODEC_STD 0x00004000
26 #define WAVE5_SYSERR_UNKNOWN_QUERY_OPTION 0x00008000
27 #define WAVE5_SYSERR_VLC_BUF_FULL 0x00010000
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/linux/arch/arm/probes/
H A Ddecode.h42 if (pcv & 0x1) { in bx_write_pc()
44 pcv &= ~0x1; in bx_write_pc()
47 pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */ in bx_write_pc()
107 * if P (bit 24) == 0 or W (bit 21) == 1
109 #define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
189 * REGS(0, ANY, NOPC, 0, ANY)
197 * bits 3.. 0 any register allowed here
212 * DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
213 * REGS(ANY, ANY, NOPC, 0, ANY)),
242 REG_TYPE_NONE = 0, /* Not a register, ignore */
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
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