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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
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H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
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H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
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H A Dgc_11_0_0_default.h28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
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/linux/Documentation/devicetree/bindings/input/
H A Dgoogle,cros-ec-keyb.yaml43 (((row) & 0xFF) << 24) | (((column) & 0xFF) << 16)
77 MATRIX_KEY(0x00, 0x02, 0) /* T1 */
78 MATRIX_KEY(0x03, 0x02, 0) /* T2 */
79 MATRIX_KEY(0x02, 0x02, 0) /* T3 */
80 MATRIX_KEY(0x01, 0x02, 0) /* T4 */
81 MATRIX_KEY(0x03, 0x04, 0) /* T5 */
82 MATRIX_KEY(0x02, 0x04, 0) /* T6 */
83 MATRIX_KEY(0x01, 0x04, 0) /* T7 */
84 MATRIX_KEY(0x02, 0x09, 0) /* T8 */
85 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
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/linux/arch/m68k/ifpsp060/
H A Disp.sa1 .long 0x60ff0000,0x02360000,0x60ff0000,0x16260000
2 .long 0x60ff0000,0x12dc0000,0x60ff0000,0x11ea0000
3 .long 0x60ff0000,0x10de0000,0x60ff0000,0x12a40000
4 .long 0x60ff0000,0x12560000,0x60ff0000,0x122a0000
5 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
6 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
7 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
8 .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
9 .long 0x2f00203a,0xfefc487b,0x0930ffff,0xfef8202f
10 .long 0x00044e74,0x00042f00,0x203afeea,0x487b0930
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/linux/include/crypto/
H A Daria.h42 0x00636363, 0x007c7c7c, 0x00777777, 0x007b7b7b,
43 0x00f2f2f2, 0x006b6b6b, 0x006f6f6f, 0x00c5c5c5,
44 0x00303030, 0x00010101, 0x00676767, 0x002b2b2b,
45 0x00fefefe, 0x00d7d7d7, 0x00ababab, 0x00767676,
46 0x00cacaca, 0x00828282, 0x00c9c9c9, 0x007d7d7d,
47 0x00fafafa, 0x00595959, 0x00474747, 0x00f0f0f0,
48 0x00adadad, 0x00d4d4d4, 0x00a2a2a2, 0x00afafaf,
49 0x009c9c9c, 0x00a4a4a4, 0x00727272, 0x00c0c0c0,
50 0x00b7b7b7, 0x00fdfdfd, 0x00939393, 0x00262626,
51 0x00363636, 0x003f3f3f, 0x00f7f7f7, 0x00cccccc,
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
142 cpu0: cpu@0 {
145 reg = <0x0>;
149 i-cache-size = <0x8000>;
152 d-cache-size = <0x8000>;
165 reg = <0x1>;
169 i-cache-size = <0x8000>;
172 d-cache-size = <0x8000>;
185 reg = <0x2>;
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/linux/arch/m68k/ifpsp060/src/
H A Disp.S42 set _off_chk, 0x00
43 set _off_divbyzero, 0x04
44 set _off_trace, 0x08
45 set _off_access, 0x0c
46 set _off_done, 0x10
48 set _off_cas, 0x14
49 set _off_cas2, 0x18
50 set _off_lock, 0x1c
51 set _off_unlock, 0x20
53 set _off_imr, 0x40
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