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/linux/include/crypto/
H A Dblake2b.h32 BLAKE2B_IV0 = 0x6A09E667F3BCC908ULL,
33 BLAKE2B_IV1 = 0xBB67AE8584CAA73BULL,
34 BLAKE2B_IV2 = 0x3C6EF372FE94F82BULL,
35 BLAKE2B_IV3 = 0xA54FF53A5F1D36F1ULL,
36 BLAKE2B_IV4 = 0x510E527FADE682D1ULL,
37 BLAKE2B_IV5 = 0x9B05688C2B3E6C1FULL,
38 BLAKE2B_IV6 = 0x1F83D9ABFB41BD6BULL,
39 BLAKE2B_IV7 = 0x5BE0CD19137E2179ULL,
45 state->h[0] = BLAKE2B_IV0 ^ (0x01010000 | keylen << 8 | outlen); in __blake2b_init()
53 state->t[0] = 0; in __blake2b_init()
[all …]
H A Dblake2s.h36 BLAKE2S_IV0 = 0x6A09E667UL,
37 BLAKE2S_IV1 = 0xBB67AE85UL,
38 BLAKE2S_IV2 = 0x3C6EF372UL,
39 BLAKE2S_IV3 = 0xA54FF53AUL,
40 BLAKE2S_IV4 = 0x510E527FUL,
41 BLAKE2S_IV5 = 0x9B05688CUL,
42 BLAKE2S_IV6 = 0x1F83D9ABUL,
43 BLAKE2S_IV7 = 0x5BE0CD19UL,
49 state->h[0] = BLAKE2S_IV0 ^ (0x01010000 | keylen << 8 | outlen); in __blake2s_init()
57 state->t[0] = 0; in __blake2s_init()
[all …]
/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dnv04.c28 { 0x00001000, NVKM_ENGINE_GR },
29 { 0x00000100, NVKM_ENGINE_FIFO },
36 nvkm_mask(mc->subdev.device, 0x000200, mask, 0x00000000); in nv04_mc_device_disable()
44 nvkm_mask(device, 0x000200, mask, mask); in nv04_mc_device_enable()
45 nvkm_rd32(device, 0x000200); in nv04_mc_device_enable()
51 return (nvkm_rd32(mc->subdev.device, 0x000200) & mask) == mask; in nv04_mc_device_enabled()
63 { NVKM_ENGINE_DISP , 0, 0, 0x01010000, true },
64 { NVKM_ENGINE_GR , 0, 0, 0x00001000, true },
65 { NVKM_ENGINE_FIFO , 0, 0, 0x00000100 },
66 { NVKM_SUBDEV_BUS , 0, 0, 0x10000000, true },
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-imon-pad.c19 { 0x2a8195b7, KEY_REWIND },
20 { 0x298315b7, KEY_REWIND },
21 { 0x2b8115b7, KEY_FASTFORWARD },
22 { 0x2b8315b7, KEY_FASTFORWARD },
23 { 0x2b9115b7, KEY_PREVIOUS },
24 { 0x298195b7, KEY_NEXT },
26 { 0x2a8115b7, KEY_PLAY },
27 { 0x2a8315b7, KEY_PLAY },
28 { 0x2a9115b7, KEY_PAUSE },
29 { 0x2b9715b7, KEY_STOP },
[all …]
/linux/drivers/media/pci/dt3155/
H A Ddt3155.h21 #define DT3155_VER_MIN 0
22 #define DT3155_VER_EXT 0
28 #define EVEN_DMA_START 0x00
29 #define ODD_DMA_START 0x0C
30 #define EVEN_DMA_STRIDE 0x18
31 #define ODD_DMA_STRIDE 0x24
32 #define EVEN_PIXEL_FMT 0x30
33 #define ODD_PIXEL_FMT 0x34
34 #define FIFO_TRIGGER 0x38
35 #define XFER_MODE 0x3C
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,msm8996-pinctrl.yaml58 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
137 reg = <0x01010000 0x300000>;
140 gpio-ranges = <&tlmm 0 0 150>;
/linux/arch/powerpc/platforms/44x/
H A Dpci.c40 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) in ppc440spe_revA()
54 return 0; in ppc440spe_revA()
62 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
83 r->start = r->end = 0; in fixup_ppc4xx_pci_bridge()
84 r->flags = 0; in fixup_ppc4xx_pci_bridge()
103 res->start = 0; in ppc4xx_parse_dma_ranges()
104 size = 0x80000000; in ppc4xx_parse_dma_ranges()
114 while ((rlen -= np * 4) >= 0) { in ppc4xx_parse_dma_ranges()
[all …]
/linux/net/smc/
H A Dsmc_clc.h22 #define SMC_CLC_PROPOSAL 0x01
23 #define SMC_CLC_ACCEPT 0x02
24 #define SMC_CLC_CONFIRM 0x03
25 #define SMC_CLC_DECLINE 0x04
27 #define SMC_TYPE_R 0 /* SMC-R only */
33 #define SMC_CLC_DECL_MEM 0x01010000 /* insufficient memory resources */
34 #define SMC_CLC_DECL_TIMEOUT_CL 0x02010000 /* timeout w4 QP confirm link */
35 #define SMC_CLC_DECL_TIMEOUT_AL 0x02020000 /* timeout w4 QP add link */
36 #define SMC_CLC_DECL_CNFERR 0x03000000 /* configuration error */
37 #define SMC_CLC_DECL_PEERNOSMC 0x03010000 /* peer did not indicate SMC */
[all …]
/linux/include/linux/
H A Dfsl_ifc.h26 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000
37 #define CSPR_BA 0xFFFF0000
39 #define CSPR_PORT_SIZE 0x00000180
42 #define CSPR_PORT_SIZE_8 0x00000080
44 #define CSPR_PORT_SIZE_16 0x00000100
46 #define CSPR_PORT_SIZE_32 0x00000180
48 #define CSPR_WP 0x00000040
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_isharp_filters.c21 0x02010000,
22 0x0A070503,
23 0x1614100D,
24 0x1C1B1918,
25 0x22211F1E,
26 0x27262423,
27 0x2A2A2928,
28 0x2D2D2C2B,
29 0x302F2F2E,
30 0x31313030,
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h13 #define E1000_WUC_APME 0x00000001 /* APM Enable */
14 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
15 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
16 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
20 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
21 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
22 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
23 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
24 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/linux/drivers/pci/hotplug/
H A Dcpqphp_ctrl.c52 #define WRONG_BUS_FREQUENCY 0x07
56 u8 rc = 0; in handle_switch_change()
62 return 0; in handle_switch_change()
67 for (hp_slot = 0; hp_slot < 6; hp_slot++) { in handle_switch_change()
68 if (change & (0x1L << hp_slot)) { in handle_switch_change()
73 (hp_slot + ctrl->slot_device_offset), 0); in handle_switch_change()
85 func->presence_save = (temp_word >> hp_slot) & 0x01; in handle_switch_change()
86 func->presence_save |= (temp_word >> (hp_slot + 7)) & 0x02; in handle_switch_change()
88 if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) { in handle_switch_change()
93 func->switch_save = 0; in handle_switch_change()
[all …]
/linux/drivers/media/pci/pt1/
H A Dpt1.c131 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
134 I2C_BOARD_INFO("qm1d1b0004", 0x60),
139 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
142 I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
147 I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
150 I2C_BOARD_INFO("qm1d1b0004", 0x60),
155 I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
158 I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
164 {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
165 {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
[all …]
/linux/drivers/media/platform/qcom/venus/
H A Dhfi_venus.c22 #define HFI_MASK_QHDR_TX_TYPE 0xff000000
23 #define HFI_MASK_QHDR_RX_TYPE 0x00ff0000
24 #define HFI_MASK_QHDR_PRI_TYPE 0x0000ff00
25 #define HFI_MASK_QHDR_ID_TYPE 0x000000ff
27 #define HFI_HOST_TO_CTRL_CMD_Q 0
30 #define HFI_MASK_QHDR_STATUS 0x000000ff
33 #define IFACEQ_CMD_IDX 0
38 #define IFACEQ_DFLT_QHDR 0x01010000
202 qhdr->tx_req = 0; in venus_write_queue()
228 *rx_req = qhdr->rx_req ? 1 : 0; in venus_write_queue()
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.c72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
90 case 0: in sun4i_tcon_channel_set_status()
94 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0); in sun4i_tcon_channel_set_status()
101 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0); in sun4i_tcon_channel_set_status()
166 val = 0xf; in sun6i_tcon_setup_lvds_phy()
169 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), in sun6i_tcon_setup_lvds_phy()
185 SUN4I_TCON0_LVDS_IF_EN, 0); in sun4i_tcon_lvds_set_status()
202 channel = 0; in sun4i_tcon_set_status()
218 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0); in sun4i_tcon_set_status()
228 u32 mask, val = 0; in sun4i_tcon_enable_vblank()
[all …]
/linux/drivers/scsi/megaraid/
H A Dmegaraid_sas.h34 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
35 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
36 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
37 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
38 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
39 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
40 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
41 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
42 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
43 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
[all …]
/linux/sound/pci/ca0106/
H A Dca0106_main.c77 * Add 4 capture channels. (SPDIF only comes in on channel 0. )
164 { .serial = 0x10131102,
182 { .serial = 0x10121102,
188 { .serial = 0x10021102,
192 { .serial = 0x10051102,
196 { .serial = 0x10061102,
201 { .serial = 0x10071102,
211 { .serial = 0x100a1102,
215 .spi_dac = 0x4021 } ,
222 { .serial = 0x10111102,
[all …]
/linux/drivers/char/
H A Drandom.c85 CRNG_EMPTY = 0, /* Little to no entropy collected */
134 * Returns: 0 if the input pool has been seeded.
145 return ret > 0 ? 0 : ret; in wait_for_random_bytes()
147 return 0; in wait_for_random_bytes()
160 int ret = 0; in execute_with_initialized_rng()
164 nb->notifier_call(nb, 0, NULL); in execute_with_initialized_rng()
281 * _vdso_rng_data.generation's invalid value is 0, so add one to the in crng_reseed()
325 memset(&chacha_state[12], 0, sizeof(u32) * 4); in crng_fast_key_erasure()
419 if (unlikely(chacha_state[12] == 0)) in _get_random_bytes()
432 * wait_for_random_bytes() should be called and return 0 at least once
[all …]
/linux/drivers/ptp/
H A Dptp_ocp.c28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
76 #define OCP_CTRL_ENABLE BIT(0)
84 #define OCP_STATUS_IN_SYNC BIT(0)
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
53 clocks = <&kryocc 0>;
68 reg = <0x0 0x1>;
72 clocks = <&kryocc 0>;
82 reg = <0x0 0x100>;
101 reg = <0x0 0x101>;
[all …]
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h21 e1000_undefined = 0,
40 e1000_eeprom_uninitialized = 0,
50 e1000_media_type_copper = 0,
57 e1000_10_half = 0,
65 E1000_FC_NONE = 0,
69 E1000_FC_DEFAULT = 0xFF
79 e1000_bus_type_unknown = 0,
87 e1000_bus_speed_unknown = 0,
98 e1000_bus_width_unknown = 0,
106 e1000_cable_length_50 = 0,
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-dif.h23 {3000000, DIF_BPF_COEFF01, 0x00000002},
24 {3000000, DIF_BPF_COEFF23, 0x00080012},
25 {3000000, DIF_BPF_COEFF45, 0x001e0024},
26 {3000000, DIF_BPF_COEFF67, 0x001bfff8},
27 {3000000, DIF_BPF_COEFF89, 0xffb4ff50},
28 {3000000, DIF_BPF_COEFF1011, 0xfed8fe68},
29 {3000000, DIF_BPF_COEFF1213, 0xfe24fe34},
30 {3000000, DIF_BPF_COEFF1415, 0xfebaffc7},
31 {3000000, DIF_BPF_COEFF1617, 0x014d031f},
32 {3000000, DIF_BPF_COEFF1819, 0x04f0065d},
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8723b2ant.c32 static u32 glcoex_ver_8723b_2ant = 0x3f;
45 s32 bt_rssi = 0; in btc8723b2ant_bt_rssi_state()
134 s32 wifi_rssi = 0; in btc8723b2ant_wifi_rssi_state()
250 u32 reg_hp_tx = 0, reg_hp_rx = 0; in btc8723b2ant_monitor_bt_ctr()
251 u32 reg_lp_tx = 0, reg_lp_rx = 0; in btc8723b2ant_monitor_bt_ctr()
253 reg_hp_txrx = 0x770; in btc8723b2ant_monitor_bt_ctr()
254 reg_lp_txrx = 0x774; in btc8723b2ant_monitor_bt_ctr()
281 "[BTCoex], High Priority Tx/Rx(reg 0x%x)=0x%x(%d)/0x%x(%d)\n", in btc8723b2ant_monitor_bt_ctr()
284 "[BTCoex], Low Priority Tx/Rx(reg 0x%x)=0x%x(%d)/0x%x(%d)\n", in btc8723b2ant_monitor_bt_ctr()
288 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); in btc8723b2ant_monitor_bt_ctr()
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-core.c45 #define CX25840_VID_INT_STAT_REG 0x410
46 #define CX25840_VID_INT_STAT_BITS 0x0000ffff
47 #define CX25840_VID_INT_MASK_BITS 0xffff0000
49 #define CX25840_VID_INT_MASK_REG 0x412
51 #define CX23885_AUD_MC_INT_MASK_REG 0x80c
52 #define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
53 #define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
56 #define CX25840_AUD_INT_CTRL_REG 0x812
57 #define CX25840_AUD_INT_STAT_REG 0x813
59 #define CX23885_PIN_CTRL_IRQ_REG 0x123
[all …]

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