Searched +full:0 +full:x004a8000 (Results 1 – 10 of 10) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/thermal/ |
| H A D | qcom-tsens.yaml | 127 - pattern: '^s[0-9]+_p1$' 128 - pattern: '^s[0-9]+_p2$' 129 - pattern: '^s[0-9]+_p1$' 130 - pattern: '^s[0-9]+_p2$' 131 - pattern: '^s[0-9]+_p1$' 132 - pattern: '^s[0-9]+_p2$' 133 - pattern: '^s[0-9]+_p1$' 134 - pattern: '^s[0-9]+_p2$' 135 - pattern: '^s[0-9]+_p1$' 136 - pattern: '^s[0-9]+_p2$' [all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | ipq9574.dtsi | 24 #clock-cells = <0>; 29 #clock-cells = <0>; 35 #size-cells = <0>; 37 CPU0: cpu@0 { 40 reg = <0x0>; 53 reg = <0x1>; 66 reg = <0x2>; 79 reg = <0x3>; 99 qcom,dload-mode = <&tcsr 0x6100>; 106 reg = <0x0 0x40000000 0x0 0x0>; [all …]
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| H A D | ipq6018.dtsi | 23 #clock-cells = <0>; 29 #clock-cells = <0>; 35 #size-cells = <0>; 37 CPU0: cpu@0 { 40 reg = <0x0>; 54 reg = <0x1>; 67 reg = <0x2>; 80 reg = <0x3>; 99 qcom,dload-mode = <&tcsr 0x6100>; 111 opp-supported-hw = <0xf>; [all …]
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| H A D | qcs404.dtsi | 24 #clock-cells = <0>; 30 #clock-cells = <0>; 37 #size-cells = <0>; 42 reg = <0x100>; 56 reg = <0x101>; 70 reg = <0x102>; 84 reg = <0x103>; 104 CPU_SLEEP_0: cpu-sleep-0 { 107 arm,psci-suspend-param = <0x40000003>; 161 reg = <0 0x80000000 0 0>; [all …]
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| H A D | msm8976.dtsi | 26 #clock-cells = <0>; 32 #size-cells = <0>; 34 CPU0: cpu@0 { 37 reg = <0x0>; 48 reg = <0x1>; 59 reg = <0x2>; 70 reg = <0x3>; 81 reg = <0x100>; 92 reg = <0x101>; 103 reg = <0x102>; [all …]
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| H A D | msm8953.dtsi | 25 #clock-cells = <0>; 31 #clock-cells = <0>; 39 #size-cells = <0>; 41 CPU0: cpu@0 { 44 reg = <0x0>; 54 reg = <0x1>; 64 reg = <0x2>; 74 reg = <0x3>; 84 reg = <0x100>; 94 reg = <0x101>; [all …]
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| H A D | msm8939.dtsi | 30 #clock-cells = <0>; 36 #clock-cells = <0>; 43 #size-cells = <0>; 49 reg = <0x100>; 67 reg = <0x101>; 80 reg = <0x102>; 93 reg = <0x103>; 102 CPU4: cpu@0 { 106 reg = <0x0>; 124 reg = <0x1>; [all …]
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| H A D | msm8916.dtsi | 27 reg = <0 0x80000000 0 0>; 36 reg = <0x0 0x86000000 0x0 0x300000>; 42 reg = <0x0 0x86300000 0x0 0x100000>; 50 reg = <0x0 0x86400000 0x0 0x100000>; 55 reg = <0x0 0x86500000 0x0 0x180000>; 60 reg = <0x0 0x86680000 0x0 0x80000>; 66 reg = <0x0 0x86700000 0x0 0xe0000>; 73 reg = <0x0 0x867e0000 0x0 0x20000>; 85 * alignment = <0x0 0x400000>; 86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; [all …]
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| H A D | msm8996.dtsi | 29 #clock-cells = <0>; 36 #clock-cells = <0>; 44 #size-cells = <0>; 46 CPU0: cpu@0 { 49 reg = <0x0 0x0>; 53 clocks = <&kryocc 0>; 68 reg = <0x0 0x1>; 72 clocks = <&kryocc 0>; 82 reg = <0x0 0x100>; 101 reg = <0x0 0x101>; [all …]
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| /freebsd/sys/dev/bxe/ |
| H A D | 57712_init_values.c | 54 /* #define ATC_COMMON_START 0 */ 55 {OP_WR, 0x1100b8, 0x1}, 58 {OP_WR, 0x600dc, 0x1}, 59 {OP_WR, 0x60050, 0x180}, 60 {OP_SW, 0x61000, 0x1ff0000}, 61 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */ 62 {OP_WR, 0x617fc, 0x3fe001}, 63 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */ 64 {OP_SW, 0x617fc, 0x20101ff}, 65 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */ [all …]
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