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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdx75.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6350.dtsi32 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 CPU0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dmsm8996.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
53 clocks = <&kryocc 0>;
68 reg = <0x0 0x1>;
72 clocks = <&kryocc 0>;
82 reg = <0x0 0x100>;
101 reg = <0x0 0x101>;
[all …]
H A Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsa8775p.dtsi27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
45 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
H A Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
[all …]
H A Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
20 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>;
26 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>
30 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>,
35 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
39 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
41 def SDT_LoongArchCsrrd : SDTypeProfile<1, 1, [SDTCisInt<0>,
43 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/dev/bxe/
H A D57712_init_values.c54 /* #define ATC_COMMON_START 0 */
55 {OP_WR, 0x1100b8, 0x1},
58 {OP_WR, 0x600dc, 0x1},
59 {OP_WR, 0x60050, 0x180},
60 {OP_SW, 0x61000, 0x1ff0000},
61 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
62 {OP_WR, 0x617fc, 0x3fe001},
63 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
64 {OP_SW, 0x617fc, 0x20101ff},
65 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
[all …]