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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
35 #define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
36 #define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
[all …]
H A Dimx1-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX1_PAD_A24__A24 0x00 0x004
35 #define MX1_PAD_A24__GPIO1_0 0x00 0x032
36 #define MX1_PAD_A24__SPI2_CLK 0x00 0x006
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8183.c35 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
36 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
37 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
44 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
[all …]
H A Dclk-mt6779.c640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
[all …]
H A Dclk-mt8192.c27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
36 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
[all …]
H A Dclk-mt8167.c24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
525 0x000, 0, 1),
527 0x000, 1, 1),
529 0x000, 2, 1),
531 0x000, 4, 4),
533 0x000, 8, 3),
535 0x000, 11, 3),
537 0x000, 15, 3),
539 0x000, 18, 1),
541 0x000, 19, 1),
[all …]
H A Dclk-mt7986-topckgen.c176 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
178 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
180 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
182 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
185 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
187 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
/linux/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
H A Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
H A Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/linux/arch/parisc/kernel/
H A Dhardware.c29 {HPHW_NPROC,0x01,0x4,0x0,"Indigo (840, 930)"},
30 {HPHW_NPROC,0x8,0x4,0x01,"Firefox(825,925)"},
31 {HPHW_NPROC,0xA,0x4,0x01,"Top Gun (835,834,935,635)"},
32 {HPHW_NPROC,0xB,0x4,0x01,"Technical Shogun (845, 645)"},
33 {HPHW_NPROC,0xF,0x4,0x01,"Commercial Shogun (949)"},
34 {HPHW_NPROC,0xC,0x4,0x01,"Cheetah (850, 950)"},
35 {HPHW_NPROC,0x80,0x4,0x01,"Cheetah (950S)"},
36 {HPHW_NPROC,0x81,0x4,0x01,"Jaguar (855, 955)"},
37 {HPHW_NPROC,0x82,0x4,0x01,"Cougar (860, 960)"},
38 {HPHW_NPROC,0x83,0x4,0x13,"Panther (865, 870, 980)"},
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-sg2044.c24 #define DIV_ASSERT BIT(0)
105 return div->initval == 0 ? 1 : div->initval; in sg2044_div_get_reg_div()
190 return 0; in sg2044_div_set_rate()
205 return 0; in sg2044_div_enable()
259 static const u32 sg2044_mux_table[] = {0, 1};
269 int ret = 0; in sg2044_mux_notifier_cb()
274 ret = ops->set_parent(hw, 0); in sg2044_mux_notifier_cb()
461 clk_fpll0_parent, 0,
462 0x044, 16, 8,
468 clk_mpll0_parent, 0,
[all …]
/linux/drivers/net/ethernet/ti/
H A Dam65-cpsw-qos.h49 #define AM65_CPSW_REG_CTL 0x004
50 #define AM65_CPSW_PN_REG_CTL 0x004
51 #define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
52 #define AM65_CPSW_PN_REG_EST_CTL 0x060
53 #define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
54 #define AM65_CPSW_P0_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
56 #define AM65_CPSW_PN_REG_CTL 0x004
57 #define AM65_CPSW_PN_REG_TX_PRI_MAP 0x018
58 #define AM65_CPSW_PN_REG_RX_PRI_MAP 0x020
59 #define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
[all …]
/linux/include/sound/sof/
H A Dheader.h23 * 0xGCCCNNNN where
34 #define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT)
39 #define SOF_CMD_TYPE_MASK (0xfffL << SOF_CMD_TYPE_SHIFT)
43 #define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U)
44 #define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U)
45 #define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U)
46 #define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U)
47 #define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U)
48 #define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U)
49 #define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dhw.h43 #define AR9170_UART_REG_BASE 0x1c0000
46 #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000)
47 #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004)
48 #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010)
49 #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x02
50 #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x04
52 #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014)
53 #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018)
54 #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x01
55 #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_regs.h8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
183 VC4_HD_REG(HDMI_M_CTL, 0x000c),
184 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
185 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
186 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
187 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
188 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
189 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
190 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
/linux/arch/arm64/include/asm/
H A Dbrk-imm.h11 * 0x004: for installing kprobes
12 * 0x005: for installing uprobes
13 * 0x006: for kprobe software single-step
14 * 0x007: for kretprobe return
15 * Allowed values for kgdb are 0x400 - 0x7ff
16 * 0x100: for triggering a fault on purpose (reserved)
17 * 0x400: for dynamic BRK instruction
18 * 0x401: for compile time BRK instruction
19 * 0x800: kernel-mode BUG() and WARN() traps
20 * 0x9xx: tag-based KASAN trap (allowed values 0x900 - 0x9ff)
[all …]
/linux/drivers/net/ethernet/seeq/
H A Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-dp-phy.h10 #define QSERDES_DP_PHY_REVISION_ID0 0x000
11 #define QSERDES_DP_PHY_REVISION_ID1 0x004
12 #define QSERDES_DP_PHY_REVISION_ID2 0x008
13 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
14 #define QSERDES_DP_PHY_CFG 0x010
15 #define QSERDES_DP_PHY_CFG_1 0x014
16 #define QSERDES_DP_PHY_PD_CTL 0x018
17 #define QSERDES_DP_PHY_MODE 0x01c
18 #define QSERDES_DP_PHY_AUX_CFG0 0x020
19 #define QSERDES_DP_PHY_AUX_CFG1 0x024
[all …]
/linux/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/linux/drivers/iommu/intel/
H A Dperfmon.c13 PMU_FORMAT_ATTR(event, "config:0-27"); /* ES: Events Select */
67 return 0; \
68 return (iommu_pmu->filter & _filter) ? attr->mode : 0; \
77 IOMMU_PMU_ATTR(filter_requester_id_en, "config1:0", IOMMU_PMU_FILTER_REQUESTER_ID);
84 IOMMU_PMU_ATTR(filter_pasid, "config2:0-21", IOMMU_PMU_FILTER_PASID);
88 #define iommu_pmu_en_requester_id(e) ((e) & 0x1)
89 #define iommu_pmu_en_domain(e) (((e) >> 1) & 0x1)
90 #define iommu_pmu_en_pasid(e) (((e) >> 2) & 0x1)
91 #define iommu_pmu_en_ats(e) (((e) >> 3) & 0x1)
92 #define iommu_pmu_en_page_table(e) (((e) >> 4) & 0x1)
[all …]
/linux/drivers/video/fbdev/via/
H A Daccel.h14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq6h-pins.dtsi9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
27 0x000 0x200 // I2C0_SCL pin
28 0x004 0x200 // I2C0_SDA pin
33 0x008 0x200 // I2C1_SCL pin
34 0x00c 0x200 // I2C1_SDA pin
39 0x080 1 // GPIO_C4__SMA0_MDC pin
40 0x084 1 // GPIO_C5__SMA0_MDIO pin
44 pinctrl-single,pins = <0x0a8 1>; // UART0 pin group
47 pinctrl-single,pins = <0x0a0 1>; // UART1 pin group
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx27-pinctrl.txt12 PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
14 number on the specific port (between 0 and 31).
21 0 - Primary function
28 0 - Input
37 0 - A_IN
46 0 - GPIO_IN
52 CONFIG can be 0 or 1, meaning Pullup disable/enable.
64 reg = <0x10015000 0x600>;
78 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
79 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC2",
[all …]

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