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/linux/include/linux/platform_data/
H A Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/linux/drivers/edac/
H A Dmpc85xx_edac.h11 #define MPC85XX_REVISION " Ver: 2.0.0"
20 #define MPC85XX_L2_ERRINJHI 0x0000
21 #define MPC85XX_L2_ERRINJLO 0x0004
22 #define MPC85XX_L2_ERRINJCTL 0x0008
23 #define MPC85XX_L2_CAPTDATAHI 0x0020
24 #define MPC85XX_L2_CAPTDATALO 0x0024
25 #define MPC85XX_L2_CAPTECC 0x0028
26 #define MPC85XX_L2_ERRDET 0x0040
27 #define MPC85XX_L2_ERRDIS 0x0044
28 #define MPC85XX_L2_ERRINTEN 0x0048
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ull-pinfunc-snvs.h13 #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
14 #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
15 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
16 #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
17 #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
18 #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
19 #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
20 #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
21 #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
22 #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
H A Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-infracfg.c19 #define MT7988_INFRA_RST0_SET_OFFSET 0x70
20 #define MT7988_INFRA_RST1_SET_OFFSET 0x80
60 infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
62 infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
64 infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
66 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
68 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
70 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
71 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
72 0x0010, 0x0014, 14, 2, -1, -1, -1),
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-hdma-v0-regs.h20 #define HDMA_V0_STOP_INT_MASK BIT(0)
21 #define HDMA_V0_LINKLIST_EN BIT(0)
23 #define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0)
24 #define HDMA_V0_DOORBELL_START BIT(0)
25 #define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0)
28 u32 ch_en; /* 0x0000 */
29 u32 doorbell; /* 0x0004 */
30 u32 prefetch; /* 0x0008 */
31 u32 handshake; /* 0x000c */
33 u64 reg; /* 0x0010..0x0014 */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-mixer.h17 #define MXR_STATUS 0x0000
18 #define MXR_CFG 0x0004
19 #define MXR_INT_EN 0x0008
20 #define MXR_INT_STATUS 0x000C
21 #define MXR_LAYER_CFG 0x0010
22 #define MXR_VIDEO_CFG 0x0014
23 #define MXR_GRAPHIC0_CFG 0x0020
24 #define MXR_GRAPHIC0_BASE 0x0024
25 #define MXR_GRAPHIC0_SPAN 0x0028
26 #define MXR_GRAPHIC0_SXY 0x002C
[all …]
H A Dregs-vp.h19 #define VP_ENABLE 0x0000
20 #define VP_SRESET 0x0004
21 #define VP_SHADOW_UPDATE 0x0008
22 #define VP_FIELD_ID 0x000C
23 #define VP_MODE 0x0010
24 #define VP_IMG_SIZE_Y 0x0014
25 #define VP_IMG_SIZE_C 0x0018
26 #define VP_PER_RATE_CTRL 0x001C
27 #define VP_TOP_Y_PTR 0x0028
28 #define VP_BOT_Y_PTR 0x002C
[all …]
/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.h50 #define XEON_PBAR23LMT_OFFSET 0x0000
51 #define XEON_PBAR45LMT_OFFSET 0x0008
52 #define XEON_PBAR4LMT_OFFSET 0x0008
53 #define XEON_PBAR5LMT_OFFSET 0x000c
54 #define XEON_PBAR23XLAT_OFFSET 0x0010
55 #define XEON_PBAR45XLAT_OFFSET 0x0018
56 #define XEON_PBAR4XLAT_OFFSET 0x0018
57 #define XEON_PBAR5XLAT_OFFSET 0x001c
58 #define XEON_SBAR23LMT_OFFSET 0x0020
59 #define XEON_SBAR45LMT_OFFSET 0x0028
[all …]
/linux/drivers/media/pci/mantis/
H A Dhopper_vp3028.h14 #define MANTIS_VP_3028_DVB_T 0x0028
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x07_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
H A Dhw_host1x08_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
H A Dhw_host1x06_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
/linux/drivers/video/fbdev/geode/
H A Dvideo_cs5530.h18 #define CS5530_VIDEO_CONFIG 0x0000
19 # define CS5530_VCFG_VID_EN 0x00000001
20 # define CS5530_VCFG_VID_REG_UPDATE 0x00000002
21 # define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
22 # define CS5530_VCFG_8_BIT_4_2_0 0x00000004
23 # define CS5530_VCFG_16_BIT_4_2_0 0x00000008
24 # define CS5530_VCFG_GV_SEL 0x00000010
25 # define CS5530_VCFG_CSC_BYPASS 0x00000020
26 # define CS5530_VCFG_X_FILTER_EN 0x00000040
27 # define CS5530_VCFG_Y_FILTER_EN 0x00000080
[all …]
/linux/arch/arm/mach-imx/
H A Diim.h11 #define MXC_IIMSTAT 0x0000
12 #define MXC_IIMSTATM 0x0004
13 #define MXC_IIMERR 0x0008
14 #define MXC_IIMEMASK 0x000C
15 #define MXC_IIMFCTL 0x0010
16 #define MXC_IIMUA 0x0014
17 #define MXC_IIMLA 0x0018
18 #define MXC_IIMSDAT 0x001C
19 #define MXC_IIMPREV 0x0020
20 #define MXC_IIMSREV 0x0024
[all …]
/linux/arch/arm/mach-mmp/
H A Dregs-timers.h9 #define TMR_CCR (0x0000)
10 #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
11 #define TMR_CR(n) (0x0028 + ((n) << 2))
12 #define TMR_SR(n) (0x0034 + ((n) << 2))
13 #define TMR_IER(n) (0x0040 + ((n) << 2))
14 #define TMR_PLVR(n) (0x004c + ((n) << 2))
15 #define TMR_PLCR(n) (0x0058 + ((n) << 2))
16 #define TMR_WMER (0x0064)
17 #define TMR_WMR (0x0068)
18 #define TMR_WVR (0x006c)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_d.h26 #define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C
27 #define ixPB0_DFT_JIT_INJ_REG0 0x13000
28 #define ixPB0_DFT_JIT_INJ_REG1 0x13004
29 #define ixPB0_DFT_JIT_INJ_REG2 0x13008
30 #define ixPB0_GLB_CTRL_REG0 0x10004
31 #define ixPB0_GLB_CTRL_REG1 0x10008
32 #define ixPB0_GLB_CTRL_REG2 0x1000C
33 #define ixPB0_GLB_CTRL_REG3 0x10010
34 #define ixPB0_GLB_CTRL_REG4 0x10014
35 #define ixPB0_GLB_CTRL_REG5 0x10018
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_1_8_0_offset.h29 // base address: 0x3080
30 …ATC_ATS_CNTL 0x0000
31 …e regATC_ATS_CNTL_BASE_IDX 0
32 …ATC_ATS_CNTL2 0x0001
33 …e regATC_ATS_CNTL2_BASE_IDX 0
34 …ATC_ATS_CNTL3 0x0002
35 …e regATC_ATS_CNTL3_BASE_IDX 0
36 …ATC_ATS_CNTL4 0x0003
37 …e regATC_ATS_CNTL4_BASE_IDX 0
38 …ATC_ATS_MISC_CNTL 0x0005
[all …]

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