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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek-hw.yaml47 #size-cells = <0>;
49 cpu0: cpu@0 {
53 performance-domains = <&performance 0>;
54 reg = <0x000>;
66 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
/linux/Documentation/devicetree/bindings/dvfs/
H A Dperformance-domain.yaml37 Number of cells in a performance domain specifier. Typically 0 for nodes
42 enum: [ 0, 1 ]
60 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
71 #size-cells = <0>;
73 cpu@0 {
76 reg = <0x0 0x0>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]