Searched +full:0 +full:x0007642c (Results 1 – 13 of 13) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | sdhci-msm.txt | 11 For SDCC version 5.0.0, MCI registers are removed from SDCC 47 - pinctrl-0: Should specify pin control groups used for this controller. 84 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 85 interrupts = <0 123 0>; 93 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; 101 qcom,dll-config = <0x000f642c>; 102 qcom,ddr-config = <0x80040868>; 107 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 108 interrupts = <0 125 0>; 110 cd-gpios = <&msmgpio 62 0x1>; [all …]
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| H A D | sdhci-msm.yaml | 113 pinctrl-0: 164 '^opp-?[0-9]+$': 226 reg = <0 0x08804000 0 0x1000>; 236 iommus = <&apps_smmu 0x4a0 0x0>; 237 qcom,dll-config = <0x0007642c>; 238 qcom,ddr-config = <0x80040868>;
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sm6125.dtsi | 24 #clock-cells = <0>; 30 #clock-cells = <0>; 38 #size-cells = <0>; 40 CPU0: cpu@0 { 43 reg = <0x0 0x0>; 57 reg = <0x0 0x1>; 66 reg = <0x0 0x2>; 75 reg = <0x0 0x3>; 84 reg = <0x0 0x100>; 98 reg = <0x0 0x101>; [all …]
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| H A D | qdu1000.dtsi | 26 #size-cells = <0>; 28 CPU0: cpu@0 { 31 reg = <0x0 0x0>; 32 clocks = <&cpufreq_hw 0>; 36 qcom,freq-domains = <&cpufreq_hw 0>; 54 reg = <0x0 0x100>; 55 clocks = <&cpufreq_hw 0>; 59 qcom,freq-domains = <&cpufreq_hw 0>; 72 reg = <0x0 0x200>; 73 clocks = <&cpufreq_hw 0>; [all …]
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| H A D | qcm2290.dtsi | 31 #clock-cells = <0>; 37 #clock-cells = <0>; 43 #size-cells = <0>; 45 CPU0: cpu@0 { 48 reg = <0x0 0x0>; 49 clocks = <&cpufreq_hw 0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 67 reg = <0x0 0x1>; 68 clocks = <&cpufreq_hw 0>; 73 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sm6375.dtsi | 27 #clock-cells = <0>; 33 #clock-cells = <0>; 39 #size-cells = <0>; 41 CPU0: cpu@0 { 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 48 qcom,freq-domain = <&cpufreq_hw 0>; 70 reg = <0x0 0x100>; 71 clocks = <&cpufreq_hw 0>; 74 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sm6115.dtsi | 30 #clock-cells = <0>; 35 #clock-cells = <0>; 41 #size-cells = <0>; 43 CPU0: cpu@0 { 46 reg = <0x0 0x0>; 47 clocks = <&cpufreq_hw 0>; 52 qcom,freq-domain = <&cpufreq_hw 0>; 65 reg = <0x0 0x1>; 66 clocks = <&cpufreq_hw 0>; 71 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sc7280.dtsi | 81 #clock-cells = <0>; 87 #clock-cells = <0>; 98 reg = <0x0 0x004cd000 0x0 0x1000>; 102 reg = <0x0 0x80000000 0x0 0x600000>; 107 reg = <0x0 0x80600000 0x0 0x200000>; 112 reg = <0x0 0x80800000 0x0 0x60000>; 117 reg = <0x0 0x80860000 0x0 0x20000>; 123 reg = <0x0 0x80884000 0x0 0x10000>; 128 reg = <0x0 0x808ff000 0x0 0x1000>; 133 reg = <0x0 0x80900000 0x0 0x200000>; [all …]
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| H A D | sm6350.dtsi | 32 #clock-cells = <0>; 40 #clock-cells = <0>; 46 #size-cells = <0>; 48 CPU0: cpu@0 { 51 reg = <0x0 0x0>; 52 clocks = <&cpufreq_hw 0>; 57 qcom,freq-domain = <&cpufreq_hw 0>; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sm8150.dtsi | 34 #clock-cells = <0>; 41 #clock-cells = <0>; 49 #size-cells = <0>; 51 CPU0: cpu@0 { 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; [all …]
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| H A D | sm8550.dtsi | 38 #clock-cells = <0>; 43 #clock-cells = <0>; 47 #clock-cells = <0>; 55 #clock-cells = <0>; 65 #size-cells = <0>; 67 CPU0: cpu@0 { 70 reg = <0 0>; 71 clocks = <&cpufreq_hw 0>; 76 qcom,freq-domain = <&cpufreq_hw 0>; 96 reg = <0 0x100>; [all …]
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| H A D | sm8650.dtsi | 40 #clock-cells = <0>; 45 #clock-cells = <0>; 50 #clock-cells = <0>; 59 #clock-cells = <0>; 69 #size-cells = <0>; 71 CPU0: cpu@0 { 74 reg = <0 0>; 76 clocks = <&cpufreq_hw 0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 107 reg = <0 0x100>; [all …]
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| H A D | sm8250.dtsi | 80 #clock-cells = <0>; 88 #clock-cells = <0>; 94 #size-cells = <0>; 96 CPU0: cpu@0 { 99 reg = <0x0 0x0>; 100 clocks = <&cpufreq_hw 0>; 107 qcom,freq-domain = <&cpufreq_hw 0>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 115 cache-size = <0x20000>; 121 cache-size = <0x400000>; [all …]
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