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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqoriq-thermal.txt6 Register (IPBRR0) at offset 0x0BF8.
10 0x01900102 T1040
32 reg = <0xf0000 0x1000>;
33 interrupts = <18 2 0 0>;
34 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
35 fsl,tmu-calibration = <0x00000000 0x00000025
36 0x00000001 0x00000028
37 0x00000002 0x0000002d
38 0x00000003 0x00000031
39 0x00000004 0x00000036
[all …]
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dboss.ini20 { 0x00000030, 0x00000015, 0x00000015, 0x0000001d, 0x00000015 },
21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-lg-p880.dts17 pinctrl-0 = <&state_default>;
120 emc-timings-0 {
122 nvidia,ram-code = <0>;
127 nvidia,emem-configuration = < 0x00050001 0xc0000010
128 0x00000001 0x00000001 0x00000002 0x00000000
129 0x00000003 0x00000001 0x00000002 0x00000004
130 0x00000001 0x00000000 0x00000002 0x00000002
131 0x02020001 0x00060402 0x77230303 0x001f0000 >;
137 nvidia,emem-configuration = < 0x00020001 0xc0000010
138 0x00000001 0x00000001 0x00000002 0x00000000
[all …]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x00000002 0x00000004
126 0x00000001 0x00000000 0x00000002 0x00000002
127 0x02020001 0x00060402 0x77230303 0x001f0000 >;
133 nvidia,emem-configuration = < 0x00030003 0xc0000010
134 0x00000001 0x00000001 0x00000002 0x00000000
135 0x00000003 0x00000001 0x00000002 0x00000004
136 0x00000001 0x00000000 0x00000002 0x00000002
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe0000
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
94 <0x0 0x1404000 0 0x2000>, /* GICH */
[all …]
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
67 reg = <0x0 0x6020000 0 0x20000>;
73 reg = <0x0 0x1e60000 0x0 0x4>;
[all …]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212.ini21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
30 { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_main.c74 #define AL_ETH_TX_L4_PROTO_IDX_MASK 0x1F
86 #define AL_ETH_TX_META_L3_LEN_MASK 0xff
87 #define AL_ETH_TX_META_L3_OFF_MASK 0xff
91 #define AL_ETH_TX_META_OUTER_L3_LEN_MASK 0x1f
93 #define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK 0x18
95 #define AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK 0x07
99 #define AL_ETH_TX_MACSEC_SIGN_SHIFT 0 /* Sign TX pkt */
105 #define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT 10 /* Secure Payload Length (0x3FFF for non-S…
109 #define AL_ETH_RX_L3_PROTO_IDX_MASK 0x1F
112 #define AL_ETH_RX_L4_PROTO_IDX_MASK 0x1F
[all …]