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/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_hashfilter.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00010008/0x00010008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
[all …]
H A Dt6fw_cfg_fpga.txt34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
H A Dt6fw_cfg_uwire.txt34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
82 reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
[all …]
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqoriq-thermal.txt6 Register (IPBRR0) at offset 0x0BF8.
10 0x01900102 T1040
32 reg = <0xf0000 0x1000>;
33 interrupts = <18 2 0 0>;
34 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
35 fsl,tmu-calibration = <0x00000000 0x00000025
36 0x00000001 0x00000028
37 0x00000002 0x0000002d
38 0x00000003 0x00000031
39 0x00000004 0x00000036
[all …]
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0
[all...]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0x0 0x140100
[all...]
H A Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all...]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all...]
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all...]
H A Dfsl-ls208xa.dtsi33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x1000
[all...]
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x800
[all...]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x
[all...]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_dbg_values.h34 0x02, 0x00, 0x04, 0x00, 0x01, 0x09, 0x01, 0x08, 0x07, 0x02, 0x00, 0x01,
35 0x04, 0x05, 0x00, 0x01, 0x07, 0x09, 0x02, 0x00, 0x01, 0x04, 0x12, 0x00,
36 0x00, 0x06, 0x02, 0x00, 0x01, 0x04, 0x05, 0x00, 0x00, 0x06, 0x02, 0x00,
37 0x01, 0x05, 0x12, 0x00, 0x00, 0x06, 0x02, 0x00, 0x04, 0x00, 0x01, 0x09,
38 0x00, 0x06, 0x02, 0x00, 0x04, 0x02, 0x00, 0x0b, 0x0e, 0x00, 0x01, 0x00,
39 0x06, 0x01, 0x04, 0x05, 0x02, 0x00, 0x12, 0x00, 0x01, 0x07, 0x09, 0x02,
40 0x00, 0x04, 0x00, 0x01, 0x08, 0x07, 0x02, 0x00, 0x04, 0x00, 0x01, 0x07,
41 0x09, 0x02, 0x00, 0x04, 0x02, 0x00, 0x0b, 0x10, 0x02, 0x00, 0x04, 0x02,
42 0x00, 0x0b, 0x0f, 0x02, 0x04, 0x00, 0x01, 0x07, 0x09, 0x02, 0x00, 0x04,
43 0x02, 0x0b, 0x0e, 0x02, 0x00, 0x04, 0x00, 0x00, 0x06, 0x02, 0x04, 0x02,
[all …]
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_main.c74 #define AL_ETH_TX_L4_PROTO_IDX_MASK 0x1F
86 #define AL_ETH_TX_META_L3_LEN_MASK 0xff
87 #define AL_ETH_TX_META_L3_OFF_MASK 0xff
91 #define AL_ETH_TX_META_OUTER_L3_LEN_MASK 0x1f
93 #define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK 0x18
95 #define AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK 0x07
99 #define AL_ETH_TX_MACSEC_SIGN_SHIFT 0 /* Sign TX pkt */
105 #define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT 10 /* Secure Payload Length (0x3FFF for non-S…
109 #define AL_ETH_RX_L3_PROTO_IDX_MASK 0x1F
112 #define AL_ETH_RX_L4_PROTO_IDX_MASK 0x1F
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2700.h38 0x0501f06c, 0x00122000, 0x00100000, 0x00014f80,
39 0x00000009, 0x0000000c, 0x00000000, 0x785ad0d5,
40 0x00000040, 0x0000f206, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323220, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32377878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x30202024, 0x00000000, 0x0000002f, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00014f80, 0xffffffff, 0x00122004,
[all …]
H A Dasm_2800.h38 0x0501f078, 0x00124000, 0x00100000, 0x00017380,
39 0x00000009, 0x0000000c, 0x00000001, 0x785ad0d5,
40 0x00000080, 0x0001f626, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323320, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32387878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x31202024, 0x00000000, 0x00000092, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00017380, 0xffffffff, 0x00124004,
[all …]
/freebsd/sys/dev/arcmsr/
H A Darcmsr.h64 #define FALSE 0
67 # define INTR_ENTROPY 0
71 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */
[all …]