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12

/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-xiaomi-mocha.dts34 reg = <0 0x80000000 0 0x80000000>;
44 panel@0 {
46 reg = <0>;
60 #size-cells = <0>;
62 port@0 {
63 reg = <0>;
105 emc-timings-0 {
106 nvidia,ram-code = <0>;
196 pinctrl-0 = <&state_default>;
932 nvidia,adjust-baud-rates = <0 9600 100>,
[all …]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c28 * indirectly from the SDS offset at 0x2000. It is only required for
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
31 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
36 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
53 #define SERDES_PLL_INDIRECT_OFFSET 0x0000
54 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
55 #define SERDES_INDIRECT_OFFSET 0x0400
56 #define SERDES_LANE_STRIDE 0x0200
59 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
60 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
[all …]
/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.h20 } while (0)
22 __CSKY_INSN_FUNCS(br16, 0xfc00, 0x0400)
23 __CSKY_INSN_FUNCS(bt16, 0xfc00, 0x0800)
24 __CSKY_INSN_FUNCS(bf16, 0xfc00, 0x0c00)
25 __CSKY_INSN_FUNCS(jmp16, 0xffc3, 0x7800)
26 __CSKY_INSN_FUNCS(jsr16, 0xffc3, 0x7801)
27 __CSKY_INSN_FUNCS(lrw16, 0xfc00, 0x1000)
28 __CSKY_INSN_FUNCS(pop16, 0xffe0, 0x1480)
30 __CSKY_INSN_FUNCS(br32, 0x0000ffff, 0x0000e800)
31 __CSKY_INSN_FUNCS(bt32, 0x0000ffff, 0x0000e860)
[all …]
/linux/arch/sh/include/cpu-sh4/cpu/
H A Dmmu_context.h10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
12 #define MMU_TTB 0xFF000008 /* Translation table base register */
13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
17 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
23 #define MMU_ITLB_DATA_ARRAY 0xF3000000
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.h24 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
28 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
29 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
30 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
32 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
33 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
34 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
35 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
36 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
37 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
[all …]
/linux/drivers/firewire/
H A Dpacket-header-definitions.h15 #define ASYNC_HEADER_Q0_DESTINATION_MASK 0xffff0000
17 #define ASYNC_HEADER_Q0_TLABEL_MASK 0x0000fc00
19 #define ASYNC_HEADER_Q0_RETRY_MASK 0x00000300
21 #define ASYNC_HEADER_Q0_TCODE_MASK 0x000000f0
22 #define ASYNC_HEADER_Q0_PRIORITY_SHIFT 0
23 #define ASYNC_HEADER_Q0_PRIORITY_MASK 0x0000000f
25 #define ASYNC_HEADER_Q1_SOURCE_MASK 0xffff0000
27 #define ASYNC_HEADER_Q1_RCODE_MASK 0x0000f000
29 #define ASYNC_HEADER_Q1_RCODE_MASK 0x0000f000
30 #define ASYNC_HEADER_Q1_OFFSET_HIGH_SHIFT 0
[all …]
H A Dohci.h7 #define OHCI1394_Version 0x000
8 #define OHCI1394_GUID_ROM 0x004
9 #define OHCI1394_ATRetries 0x008
10 #define OHCI1394_CSRData 0x00C
11 #define OHCI1394_CSRCompareData 0x010
12 #define OHCI1394_CSRControl 0x014
13 #define OHCI1394_ConfigROMhdr 0x018
14 #define OHCI1394_BusID 0x01C
15 #define OHCI1394_BusOptions 0x020
16 #define OHCI1394_GUIDHi 0x024
[all …]
/linux/arch/mips/include/asm/xtalk/
H A Dxwidget.h18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
[all …]
/linux/sound/soc/ux500/
H A Dux500_msp_i2s.h30 #define MSP_BIG_ENDIAN 0x00000000
31 #define MSP_LITTLE_ENDIAN 0x00001000
32 #define MSP_UNEXPECTED_FS_ABORT 0x00000000
33 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
34 #define MSP_NON_MODE_BIT_MASK 0x00009000
37 #define RX_ENABLE 0x00000001
38 #define RX_FIFO_ENABLE 0x00000002
39 #define RX_SYNC_SRG 0x00000010
40 #define RX_CLK_POL_RISING 0x00000020
41 #define RX_CLK_SEL_SRG 0x0000004
[all...]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
H A Drt61pci.h20 #define RT2561s_PCI_ID 0x0301
21 #define RT2561_PCI_ID 0x0302
22 #define RT2661_PCI_ID 0x0401
27 #define RF5225 0x0001
28 #define RF5325 0x0002
29 #define RF2527 0x0003
30 #define RF2529 0x0004
41 #define CSR_REG_BASE 0x3000
42 #define CSR_REG_SIZE 0x04b0
43 #define EEPROM_BASE 0x0000
[all …]
/linux/drivers/scsi/aic94xx/
H A Daic94xx_reg_def.h22 #define CSEQ_MODE_PAGE_SIZE 0x200 /* CSEQ mode page size */
23 #define LmSEQ_MODE_PAGE_SIZE 0x200 /* LmSEQ mode page size */
24 #define LmSEQ_HOST_REG_SIZE 0x4000 /* LmSEQ Host Register size */
32 * CHIM Registers, Address Range : (0x00-0xFF)
34 #define COMBIST (REG_BASE_ADDR + 0x00)
37 #define L7BLKRST 0x80000000
38 #define L6BLKRST 0x40000000
39 #define L5BLKRST 0x20000000
40 #define L4BLKRST 0x10000000
41 #define L3BLKRST 0x08000000
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723x.h28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h6 #define MCDE_IMSCPP 0x00000104
7 #define MCDE_RISPP 0x00000114
8 #define MCDE_MISPP 0x00000124
9 #define MCDE_SISPP 0x00000134
11 #define MCDE_PP_VCMPA BIT(0)
21 #define MCDE_IMSCOVL 0x00000108
22 #define MCDE_RISOVL 0x00000118
23 #define MCDE_MISOVL 0x00000128
24 #define MCDE_SISOVL 0x00000138
27 #define MCDE_IMSCCHNL 0x0000010C
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10005388,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dtable.c8 0x800, 0x80040000,
9 0x804, 0x00000003,
10 0x808, 0x0000FC00,
11 0x80C, 0x0000000A,
12 0x810, 0x10001331,
13 0x814, 0x020C3D10,
14 0x818, 0x02200385,
15 0x81C, 0x00000000,
16 0x820, 0x01000100,
17 0x824, 0x00190204,
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.h9 #define BGMAC_DEV_CTL 0x000
10 #define BGMAC_DC_TSM 0x00000002
11 #define BGMAC_DC_CFCO 0x00000004
12 #define BGMAC_DC_RLSS 0x00000008
13 #define BGMAC_DC_MROR 0x00000010
14 #define BGMAC_DC_FCM_MASK 0x00000060
16 #define BGMAC_DC_NAE 0x00000080
17 #define BGMAC_DC_TF 0x00000100
18 #define BGMAC_DC_RDS_MASK 0x00030000
20 #define BGMAC_DC_TDS_MASK 0x000c0000
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dtable.c7 0x01c, 0x07000000,
8 0x800, 0x00040000,
9 0x804, 0x00008003,
10 0x808, 0x0000fc00,
11 0x80c, 0x0000000a,
12 0x810, 0x10005088,
13 0x814, 0x020c3d10,
14 0x818, 0x00200185,
15 0x81c, 0x00000000,
16 0x820, 0x01000000,
[all …]
/linux/arch/arm/mach-omap1/
H A Dusb.c54 int alt_pingroup = 0; in omap_otg_init()
59 syscon = omap_readl(OTG_SYSCON_1) & 0xffff; in omap_otg_init()
63 //omap_writew(0, OTG_IRQ_EN); in omap_otg_init()
66 if (config->pins[0] > 2) /* alt pingroup 2 */ in omap_otg_init()
68 syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); in omap_otg_init()
88 else if (config->pins[0]) in omap_otg_init()
89 pr_cont(", usb0 %d wires%s", config->pins[0], in omap_otg_init()
164 .end = UDC_BASE + 0xff,
178 static u64 udc_dmamask = ~(u32)0;
185 .coherent_dma_mask = 0xffffffff,
[all …]

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