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/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
17 reg = <0>;
61 reg = <0x6011000 0x20>;
70 reg = <0x10000000 0x4000000>;
75 #address-cells = <0>;
83 <0x00003 0x00003 0x00000008>,
84 <0x00004 0x00004 0x00000010>,
85 <0x00005 0x00005 0x00000200>,
86 <0x00006 0x00006 0x00000100>,
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi12 #size-cells = <0>;
15 cpu0: cpu@0 {
17 reg = <0>;
2611 l2_cache0: cache-controller-0 {
2784 <0x00003 0x00000000 0x00000010>,
2785 <0x00004 0x00000000 0x00000011>,
2786 <0x00005 0x00000000 0x00000007>,
2787 <0x00006 0x00000000 0x00000006>,
2788 <0x00008 0x00000000 0x00000027>,
2789 <0x00009 0x00000000 0x00000028>,
[all …]
/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h34 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
41 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
42 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
43 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
44 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
45 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
47 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
48 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
49 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192f.c18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
19 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
20 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
21 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
22 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
23 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
24 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
25 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
26 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
27 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723d.c19 #define WLAN_SLOT_TIME 0x09
20 #define WLAN_RL_VAL 0x3030
21 #define WLAN_BAR_VAL 0x0201ffff
22 #define BIT_MASK_TBTT_HOLD 0x00000fff
24 #define BIT_MASK_TBTT_SETUP 0x000000ff
25 #define BIT_SHIFT_TBTT_SETUP 0
30 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
31 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
32 #define WLAN_PIFS_VAL 0
33 #define WLAN_AGG_BRK_TIME 0x16
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c28 * indirectly from the SDS offset at 0x2000. It is only required for
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
31 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
36 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
53 #define SERDES_PLL_INDIRECT_OFFSET 0x0000
54 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
55 #define SERDES_INDIRECT_OFFSET 0x0400
56 #define SERDES_LANE_STRIDE 0x0200
59 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
60 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
[all …]