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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-karo-tx25.dts17 reg_fec_phy: regulator-0 {
22 gpio = <&gpio4 9 0>;
28 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
35 MX25_PAD_UART1_TXD__UART1_TXD 0x00000020
36 MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0
37 MX25_PAD_UART1_CTS__UART1_CTS 0x00000060
38 MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0
44 MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */
45 MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */
46 MX25_PAD_FEC_MDC__FEC_MDC 0x00000060
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstb0899_reg.h14 #define STB0899_DEV_ID 0xf000
15 #define STB0899_CHIP_ID (0x0f << 4)
18 #define STB0899_CHIP_REL (0x0f << 0)
19 #define STB0899_OFFST_CHIP_REL 0
22 #define STB0899_DEMOD 0xf40e
23 #define STB0899_MODECOEFF (0x01 << 0)
24 #define STB0899_OFFST_MODECOEFF 0
27 #define STB0899_RCOMPC 0xf410
28 #define STB0899_AGC1CN 0xf412
29 #define STB0899_AGC1REF 0xf413
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp-mek.dts27 mboxes = <&lsio_mu5 0 1
34 fsl,entry-address = <0x34fe0000>;
40 reg = <0x00000000 0x80000000 0 0x40000000>;
55 pinctrl-0 = <&pinctrl_typec_mux>;
69 mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */
72 #size-cells = <0>;
74 i2c@0 {
75 reg = <0>;
77 #size-cells = <0>;
81 reg = <0x1a>;
[all …]
H A Dimx8dxl-evk.dts31 mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
36 fsl,entry-address = <0x34fe0000>;
42 reg = <0x00000000 0x80000000 0 0x40000000>;
54 * reg = <0 0x96000000 0 0x2000000>;
63 size = <0 0x14000000>;
64 alloc-ranges = <0 0x98000000 0 0x14000000>;
69 reg = <0 0x90000000 0 0x8000>;
74 reg = <0 0x90008000 0 0x8000>;
79 reg = <0 0x90010000 0 0x8000>;
84 reg = <0 0x90018000 0 0x8000>;
[all …]
H A Dimx8qm-mek.dts32 reg = <0x00000000 0x80000000 0 0x40000000>;
37 #clock-cells = <0>;
48 reg = <0 0x90000000 0 0x8000>;
53 reg = <0 0x90008000 0 0x8000>;
58 reg = <0 0x90010000 0 0x8000>;
63 reg = <0 0x90018000 0 0x8000>;
68 reg = <0 0x900ff000 0 0x1000>;
73 reg = <0 0x90100000 0 0x8000>;
78 reg = <0 0x90108000 0 0x8000>;
83 reg = <0 0x90110000 0 0x8000>;
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Divb_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x0000002c,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
H A Dhsw_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x00000160,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
/linux/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h110 PAS_MAC_CFG_PCFG = 0x80,
111 PAS_MAC_CFG_MACCFG = 0x84,
112 PAS_MAC_CFG_ADR0 = 0x8c,
113 PAS_MAC_CFG_ADR1 = 0x90,
114 PAS_MAC_CFG_TXP = 0x98,
115 PAS_MAC_CFG_RMON = 0x100,
116 PAS_MAC_IPC_CHNL = 0x208,
120 #define PAS_MAC_CFG_PCFG_PE 0x80000000
121 #define PAS_MAC_CFG_PCFG_CE 0x40000000
122 #define PAS_MAC_CFG_PCFG_BU 0x20000000
[all …]
/linux/arch/m68k/include/asm/
H A Dm54xxacr.h12 #define CACR_DEC 0x80000000 /* Enable data cache */
13 #define CACR_DWP 0x40000000 /* Data write protection */
14 #define CACR_DESB 0x20000000 /* Enable data store buffer */
15 #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
18 #define CACR_DDCM_CP 0x02000000 /* Copyback cache */
19 #define CACR_DDCM_P 0x04000000 /* No cache, precise */
20 #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
21 #define CACR_DCINVA 0x01000000 /* Invalidate data cache */
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl176e.h5 #define NV176E_SET_OBJECT (0x00000000)
6 #define NV176E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
7 #define NV176E_SEMAPHORE_OFFSET (0x00000064)
8 #define NV176E_SEMAPHORE_ACQUIRE (0x00000068)
9 #define NV176E_SEMAPHORE_RELEASE (0x0000006c)
H A Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
H A Dcl826f.h26 #define NV826F_SEMAPHOREA (0x00000010)
27 #define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0
28 #define NV826F_SEMAPHOREB (0x00000014)
30 #define NV826F_SEMAPHOREC (0x00000018)
31 #define NV826F_SEMAPHOREC_PAYLOAD 31:0
32 #define NV826F_SEMAPHORED (0x0000001C)
33 #define NV826F_SEMAPHORED_OPERATION 2:0
34 #define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
35 #define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002
36 #define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
[all …]
H A Dclc36f.h8 #define NVC36F_NON_STALL_INTERRUPT (0x00000020)
9 #define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
15 #define NVC36F_MEM_OP_A (0x00000028)
16 #define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant fo…
17 #define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify …
19 #define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant fo…
21 #define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
22 #define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
24 #define NVC36F_MEM_OP_B (0x0000002c)
25 #define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-lg-p895.dts12 pinctrl-0 = <&state_default>;
123 nvidia,emem-configuration = < 0x00020001 0xc0000010
124 0x00000001 0x00000001 0x00000002 0x00000000
125 0x00000003 0x00000001 0x00000002 0x00000004
126 0x00000001 0x00000000 0x00000002 0x00000002
127 0x02020001 0x00060402 0x77230303 0x001f0000 >;
133 nvidia,emem-configuration = < 0x00030003 0xc0000010
134 0x00000001 0x00000001 0x00000002 0x00000000
135 0x00000003 0x00000001 0x00000002 0x00000004
136 0x00000001 0x00000000 0x00000002 0x00000002
[all …]
/linux/arch/powerpc/include/asm/
H A Dfsl_lbc.h22 #define BR_BA 0xFFFF8000
24 #define BR_PS 0x00001800
26 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
27 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
28 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
29 #define BR_DECC 0x00000600
31 #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
32 #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
33 #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
34 #define BR_WP 0x00000100
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.h12 #define SXGBE_MTL_OPMODE_ESTMASK 0x3
13 #define SXGBE_MTL_OPMODE_RAAMASK 0x1
14 #define SXGBE_MTL_FCMASK 0x7
20 #define SXGBE_MTL_ENABLE_FC 0x80
22 #define ETS_WRR 0xFFFFFF9F
23 #define ETS_RST 0xFFFFFF9F
24 #define ETS_WFQ 0x00000020
25 #define ETS_DWRR 0x00000040
26 #define RAA_SP 0xFFFFFFFB
27 #define RAA_WSP 0x00000004
[all …]
/linux/sound/pci/vx222/
H A Dvx222.h32 #define VX2_AKM_LEVEL_MAX 0x93
38 #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008
41 #define VX_INTCSR_VALUE 0x00000001
42 #define VX_PCI_INTERRUPT_MASK 0x00000040
44 /* Constants used to access the CDSP register (0x20). */
45 #define VX_CDSP_TEST1_MASK 0x00000080
46 #define VX_CDSP_TOR1_MASK 0x00000040
47 #define VX_CDSP_TOR2_MASK 0x00000020
48 #define VX_CDSP_RESERVED0_0_MASK 0x00000010
49 #define VX_CDSP_CODEC_RESET_MASK 0x00000008
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/linux/arch/arm/nwfpe/
H A Dfpsr.h32 #define MASK_SYSID 0xff000000
33 #define BIT_HARDWARE 0x80000000
34 #define FP_EMULATOR 0x01000000 /* System ID for emulator */
35 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
40 #define MASK_TRAP_ENABLE 0x00ff0000
41 #define MASK_TRAP_ENABLE_STRICT 0x001f0000
42 #define BIT_IXE 0x00100000 /* inexact exception enable */
43 #define BIT_UFE 0x00080000 /* underflow exception enable */
44 #define BIT_OFE 0x00040000 /* overflow exception enable */
45 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
[all …]
/linux/drivers/net/usb/
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux/sound/firewire/motu/
H A Dmotu-protocol-v1.c10 // Status register for MOTU 828 (0x'ffff'f000'0b00).
12 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
13 // 0x00008000: mode of optical input interface.
14 // 0x00008000: for S/PDIF signal.
15 // 0x00000000: disabled or for ADAT signal.
16 // 0x00004000: mode of optical output interface.
17 // 0x00004000: for S/PDIF signal.
18 // 0x00000000: disabled or for ADAT signal.
19 // 0x00003f00: monitor input mode.
20 // 0x00000800: analog-1/2
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_10_0_default.h26 #define mmTHM_TCON_CUR_TMP_DEFAULT 0x00000000
27 #define mmTHM_TCON_HTC_DEFAULT 0x00004000
28 #define mmTHM_TCON_THERM_TRIP_DEFAULT 0x00000001
29 #define mmTHM_CTF_DELAY_DEFAULT 0x00000000
30 #define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT 0x000000f9
31 #define mmTHM_THERMAL_INT_ENA_DEFAULT 0x00000000
32 #define mmTHM_THERMAL_INT_CTRL_DEFAULT 0x0fff0078
33 #define mmTHM_THERMAL_INT_STATUS_DEFAULT 0x00000000
34 #define mmTHM_TMON0_RDIL0_DATA_DEFAULT 0x00000000
35 #define mmTHM_TMON0_RDIL1_DATA_DEFAULT 0x00000000
[all …]
/linux/arch/sparc/include/uapi/asm/
H A Dperfctr.h58 #define PRIV 0x00000001
59 #define SYS 0x00000002
60 #define USR 0x00000004
63 #define CYCLE_CNT 0x00000000
64 #define INSTR_CNT 0x00000010
65 #define DISPATCH0_IC_MISS 0x00000020
66 #define DISPATCH0_STOREBUF 0x00000030
67 #define IC_REF 0x00000080
68 #define DC_RD 0x00000090
69 #define DC_WR 0x000000A0
[all …]

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