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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqoriq-thermal.txt6 Register (IPBRR0) at offset 0x0BF8.
10 0x01900102 T1040
32 reg = <0xf0000 0x1000>;
33 interrupts = <18 2 0 0>;
34 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
35 fsl,tmu-calibration = <0x00000000 0x00000025
36 0x00000001 0x00000028
37 0x00000002 0x0000002d
38 0x00000003 0x00000031
39 0x00000004 0x00000036
[all …]
H A Dqoriq-thermal.yaml20 Register (IPBRR0) at offset 0x0BF8.
24 0x01900102 T1040
82 reg = <0xf0000 0x1000>;
83 interrupts = <18 2 0 0>;
84 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
85 fsl,tmu-calibration = <0x00000000 0x00000025>,
86 <0x00000001 0x00000028>,
87 <0x00000002 0x0000002d>,
88 <0x00000003 0x00000031>,
89 <0x00000004 0x00000036>,
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_tx_desc.h28 #define R92C_FLAGS0_BMCAST 0x01
29 #define R92C_FLAGS0_LSG 0x04
30 #define R92C_FLAGS0_FSG 0x08
31 #define R92C_FLAGS0_OWN 0x80
34 #define R92C_TXDW1_MACID_M 0x0000001f
35 #define R92C_TXDW1_MACID_S 0
36 #define R92C_TXDW1_AGGEN 0x00000020
37 #define R92C_TXDW1_AGGBK 0x00000040
39 #define R92C_TXDW1_QSEL_M 0x00001f00
42 #define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */
[all …]
H A Dr92c_rx_desc.h26 #define R92C_RXDW0_PKTLEN_M 0x00003fff
27 #define R92C_RXDW0_PKTLEN_S 0
28 #define R92C_RXDW0_CRCERR 0x00004000
29 #define R92C_RXDW0_ICVERR 0x00008000
30 #define R92C_RXDW0_INFOSZ_M 0x000f0000
32 #define R92C_RXDW0_CIPHER_M 0x00700000
34 #define R92C_RXDW0_QOS 0x00800000
35 #define R92C_RXDW0_SHIFT_M 0x03000000
37 #define R92C_RXDW0_PHYST 0x04000000
38 #define R92C_RXDW0_SWDEC 0x08000000
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x4451147
[all...]
/freebsd/sys/dev/rtwn/rtl8192c/usb/
H A Dr92cu_priv.h29 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
30 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
31 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
32 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
33 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
34 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
35 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
36 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 },
37 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff },
38 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_ec_regs.h60 /* [0x0] Ethernet controller Version */
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
66 /* [0xc] General L2 configuration for the Ethernet controlle ... */
68 /* [0x10] Configure protocol index values */
70 /* [0x14] Configure protocol index values (extended protocols ... */
72 /* [0x18] Enable modules operation (extended operations). */
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
[all …]
/freebsd/sys/arm/allwinner/
H A Daw_rtc.c50 #define LOSC_CTRL_REG 0x00
51 #define A10_RTC_DATE_REG 0x04
52 #define A10_RTC_TIME_REG 0x08
53 #define A31_LOSC_AUTO_SWT_STA 0x04
54 #define A31_RTC_DATE_REG 0x10
55 #define A31_RTC_TIME_REG 0x14
57 #define TIME_MASK 0x001f3f3f
59 #define LOSC_OSC_SRC (1 << 0)
62 #define LOSC_MAGIC 0x16aa0000
63 #define LOSC_BUSY_MASK 0x00000380
[all …]
/freebsd/sys/arm/include/
H A Darmreg.h44 #define PSR_MODE 0x0000001f /* mode mask */
45 #define PSR_USR32_MODE 0x00000010
46 #define PSR_FIQ32_MODE 0x00000011
47 #define PSR_IRQ32_MODE 0x00000012
48 #define PSR_SVC32_MODE 0x00000013
49 #define PSR_MON32_MODE 0x00000016
50 #define PSR_ABT32_MODE 0x00000017
51 #define PSR_HYP32_MODE 0x0000001a
52 #define PSR_UND32_MODE 0x0000001
[all...]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_dtsec_mii_acc.h40 #define MIIMCFG_RESET_MGMT 0x80000000
41 #define MIIMCFG_MGNTCLK_MASK 0x00000007
42 #define MIIMCFG_MGNTCLK_SHIFT 0
45 #define MIIMCOM_SCAN_CYCLE 0x00000002
46 #define MIIMCOM_READ_CYCLE 0x00000001
50 #define MIIMADD_PHY_ADDR_MASK 0x00001f00
52 #define MIIMADD_REG_ADDR_SHIFT 0
53 #define MIIMADD_REG_ADDR_MASK 0x0000001f
56 #define MIIMIND_BUSY 0x00000001
60 #define PHY_CR_PHY_RESET 0x8000
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211phy.h27 #define AR_PHY_BASE 0x9800 /* PHY registers base address */
30 #define AR_PHY_TURBO 0x9804 /* PHY frame control register */
31 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
32 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
34 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */
36 #define AR_PHY_ACTIVE 0x981C /* PHY activation register */
37 #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */
38 #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */
40 #define AR_PHY_AGC_CONTROL 0x9860 /* PHY chip calibration and noise floor setting */
41 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* Perform PHY chip internal calibration */
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82575.h56 #define E1000_SW_SYNCH_MB 0x00000100
57 #define E1000_STAT_DEV_RST_SET 0x00100000
81 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
82 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
83 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
84 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
85 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
86 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
87 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
88 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
[all …]
/freebsd/tools/test/iconv/ref/
H A DMACARABIC1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACHEBREW1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACUKRAINE1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACCENTRALEUROPE1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACCYRILLIC1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACCROATIAN1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACGREEK1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACICELAND1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACROMAN1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACROMANIA1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
H A DMACTURKISH1 0x00 = 0x00000000
2 0x01 = 0x00000001
3 0x02 = 0x00000002
4 0x03 = 0x00000003
5 0x04 = 0x00000004
6 0x05 = 0x00000005
7 0x06 = 0x00000006
8 0x07 = 0x00000007
9 0x08 = 0x00000008
10 0x09 = 0x00000009
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]

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