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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager_vi.c57 * LDS: X0000000'00000000 - X0000001'00000000 (4GB) in compute_sh_mem_bases_64bit()
58 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) in compute_sh_mem_bases_64bit()
61 * (where X/Y is the configurable nybble with the low-bit 0) in compute_sh_mem_bases_64bit()
71 WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || in compute_sh_mem_bases_64bit()
72 top_address_nybble == 0); in compute_sh_mem_bases_64bit()
115 if (qpd->sh_mem_config == 0) { in update_qpd_vi()
124 qpd->sh_mem_ape1_limit = 0; in update_qpd_vi()
125 qpd->sh_mem_ape1_base = 0; in update_qpd_vi()
134 pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n", in update_qpd_vi()
137 return 0; in update_qpd_vi()
H A Dkfd_device_queue_manager_cik.c57 * LDS: X0000000'00000000 - X0000001'00000000 (4GB) in compute_sh_mem_bases_64bit()
58 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) in compute_sh_mem_bases_64bit()
61 * (where X/Y is the configurable nybble with the low-bit 0) in compute_sh_mem_bases_64bit()
71 WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || in compute_sh_mem_bases_64bit()
72 top_address_nybble == 0); in compute_sh_mem_bases_64bit()
113 if (qpd->sh_mem_config == 0) { in update_qpd_cik()
118 qpd->sh_mem_ape1_limit = 0; in update_qpd_cik()
119 qpd->sh_mem_ape1_base = 0; in update_qpd_cik()
128 pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", in update_qpd_cik()
131 return 0; in update_qpd_cik()
/linux/arch/x86/events/intel/
H A Dp4.c20 * array indices: 0,1 - HT threads, used with HT enabled cpu
51 P4_GEN_PEBS_BIND(1stl_cache_load_miss_retired, 0x0000001, 0x0000001),
52 P4_GEN_PEBS_BIND(2ndl_cache_load_miss_retired, 0x0000002, 0x0000001),
53 P4_GEN_PEBS_BIND(dtlb_load_miss_retired, 0x0000004, 0x0000001),
54 P4_GEN_PEBS_BIND(dtlb_store_miss_retired, 0x0000004, 0x0000002),
55 P4_GEN_PEBS_BIND(dtlb_all_miss_retired, 0x0000004, 0x0000003),
56 P4_GEN_PEBS_BIND(tagged_mispred_branch, 0x0018000, 0x0000010),
57 P4_GEN_PEBS_BIND(mob_load_replay_retired, 0x0000200, 0x0000001),
58 P4_GEN_PEBS_BIND(split_load_retired, 0x0000400, 0x0000001),
59 P4_GEN_PEBS_BIND(split_store_retired, 0x0000400, 0x0000002),
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/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S120 ALT_FTR_SECTION_END(0, 1)
140 2: PPC_LCMPI r3,0
152 ALT_FTR_SECTION_END(0, 1)
190 ALT_FTR_SECTION_END(0, 1)
208 #if 0
210 * reports an error. #if 0'ed so as not to break the build normally.
223 ALT_FTR_SECTION_END(0, 1)
235 END_##TYPE##_SECTION(0, 1) \
243 END_##TYPE##_SECTION(0, 0) \
253 END_##TYPE##_SECTION_NESTED(0, 1, 80) \
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/linux/drivers/scsi/lpfc/
H A Dlpfc_hw4.h36 * #define example_bit_field_MASK 0x03
47 * bf_set(example_bit_field, &t1, 0);
63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF)
64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF)
79 #define lpfc_sli_intf_valid_MASK 0x00000007
83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
93 #define lpfc_sli_intf_if_type_MASK 0x0000000F
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H A Dlpfc_sli4.h37 #define LPFC_SKIP_UNREG_FCF 0
46 #define LPFC_HBA_HDWQ_MIN 0
51 #define LPFC_IRQ_CHANN_MIN 0
56 #define LPFC_FCP_MQ_THRESHOLD_MIN 0
65 #define LPFC_FCOE_FCF_DEF_INDEX 0
66 #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
67 #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
69 #define LPFC_FCOE_NULL_VID 0xFFF
70 #define LPFC_FCOE_IGNORE_VID 0xFFFF
73 #define LPFC_FCOE_FCF_MAC3 0xFF
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/linux/Documentation/devicetree/bindings/arm/
H A Dpsci.yaml29 to #0.
70 # HVC #0, with the register assignments specified in this binding.
118 It should also be noted that, in PSCI firmware v1.0 the OS-Initiated
151 cpu_suspend = <0x95c10000>;
152 cpu_off = <0x95c10001>;
153 cpu_on = <0x95c10002>;
154 migrate = <0x95c10003>;
182 cpu_on = <0x95c10002>;
183 cpu_off = <0x95c10001>;
191 #size-cells = <0>;
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/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
H A Dkaweth.c57 #define KAWETH_STATUS_BROKEN 0x0000001
58 #define KAWETH_STATUS_CLOSING 0x0000002
59 #define KAWETH_STATUS_SUSPENDING 0x0000004
63 #define KAWETH_PACKET_FILTER_PROMISCUOUS 0x01
64 #define KAWETH_PACKET_FILTER_ALL_MULTICAST 0x02
65 #define KAWETH_PACKET_FILTER_DIRECTED 0x04
66 #define KAWETH_PACKET_FILTER_BROADCAST 0x08
67 #define KAWETH_PACKET_FILTER_MULTICAST 0x10
70 #define KAWETH_COMMAND_GET_ETHERNET_DESC 0x00
71 #define KAWETH_COMMAND_MULTICAST_FILTERS 0x01
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
[all …]
/linux/include/linux/greybus/
H A Dgreybus_protocols.h15 #define GB_SVC_DEVICE_ID_SVC 0
20 #define GB_SVC_CPORT_ID 0
21 #define GB_CONTROL_BUNDLE_ID 0
22 #define GB_CONTROL_CPORT_ID 0
32 * (0x80) of the operation type field is used to indicate whether
56 #define GB_REQUEST_TYPE_CPORT_SHUTDOWN 0x00
57 #define GB_REQUEST_TYPE_INVALID 0x7f
67 #define GB_CONTROL_TYPE_VERSION 0x01
68 #define GB_CONTROL_TYPE_PROBE_AP 0x02
69 #define GB_CONTROL_TYPE_GET_MANIFEST_SIZE 0x03
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/linux/sound/soc/codecs/
H A Dtas2781-fmwlib.c25 #define ERROR_PRAM_CRCCHK 0x0000000
26 #define ERROR_YRAM_CRCCHK 0x0000001
27 #define PPC_DRIVER_CRCCHK 0x00000200
29 #define TAS2781_SA_COEFF_SWAP_REG TASDEVICE_REG(0, 0x35, 0x2c)
44 #define TAS2781_YRAM_BOOK2 0
55 #define MAIN_ALL_DEVICES_1X 0x01
56 #define MAIN_DEVICE_A_1X 0x02
57 #define MAIN_DEVICE_B_1X 0x03
58 #define MAIN_DEVICE_C_1X 0x04
59 #define MAIN_DEVICE_D_1X 0x05
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/linux/drivers/net/ethernet/nvidia/
H A Dforcedeth.c66 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet form…
69 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
[all …]