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12

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c49 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
50 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
51 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
54 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
55 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
56 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
57 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
58 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
H A Dsi.c61 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 mmDB_DEBUG, 0xffffffff, 0x00000000,
64 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 0x340c, 0x000000c0, 0x00800040,
68 0x360c, 0x000000c0, 0x00800040,
69 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
H A Dgmc_v8_0.c68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
[all …]
H A Dgmc_v7_0.c62 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
63 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
64 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
65 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
69 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
74 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers()
102 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
105 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_stop()
118 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
121 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
[all …]
/linux/arch/parisc/kernel/
H A Dperf_images.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Imagine for use with the Onyx (PCX-U) CPU interface
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * It can be changed with DIP switch(S2-5).
9 * phys address | S2-5 = OFF | S2-5 = ON
10 * -----------------------------+---------------+---------------
11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
[all …]
/linux/drivers/scsi/mpi3mr/mpi/
H A Dmpi30_transport.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2016-2023 Broadcom Inc. All rights reserved.
20 #define MPI3_VERSION_MINOR (0)
22 #define MPI3_VERSION_DEV (0)
23 #define MPI3_DEVHANDLE_INVALID (0xffff)
73 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
74 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
75 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
77 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
78 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
30 "#address-cells":
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h1 /* SPDX-License-Identifier: MIT */
5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
[all …]
/linux/arch/mips/include/asm/mach-malta/
H A Dspaces.h17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
/linux/arch/mips/pic32/pic32mzda/
H A Dconfig.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <asm/mach-pic32/pic32.h>
14 #define PIC32_CFGCON 0x0000
15 #define PIC32_DEVID 0x0020
16 #define PIC32_SYSKEY 0x0030
17 #define PIC32_CFGEBIA 0x00c0
18 #define PIC32_CFGEBIC 0x00d0
19 #define PIC32_CFGCON2 0x00f0
20 #define PIC32_RCON 0x1240
49 return 0; in pic32_conf_modify_atomic()
[all …]
/linux/sound/pci/ctxfi/
H A Dcthw20k2.c1 // SPDX-License-Identifier: GPL-2.0-only
48 #define SRCCTL_STATE 0x00000007
49 #define SRCCTL_BM 0x00000008
50 #define SRCCTL_RSR 0x00000030
51 #define SRCCTL_SF 0x000001C0
52 #define SRCCTL_WR 0x00000200
53 #define SRCCTL_PM 0x00000400
54 #define SRCCTL_ROM 0x00001800
55 #define SRCCTL_VO 0x00002000
56 #define SRCCTL_ST 0x00004000
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h1 /* SPDX-License-Identifier: MIT */
3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2007-2011, Intel Corporation.
45 * to the different groups of PowerVR 5-series chip designs
47 * 0x8086 = Intel Corporation
49 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
50 * PowerVR SGX535 - Moorestown - Intel GMA 600
51 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
53 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
58 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
46 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, in nv50_gr_object_bind()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
72 struct nv50_gr *gr = nv50_gr_chan(object)->gr; in nv50_gr_chan_bind()
73 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in nv50_gr_chan_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
[all …]
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
17 #include <linux/mdio-bitbang.h>
39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
60 if (rdev->family == CHIP_RV740) in rv770_set_uvd_clocks()
71 return 0; in rv770_set_uvd_clocks()
75 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
81 vclk_div -= 1; in rv770_set_uvd_clocks()
82 dclk_div -= 1; in rv770_set_uvd_clocks()
84 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
90 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
[all …]
H A Dsi.c159 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
160 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
161 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
164 (0x8000 << 16) | (0x98f4 >> 2),
165 0x00000000,
166 (0x8040 << 16) | (0x98f4 >> 2),
167 0x00000000,
168 (0x8000 << 16) | (0xe80 >> 2),
169 0x00000000,
170 (0x8040 << 16) | (0xe80 >> 2),
[all …]
H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
H A Devergreen.c50 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
51 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
52 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
62 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
63 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
65 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
73 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
74 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
76 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
84 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
[all …]
H A Dcik.c144 * cik_get_allowed_info_register - fetch the register for the info ioctl
150 * Returns 0 for success or -EINVAL for an invalid register
170 return 0; in cik_get_allowed_info_register()
172 return -EINVAL; in cik_get_allowed_info_register()
184 spin_lock_irqsave(&rdev->didt_idx_lock, flags); in cik_didt_rreg()
187 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); in cik_didt_rreg()
195 spin_lock_irqsave(&rdev->didt_idx_lock, flags); in cik_didt_wreg()
198 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); in cik_didt_wreg()
205 int actual_temp = 0; in ci_get_temp()
210 if (temp & 0x200) in ci_get_temp()
[all …]
/linux/drivers/message/fusion/lsi/
H A Dmpi_log_sas.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2000-2008 LSI Corporation. All rights reserved. *
7 * ------------ *
10 *-------------------------------------------------------------------------*
16 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
17 #define SAS_LOGINFO_MASK 0xFFFF0000
20 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
22 /* Bits 31-28: MPI_IOCLOGINFO_TYPE_SAS (3) */
23 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
24 /* Bits 23-16: LOGINFO_CODE */
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_initvals.h2 * Copyright (c) 2010-2011 Atheros Communications Inc.
19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
[all …]

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