| /freebsd/sys/contrib/dev/rtw89/ |
| H A D | rtw8852b_rfk_table.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
[all …]
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| H A D | rtw8852c_rfk_table.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x
[all...] |
| H A D | rtw8851b_rfk_table.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
[all …]
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| H A D | rtw8852b_table.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
10 {0x704, 0x601E0100},
11 {0x4000, 0x0000000
[all...] |
| H A D | rtw8852c_table.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
10 {0xF0FF0000, 0x00000000},
11 {0xF03300F
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | faraday,ftpci100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
21 The plain variant has 128MiB of non-prefetchable memory space, whereas the
27 and should point to respective interrupt in that controller in its interrupt-map.
29 The code which is the only documentation of how the Faraday PCI (the non-dual
34 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
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| H A D | faraday,ftpci100.txt | 9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
14 - compatible: ranging from specific to generic, should be one of
15 "cortina,gemini-pci", "faraday,ftpci100"
16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual"
18 "faraday,ftpci100-dual"
19 - reg: memory base and size for the host bridge
20 - #address-cells: set to <3>
21 - #size-cells: set to <2>
22 - #interrupt-cells: set to <1>
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/gemini/ |
| H A D | gemini.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
20 compatible = "cortina,gemini-flash", "cfi-flash";
[all …]
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| /freebsd/sys/dev/bhnd/cores/pmu/ |
| H A D | bhnd_pmureg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
10 * distributed with the Asus RT-N16 firmware source code release.
29 (((_value) & _flag) != 0)
40 * Common per-core clock control/status register available on PMU-equipped
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | sam9x7.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
10 #include <dt-bindings/clock/at91.h>
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17 #include <dt-bindings/pinctrl/at91.h>
[all …]
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| /freebsd/sys/dev/ispfw/ |
| H A D | asm_2700.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2022 by Qlogic, Inc.
38 0x0501f06c, 0x00122000, 0x00100000, 0x00014f80,
39 0x00000009, 0x0000000c, 0x00000000, 0x785ad0d5,
40 0x00000040, 0x0000f206, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323220, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32377878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
[all …]
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| H A D | asm_2800.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2023 by Qlogic, Inc.
38 0x0501f078, 0x00124000, 0x00100000, 0x00017380,
39 0x00000009, 0x0000000c, 0x00000001, 0x785ad0d5,
40 0x00000080, 0x0001f626, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323320, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32387878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
[all …]
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| H A D | asm_2500.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2019 by Qlogic, Inc.
38 0x0501f06b, 0x00115000, 0x00100000, 0x0000c8ea,
39 0x00000008, 0x00000008, 0x000000cf, 0x00109095,
40 0x00000004, 0x00000000, 0x20434f50, 0x59524947,
41 0x48542032, 0x30313920, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32357878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020382e, 0x30382e32,
[all …]
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| H A D | asm_2400.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2014 by Qlogic, Inc.
33 0x0401f1be, 0x00112000, 0x00100000, 0x0000c79b,
34 0x00000008, 0x00000007, 0x00000000, 0x00009496,
35 0x00000003, 0x00000000, 0x20434f50, 0x59524947,
36 0x48542032, 0x30313720, 0x514c4f47, 0x49432043,
37 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
38 0x32347878, 0x20466972, 0x6d776172, 0x65202020,
39 0x56657273, 0x696f6e20, 0x2020382e, 0x30372e30,
[all …]
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| H A D | asm_2600.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2005-2019 by Qlogic, Inc.
38 0x0501f06c, 0x0011b000, 0x00100000, 0x00011c0f,
39 0x00000008, 0x00000008, 0x000000e7, 0x0078d0d5,
40 0x00000020, 0x00000006, 0x20434f50, 0x59524947,
41 0x48542032, 0x30313920, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x38337878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020382e, 0x30382e32,
[all …]
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| /freebsd/sys/dev/bxe/ |
| H A D | 57711_init_values.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
30 /* clang-format off */
34 * OP_WR - write a single register.
35 * OP_RD - read a single register.
36 * OP_SW - write an array to consecutive registers.
37 * OP_WB - write an array using DMAE.
38 * OP_ZR - clear consecutive registers.
39 * OP_WB_ZR - clear consecutive registers using DMAE.
[all …]
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| H A D | 57710_init_values.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
30 /* clang-format off */
34 * OP_WR - write a single register.
35 * OP_RD - read a single register.
36 * OP_SW - write an array to consecutive registers.
37 * OP_WB - write an array using DMAE.
38 * OP_ZR - clear consecutive registers.
39 * OP_WB_ZR - clear consecutive registers using DMAE.
[all …]
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| H A D | 57712_init_values.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
30 /* clang-format off */
34 * OP_WR - write a single register.
35 * OP_RD - read a single register.
36 * OP_SW - write an array to consecutive registers.
37 * OP_WB - write an array using DMAE.
38 * OP_ZR - clear consecutive registers.
39 * OP_WB_ZR - clear consecutive registers using DMAE.
[all …]
|
| /freebsd/sys/dev/sound/pci/ |
| H A D | emu10kx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2003-2007 Yuriy Tsibizov <yuriy.tsibizov@gfk.ru>
59 #define HAS_51 0x0001
60 #define HAS_71 0x0002
61 #define HAS_AC97 0x0004
63 #define IS_EMU10K1 0x0008
64 #define IS_EMU10K2 0x0010
65 #define IS_CA0102 0x0020
66 #define IS_CA0108 0x0040
[all …]
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| /freebsd/contrib/libarchive/libarchive/ |
| H A D | archive_read_support_format_cab.c | 1 /*-
2 * Copyright (c) 2010-2012 Michihiro NAKAJIMA
134 #define SLOT_MAX 21/*->25*/
150 #define CFHEADER_signature 0
165 #define CFFOLDER_coffCabStart 0
171 #define CFFILE_cbFile 0
178 #define CFDATA_csum 0
215 #define COMPTYPE_NONE 0x0000
216 #define COMPTYPE_MSZIP 0x0001
217 #define COMPTYPE_QUANTUM 0x0002
[all …]
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| H A D | archive_read_support_format_rar.c | 1 /*-
2 * Copyright (c) 2003-2007 Tim Kientzle
53 #define MARK_HEAD 0x72
54 #define MAIN_HEAD 0x73
55 #define FILE_HEAD 0x74
56 #define COMM_HEAD 0x75
57 #define AV_HEAD 0x76
58 #define SUB_HEAD 0x77
59 #define PROTECT_HEAD 0x78
60 #define SIGN_HEAD 0x79
[all …]
|