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/illumos-gate/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/
H A Drxpfw.h17 int RXP_b06FwReleaseMajor = 0x1;
18 int RXP_b06FwReleaseMinor = 0x0;
19 int RXP_b06FwReleaseFix = 0x0;
20 u32_t RXP_b06FwStartAddr = 0x08003210;
21 u32_t RXP_b06FwTextAddr = 0x08000000;
22 int RXP_b06FwTextLen = 0x7874;
23 u32_t RXP_b06FwDataAddr = 0x00000000;
24 int RXP_b06FwDataLen = 0x0;
25 u32_t RXP_b06FwRodataAddr = 0x08007874;
26 int RXP_b06FwRodataLen = 0x24;
[all …]
H A Dxinanfw.h17 int TXP_b09FwReleaseMajor = 0x1;
18 int TXP_b09FwReleaseMinor = 0x0;
19 int TXP_b09FwReleaseFix = 0x0;
20 u32_t TXP_b09FwStartAddr = 0x080000a8;
21 u32_t TXP_b09FwTextAddr = 0x08000000;
22 int TXP_b09FwTextLen = 0x53e0;
23 u32_t TXP_b09FwDataAddr = 0x00000000;
24 int TXP_b09FwDataLen = 0x0;
25 u32_t TXP_b09FwRodataAddr = 0x080053e0;
26 int TXP_b09FwRodataLen = 0x30;
[all …]
H A Dtpatfw.h17 int TPAT_b06FwReleaseMajor = 0x1;
18 int TPAT_b06FwReleaseMinor = 0x0;
19 int TPAT_b06FwReleaseFix = 0x0;
20 u32_t TPAT_b06FwStartAddr = 0x08000490;
21 u32_t TPAT_b06FwTextAddr = 0x08000400;
22 int TPAT_b06FwTextLen = 0x17d4;
23 u32_t TPAT_b06FwDataAddr = 0x00000000;
24 int TPAT_b06FwDataLen = 0x0;
25 u32_t TPAT_b06FwRodataAddr = 0x00000000;
26 int TPAT_b06FwRodataLen = 0x0;
[all …]
H A Dcomfw.h17 int COM_b06FwReleaseMajor = 0x1;
18 int COM_b06FwReleaseMinor = 0x0;
19 int COM_b06FwReleaseFix = 0x0;
20 u32_t COM_b06FwStartAddr = 0x08000118;
21 u32_t COM_b06FwTextAddr = 0x08000000;
22 int COM_b06FwTextLen = 0x7a78;
23 u32_t COM_b06FwDataAddr = 0x00000000;
24 int COM_b06FwDataLen = 0x0;
25 u32_t COM_b06FwRodataAddr = 0x08007a78;
26 int COM_b06FwRodataLen = 0xdc;
[all …]
H A Dtxpfw.h17 int TXP_b06FwReleaseMajor = 0x1;
18 int TXP_b06FwReleaseMinor = 0x0;
19 int TXP_b06FwReleaseFix = 0x0;
20 u32_t TXP_b06FwStartAddr = 0x080000a8;
21 u32_t TXP_b06FwTextAddr = 0x08000000;
22 int TXP_b06FwTextLen = 0x4fe8;
23 u32_t TXP_b06FwDataAddr = 0x00000000;
24 int TXP_b06FwDataLen = 0x0;
25 u32_t TXP_b06FwRodataAddr = 0x00000000;
26 int TXP_b06FwRodataLen = 0x0;
[all …]
H A Dcpfw.h17 int CP_b06FwReleaseMajor = 0x1;
18 int CP_b06FwReleaseMinor = 0x0;
19 int CP_b06FwReleaseFix = 0x0;
20 u32_t CP_b06FwStartAddr = 0x080000a0;
21 u32_t CP_b06FwTextAddr = 0x08000000;
22 int CP_b06FwTextLen = 0x5e64;
23 u32_t CP_b06FwDataAddr = 0x08005f60;
24 int CP_b06FwDataLen = 0x84;
25 u32_t CP_b06FwRodataAddr = 0x08005e64;
26 int CP_b06FwRodataLen = 0xd8;
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A D57710_int_offsets.h34 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
36 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
37 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
38 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
39 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
40 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
41 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
42 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
43 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
H A D57711_int_offsets.h34 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
36 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
37 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
38 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
39 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
40 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
41 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
42 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
43 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
H A D57712_int_offsets.h34 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
36 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
37 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
38 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
39 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
40 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
41 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
42 { 0x3d, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
43 …{ 0x3c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
/illumos-gate/usr/src/lib/iconv_modules/hi_IN/include/
H A Discii-dev.h32 {0xA1, 0x0901, 3},
33 {0xA4, 0x0905, 7},
34 {0xAB, 0x090E, 3},
35 {0xAE, 0x090D, 1},
36 {0xAF, 0x0912, 3},
37 {0xB2, 0x0911, 1},
38 {0xB3, 0x0915, 27},
39 {0xCE, 0x095F, 1},
40 {0xCF, 0x0930, 10},
42 {0xDA, 0x093E, 6},
[all …]
H A Dea-iscii.h31 #define NUKTA 0xFD
32 #define MATRA 0xFE
33 #define COMBINED_MATRA_NUKTA 0xFF
37 #define FIRST_VOWEL 0x43
47 { 0x41, 0xA1, 2 },
48 { 0x43, 0xA4, 1 },
49 { 0x44, 0xB3, 4 },
50 { 0x48, 0xB8, 4 },
51 { 0x4C, 0xBD, 10 },
52 { 0x56, 0xC8, 5 },
[all …]
H A Discii-bng.h32 {0xA1, 0x0981, 3},
33 {0xA4, 0x0985, 7},
34 {0xAC, 0x098F, 2},
35 {0xB0, 0x0993, 2},
36 {0xB3, 0x0995, 20},
37 {0xC8, 0x09AA, 8},
38 {0xD1, 0x09B2, 1},
39 {0xD5, 0x09B6, 4},
41 {0xDA, 0x09BE, 6},
42 {0xE1, 0x09C7, 2},
[all …]
H A Discii-ori.h32 {0xA1, 0x0B01, 3},
33 {0xA4, 0x0B05, 6},
34 {0xAC, 0x0B0F, 2},
35 {0xB0, 0x0B13, 2},
36 {0xB3, 0x0B15, 20},
37 {0xC8, 0x0B2A, 6},
38 {0xCE, 0x0B5F, 2},
39 {0xD1, 0x0B32, 2},
40 {0xD5, 0x0B36, 4},
42 {0xDA, 0x0B3E, 6},
[all …]
H A Discii-gmk.h32 {0xA2, 0x0A02, 1},
33 {0xA4, 0x0A05, 6},
34 {0xAC, 0x0A0F, 2},
35 {0xB0, 0x0A13, 2},
36 {0xB3, 0x0A15, 20},
37 {0xC8, 0x0A2A, 6},
38 {0xCF, 0x0A30, 1},
39 {0xD1, 0x0A32, 1},
40 {0xD4, 0x0A35, 2},
41 {0xD7, 0x0A38, 2},
[all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A Decore_iro_values.h40 { 0x0, 0x0, 0x0, 0x0, 0x8}, /* YSTORM_FLOW_CONTROL_MODE_OFFSET */
41 { 0x4cb0, 0x80, 0x0, 0x0, 0x80}, /* TSTORM_PORT_STAT_OFFSET(port_id) */
42 { 0x6518, 0x20, 0x0, 0x0, 0x20}, /* TSTORM_LL2_PORT_STAT_OFFSET(port_id) */
43 { 0xb00, 0x8, 0x0, 0x0, 0x4}, /* USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) */
44 { 0xa80, 0x8, 0x0, 0x0, 0x4}, /* USTORM_FLR_FINAL_ACK_OFFSET(pf_id) */
45 { 0x0, 0x8, 0x0, 0x0, 0x2}, /* USTORM_EQE_CONS_OFFSET(pf_id) */
46 …{ 0x80, 0x8, 0x0, 0x0, 0x4}, /* USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id…
47 …{ 0x84, 0x8, 0x0, 0x0, 0x2}, /* USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone…
48 { 0x4c40, 0x0, 0x0, 0x0, 0x78}, /* XSTORM_INTEG_TEST_DATA_OFFSET */
49 { 0x3df0, 0x0, 0x0, 0x0, 0x78}, /* YSTORM_INTEG_TEST_DATA_OFFSET */
[all …]
/illumos-gate/usr/src/man/man3cpc/
H A Dgeneric_events.3cpc927 .SS "AMD Opteron Family 0xF Processor"
936 \fBPAPI_br_ins\fR \fBFR_retired_branches_w_excp_intr\fR 0x0
937 \fBPAPI_br_msp\fR \fBFR_retired_branches_mispred\fR 0x0
938 \fBPAPI_br_tkn\fR \fBFR_retired_taken_branches\fR 0x0
939 \fBPAPI_fp_ops\fR \fBFP_dispatched_fpu_ops\fR 0x3
940 \fBPAPI_fad_ins\fR \fBFP_dispatched_fpu_ops\fR 0x1
941 \fBPAPI_fml_ins\fR \fBFP_dispatched_fpu_ops\fR 0x2
942 \fBPAPI_fpu_idl\fR \fBFP_cycles_no_fpu_ops_retired\fR 0x0
943 \fBPAPI_tot_cyc\fR \fBBU_cpu_clk_unhalted\fR 0x0
944 \fBPAPI_tot_ins\fR \fBFR_retired_x86_instr_w_excp_intr\fR 0x0
[all …]
/illumos-gate/usr/src/uts/intel/os/
H A Dcpuid_subr.c73 * selects the socket type by either (model & 0x3) for family 0fh or the CPUID
78 * Family 0xf revisions B through E
80 #define A_SKTS_0 0
82 [0] = X86_SOCKET_754,
88 * Family 0xf revisions F and G
92 [0] = X86_SOCKET_S1g1,
97 * Family 0x10
101 [0] = X86_SOCKET_F1207,
110 * Family 0x11
118 * Family 0x12
[all …]
/illumos-gate/usr/src/test/elf-tests/tests/capabilities/
H A Dsymcap.ksh28 sc_arg0=$(basename $0)
29 sc_err=0
42 # 0: none
52 sc_obj_hw1=( "0x0" "0x5" "0x42" "0x0" "0x0" "0x0" "0x0"
53 "0x3" "0x8" )
54 sc_obj_hw2=( "0x0" "0x0" "0x0" "0x23" "0xff00" "0x0" "0x0"
55 "0xff7ff6" "0xff7ff6" )
56 sc_obj_hw3=( "0x0" "0x0" "0x0" "0x0" "0x0" "0x12345" "0x7000000"
57 "0x87654321" "0x87654321" )
114 return (0);
[all …]
/illumos-gate/usr/src/lib/libmvec/common/
H A D__vsin.c70 static const unsigned thresh[2] = { 0x3fc90000, 0x3fc40000 };
82 double x0, x1, x2, *py0 = 0, *py1 = 0, *py2, *xsave, *ysave; in __vsin() local
83 unsigned hx0, hx1, hx2, xsb0, xsb1 = 0, xsb2; in __vsin()
91 biguns = 0; in __vsin()
93 x0 = *x; /* error: 'x0' may be used uninitialized */ in __vsin()
98 hx0 = xsb0 & ~0x80000000; in __vsin()
99 if (hx0 > 0x3fe921fb) in __vsin()
104 if (hx0 < 0x3e400000) in __vsin()
110 i = 0; in __vsin()
111 if (--n <= 0) in __vsin()
[all …]
H A D__vcos.c82 static const unsigned thresh[2] = { 0x3fc90000, 0x3fc40000 };
89 * y[i*stridey] := cos( x[i*stridex] ), for i = 0..n.
102 double x0, x1, x2, *py0 = 0, *py1 = 0, *py2, *xsave, *ysave; in __vcos() local
103 unsigned hx0, hx1, hx2, xsb0, xsb1 = 0, xsb2; in __vcos()
111 biguns = 0; in __vcos()
113 x0 = *x; /* 'x0' may be used uninitialized */ in __vcos()
119 hx0 = xsb0 & ~0x80000000; /* mask off sign bit */ in __vcos()
120 if (hx0 > 0x3fe921fb) { in __vcos()
125 if (hx0 < 0x3e400000) { in __vcos()
131 i = 0; in __vcos()
[all …]
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dsbbcreg.h38 #define SBBC_SC_MODE 0x00000020
48 uint32_t devid; /* 0x0.0000 All, device ID */
50 uint32_t devtemp; /* 0x0.0010 All */
52 uint32_t incon_scratch; /* 0x0.0020 All */
54 uint32_t incon_tstl1; /* 0x0.0030 AR and SDC */
56 uint32_t incon_tsterr; /* 0x0.0040 AR and SDC */
58 uint32_t device_conf; /* 0x0.0050 All, device configuration */
60 uint32_t device_rstcntl; /* 0x0.0060 SBBC,AR,dev reset control */
62 uint32_t device_rststat; /* 0x0.0070 All, device reset status */
64 uint32_t device_errstat; /* 0x0.0080 SBBC, device reset */
[all …]
/illumos-gate/usr/src/lib/libm/common/Q/
H A Dfmodl.c35 is = -0x7fffffff - 1,
36 im = 0x0000ffff,
37 iu = 0x00010000;
47 #define __H3(x) *(0 + (int *) &x)
49 #define __H0(x) *(0 + (int *) &x)
60 int x0, y0, z0, carry; in fmodl() local
72 sx = hx & 0x80000000; in fmodl()
73 x0 = hx ^ sx; in fmodl()
74 y0 &= 0x7fffffff; in fmodl()
77 if (x0 >= 0x7fff0000 || /* !finitel(x) */ in fmodl()
[all …]
/illumos-gate/usr/src/uts/sparc/krtld/
H A Ddoreloc.c64 /* R_SPARC_NONE */ {0x0, FLG_RE_NOTREL, 0, 0, 0},
65 /* R_SPARC_8 */ {0x0, FLG_RE_VERIFY, 1, 0, 0},
66 /* R_SPARC_16 */ {0x0, FLG_RE_VERIFY, 2, 0, 0},
67 /* R_SPARC_32 */ {0x0, FLG_RE_VERIFY, 4, 0, 0},
68 /* R_SPARC_DISP8 */ {0x0, FLG_RE_PCREL | FLG_RE_VERIFY | FLG_RE_SIGN,
69 1, 0, 0},
70 /* R_SPARC_DISP16 */ {0x0, FLG_RE_PCREL | FLG_RE_VERIFY | FLG_RE_SIGN,
71 2, 0, 0},
72 /* R_SPARC_DISP32 */ {0x0, FLG_RE_PCREL | FLG_RE_VERIFY | FLG_RE_SIGN,
73 4, 0, 0},
[all …]
/illumos-gate/usr/src/lib/libm/common/m9x/
H A Dremquol.c38 is = -0x7fffffff - 1,
39 im = 0x0000ffff,
40 iu = 0x00010000;
46 #define __H0(x) ((int *) &x)[0]
55 * On entrance: *quo is initialized to 0, x finite and y non-zero & ordered
62 int x0, y0, z0, carry; in fmodquol() local
76 x0 = hx ^ sx; in fmodquol()
77 y0 &= ~0x80000000; in fmodquol()
90 if (x0 < iu) { /* subnormal x */ in fmodquol()
91 ix = 0; in fmodquol()
[all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/mcp/
H A Dnvm_cfg.h50 #define NVM_CFG_version 0x81819
61 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
62 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
71 u32 generic_cont0; /* 0x0 */
72 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
73 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
74 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
75 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
76 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
77 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
[all …]

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