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123

/linux/include/linux/usb/
H A Dr8a66597.h13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
[all …]
H A Daudio-v2.h8 * in http://www.usb.org/developers/devclass_docs/Audio2.0_final.zip
16 /* v1.0 and v2.0 of this standard have many things in common. For the rest
22 * From the USB Audio spec v2.0:
27 * present then the bit pair must be set to 0b00.
29 * set to 0b01. If a Control is also Host programmable, the bit
30 * pair must be set to 0b11. The value 0b10 is not allowed.
36 return (bmControls >> ((control - 1) * 2)) & 0x1; in uac_v2v3_control_is_readable()
41 return (bmControls >> ((control - 1) * 2)) & 0x2; in uac_v2v3_control_is_writeable()
49 __le16 bcdADC; /* 0x0200 */
79 #define UAC_CLOCK_SOURCE_TYPE_EXT 0x0
[all …]
/linux/include/linux/irqchip/
H A Darm-gic-v5.h19 #define GICV5_HWIRQ_ID GENMASK(23, 0)
21 #define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
23 #define GICV5_HWIRQ_TYPE_PPI UL(0x1)
24 #define GICV5_HWIRQ_TYPE_LPI UL(0x2)
25 #define GICV5_HWIRQ_TYPE_SPI UL(0x3)
30 #define GICV5_ARCH_PPI_S_DB_PPI 0x0
31 #define GICV5_ARCH_PPI_RL_DB_PPI 0x1
32 #define GICV5_ARCH_PPI_NS_DB_PPI 0x2
33 #define GICV5_ARCH_PPI_SW_PPI 0x3
34 #define GICV5_ARCH_PPI_HACDBSIRQ 0xf
[all …]
/linux/net/dsa/
H A Dtag_ar9331.c23 * According to the AR8216 doc it should 0b10. On AR9331 it is 0b11 on RX path
24 * and should be set to 0b11 to make it work.
27 #define AR9331_HDR_PORT_NUM_MASK GENMASK(3, 0)
40 /* 0b10 for AR8216 and 0b11 for AR9331 */ in ar9331_tag_xmit()
43 phdr[0] = cpu_to_le16(hdr); in ar9331_tag_xmit()
61 netdev_warn_once(ndev, "%s:%i wrong header version 0x%2x\n", in ar9331_tag_rcv()
67 netdev_warn_once(ndev, "%s:%i packet should not be from cpu 0x%2x\n", in ar9331_tag_rcv()
77 skb->dev = dsa_conduit_find_user(ndev, 0, port); in ar9331_tag_rcv()
/linux/drivers/hid/
H A Dhid-steam.c57 #define STEAM_QUIRK_WIRELESS BIT(0)
86 ID_SET_DIGITAL_MAPPINGS = 0x80,
87 ID_CLEAR_DIGITAL_MAPPINGS = 0x81,
88 ID_GET_DIGITAL_MAPPINGS = 0x82,
89 ID_GET_ATTRIBUTES_VALUES = 0x83,
90 ID_GET_ATTRIBUTE_LABEL = 0x84,
91 ID_SET_DEFAULT_DIGITAL_MAPPINGS = 0x85,
92 ID_FACTORY_RESET = 0x86,
93 ID_SET_SETTINGS_VALUES = 0x87,
94 ID_CLEAR_SETTINGS_VALUES = 0x88,
[all …]
/linux/drivers/usb/gadget/udc/
H A Dm66592-udc.h16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]
/linux/drivers/net/mdio/
H A Dmdio-aspeed.c17 #define ASPEED_MDIO_CTRL 0x0
20 #define ASPEED_MDIO_CTRL_ST_C45 0
23 #define MDIO_C22_OP_WRITE 0b01
24 #define MDIO_C22_OP_READ 0b10
25 #define MDIO_C45_OP_ADDR 0b00
26 #define MDIO_C45_OP_WRITE 0b01
27 #define MDIO_C45_OP_PREAD 0b10
28 #define MDIO_C45_OP_READ 0b11
31 #define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0)
33 #define ASPEED_MDIO_DATA 0x4
[all …]
/linux/include/uapi/linux/
H A Dcciss_defs.h12 #define CMD_SUCCESS 0x0000
13 #define CMD_TARGET_STATUS 0x0001
14 #define CMD_DATA_UNDERRUN 0x0002
15 #define CMD_DATA_OVERRUN 0x0003
16 #define CMD_INVALID 0x0004
17 #define CMD_PROTOCOL_ERR 0x0005
18 #define CMD_HARDWARE_ERR 0x0006
19 #define CMD_CONNECTION_LOST 0x0007
20 #define CMD_ABORTED 0x0008
21 #define CMD_ABORT_FAILED 0x0009
[all …]
/linux/arch/powerpc/include/asm/
H A Dpnv-ocxl.h16 #define PNV_OCXL_ATSD_LNCH 0x00
18 #define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0)
20 * 0b00 Just invalidate TLB.
21 * 0b01 Invalidate just Page Walk Cache.
22 * 0b10 Invalidate TLB, Page Walk Cache, and any
29 * 0b00 Invalidate just the target VA.
30 * 0b01 Invalidate matching PID.
33 /* 0b1: Process Scope, 0b0: Partition Scope */
45 * L=0b0 for 4KB pages
46 * L=0b1 for large pages)
[all …]
H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux/arch/arm64/include/asm/
H A Dkvm_nested.h26 ((tcr & TCR_EL2_DS) ? TCR_DS : 0) | in translate_tcr_el2_to_tcr_el1()
27 ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | in translate_tcr_el2_to_tcr_el1()
135 xn &= 0b10; in kvm_s2_trans_exec_el0()
138 case 0b00: in kvm_s2_trans_exec_el0()
139 case 0b01: in kvm_s2_trans_exec_el0()
151 xn &= 0b10; in kvm_s2_trans_exec_el1()
154 case 0b00: in kvm_s2_trans_exec_el1()
155 case 0b11: in kvm_s2_trans_exec_el1()
238 *elr = 0xbad9acc0debadbad; in kvm_auth_eretax()
253 u8 shift = 0; \
[all …]
/linux/tools/testing/selftests/ftrace/test.d/dynevent/
H A Dtprobe_syntax_errors.tc36 check_error 't kfree ^+0@0)' # DEREF_NEED_BRACE
37 check_error 't kfree ^+0ab1(@0)' # BAD_DEREF_OFFS
38 check_error 't kfree +0(+0(@0^)' # DEREF_OPEN_BRACE
41 check_error 't kfree +0(^$comm)' # COMM_CANT_DEREF
49 check_error 't kfree +0(^+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(@0))))))))))))))' # TOO_MANY_OPS?
50 check_error 't kfree +0(@11):u8[10^' # ARRAY_NO_CLOSE
51 check_error 't kfree +0(@11):u8[10]^a' # BAD_ARRAY_SUFFIX
52 check_error 't kfree +0(@11):u8[^10a]' # BAD_ARRAY_NUM
53 check_error 't kfree +0(@11):u8[^256]' # ARRAY_TOO_BIG
58 check_error 't kfree @11:^b10@a/16' # BAD_BITFIELD
[all …]
H A Dfprobe_syntax_errors.tc50 check_error 'f vfs_read ^+0@0)' # DEREF_NEED_BRACE
51 check_error 'f vfs_read ^+0ab1(@0)' # BAD_DEREF_OFFS
52 check_error 'f vfs_read +0(+0(@0^)' # DEREF_OPEN_BRACE
55 check_error 'f vfs_read +0(^$comm)' # COMM_CANT_DEREF
63 check_error 'f vfs_read +0(^+0(
[all...]
/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h13 #define LOONGARCH_BREAKPOINT_EXECUTE (0 << 0)
16 #define LOONGARCH_BREAKPOINT_LOAD (1 << 0)
32 #define LOONGARCH_BREAKPOINT_LEN_1 0b11
33 #define LOONGARCH_BREAKPOINT_LEN_2 0b10
34 #define LOONGARCH_BREAKPOINT_LEN_4 0b01
35 #define LOONGARCH_BREAKPOINT_LEN_8 0b00
45 #define CSR_CFG_ADDR 0
59 if (T == 0) \
63 } while (0)
67 if (T == 0) \
[all …]
/linux/tools/testing/selftests/ftrace/test.d/kprobe/
H A Dkprobe_syntax_errors.tc46 check_error 'p vfs_read ^+0@0)' # DEREF_NEED_BRACE
47 check_error 'p vfs_read ^+0ab1(@0)' # BAD_DEREF_OFFS
48 check_error 'p vfs_read +0(+0(@0^)' # DEREF_OPEN_BRACE
51 check_error 'p vfs_read +0(^$comm)' # COMM_CANT_DEREF
59 check_error 'p vfs_read +0(^+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(+0(@0))))))))))))))' # TOO_MANY_OPS?
60 check_error 'p vfs_read +0(@11):u8[10^' # ARRAY_NO_CLOSE
61 check_error 'p vfs_read +0(@11):u8[10]^a' # BAD_ARRAY_SUFFIX
62 check_error 'p vfs_read +0(@11):u8[^10a]' # BAD_ARRAY_NUM
63 check_error 'p vfs_read +0(@11):u8[^256]' # ARRAY_TOO_BIG
68 check_error 'p vfs_read @11:^b10@a/16' # BAD_BITFIELD
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h53 #define CVMX_USBCXBASE 0x00016F0010000000ull
56 ((bid) & 1) * 0x100000000000ull)
59 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid)
62 #define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid)
63 #define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid)
64 #define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid)
65 #define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid)
66 #define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid)
67 #define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid)
[all …]
/linux/arch/powerpc/kvm/
H A Dbook3s_hv_tm_builtin.c27 * rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit in kvmhv_p9_tm_emulation_early()
29 * instructions. For the tsr. instruction if bit 31 = 0 then it is per in kvmhv_p9_tm_emulation_early()
32 * to handle TM-related invalid forms that have bit 31 = 0. Moreover, in kvmhv_p9_tm_emulation_early()
39 /* XXX do we need to check for PR=0 here? */ in kvmhv_p9_tm_emulation_early()
43 return 0; in kvmhv_p9_tm_emulation_early()
54 return 0; in kvmhv_p9_tm_emulation_early()
58 return 0; in kvmhv_p9_tm_emulation_early()
62 return 0; in kvmhv_p9_tm_emulation_early()
74 /* XXX do we need to check for PR=0 here? */ in kvmhv_p9_tm_emulation_early()
75 rs = (instr >> 21) & 0x1f; in kvmhv_p9_tm_emulation_early()
[all …]
/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst42 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
52 b) By event type, such as "event=0xXXXX, event=0x1XXXX".
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
73 "bdf" filter will be in effect, because "bdf=0" meaning 0000:000:00.0.
83 bitmap should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4
84 lanes), bit8 is set, port=0x100; if these two Root Ports are both
85 monitored, port=0x101.
89 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0x1/ sleep 5
97 For example, "bdf=0x3900" means BDF of target Endpoint is 0000:39:00.0.
[all …]
H A Dhisi-pmu.rst13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
32 e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
35 e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
57 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
65 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
67 This will only count the operations from core/thread 0 and 1 in this cluster.
79 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
97 $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
98 hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
35 #clock-cells = <0>;
39 reg = <0x0d50>;
44 #clock-cells = <0>;
48 reg = <0x0b00>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
/linux/drivers/mfd/
H A Docelot-spi.c30 #define REG_DEV_CPUORG_IF_CTRL 0x0000
31 #define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
33 #define CFGSTAT_IF_NUM_VCORE (0 << 24)
38 #define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39 #define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
41 #define VSC7512_CHIP_REGS_RES_START 0x71070000
42 #define VSC7512_CHIP_REGS_RES_SIZE 0x14
64 * our CPU. These are two bits (0 and 1) but they're repeated such that in ocelot_spi_initialize()
68 * 0b00: little-endian, MSB first in ocelot_spi_initialize()
72 * 0b01: big-endian, MSB first in ocelot_spi_initialize()
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dsea_to_user.c28 #define PAGE_PHYSICAL 0x007fffffffffffffULL
29 #define PAGE_ADDR_MASK (~(0xfffULL))
43 #define ERROR_TYPE_MEMORY_UER 0x10
45 #define MASK_MEMORY_UER 0b10
48 #define START_GVA 0x80000000UL
49 #define VM_MEM_SIZE 0x40000000UL
51 #define EINJ_OFFSET 0x01234badUL
66 if (fd < 0) in translate_hva_to_hpa()
75 if ((pinfo & PAGE_PRESENT) == 0) in translate_hva_to_hpa()
84 char cmd[256] = {0}; in write_einj_entry()
[all …]
/linux/arch/powerpc/include/asm/book3s/64/
H A Dradix.h26 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
27 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
28 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
31 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
32 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
33 #define RADIX_P4D_BAD_BITS 0x60000000000000e0UL
56 * +------------------+ Kernel virtual map (0xc008000000000000)
60 * 0b11......+------------------+ Kernel linear map (0xc....)
64 * 0b10......+------------------+
68 * 0b01......+------------------+
[all …]
/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A Dct.json15 0,
21 "expExitCode": "0",
23 "matchPattern": "action order [0-9]*: ct zone 0 pipe.*index 42 ref",
42 0,
48 "expExitCode": "0",
50 "matchPattern": "action order [0-9]*: ct zone 0 pipe.*index 42 ref.*cookie deadbeef",
69 0,
75 "expExitCode": "0",
2 { global() object
6 "actions", global() string
13 [ global() array
14 "$TC actions flush action ct", global() string
26 "$TC actions flush action ct" global() string
33 "actions", global() string
40 [ global() array
41 "$TC actions flush action ct", global() string
53 "$TC actions flush action ct" global() string
60 "actions", global() string
67 [ global() array
68 "$TC actions flush action ct", global() string
80 "$TC actions flush action ct" global() string
87 "actions", global() string
94 [ global() array
95 "$TC actions flush action ct", global() string
107 "$TC actions flush action ct" global() string
114 "actions", global() string
121 [ global() array
122 "$TC actions flush action ct", global() string
134 "$TC actions flush action ct" global() string
141 "actions", global() string
148 [ global() array
149 "$TC actions flush action ct", global() string
161 "$TC actions flush action ct" global() string
168 "actions", global() string
175 [ global() array
176 "$TC actions flush action ct", global() string
188 "$TC actions flush action ct" global() string
195 "actions", global() string
202 [ global() array
203 "$TC actions flush action ct", global() string
215 "$TC actions flush action ct" global() string
222 "actions", global() string
229 [ global() array
230 "$TC actions flush action ct", global() string
242 "$TC actions flush action ct" global() string
249 "actions", global() string
256 [ global() array
257 "$TC actions flush action ct", global() string
269 "$TC actions flush action ct" global() string
276 "actions", global() string
283 [ global() array
284 "$TC actions flush action ct", global() string
296 "$TC actions flush action ct" global() string
303 "actions", global() string
310 [ global() array
311 "$TC actions flush action ct", global() string
323 "$TC actions flush action ct" global() string
330 "actions", global() string
337 [ global() array
338 "$TC actions flush action ct", global() string
350 "$TC actions flush action ct" global() string
357 "actions", global() string
364 [ global() array
365 "$TC actions flush action ct", global() string
377 "$TC actions flush action ct" global() string
384 "actions", global() string
391 [ global() array
392 "$TC actions flush action ct", global() string
404 "$TC actions flush action ct" global() string
411 "actions", global() string
418 [ global() array
419 "$TC actions flush action ct", global() string
431 "$TC actions flush action ct" global() string
438 "actions", global() string
445 [ global() array
446 "$TC actions flush action ct", global() string
458 "$TC actions flush action ct" global() string
465 "actions", global() string
474 "nsPlugin", global() string
479 [ global() array
480 "$TC qdisc del dev $DEV1 ingress", global() string
490 { global() object
506 "$TC qdisc del dev $DEV1 ingress" global() string
513 "actions", global() string
520 [ global() array
521 "$TC actions flush action ct", global() string
533 "$TC qdisc del dev $DEV1 root" global() string
540 "actions", global() string
547 [ global() array
548 "$TC actions flush action ct", global() string
559 { global() object
565 { global() object
577 "$TC qdisc del dev $DEV1 ingress" global() string
584 "actions", global() string
591 [ global() array
592 "$TC actions flush action ct", global() string
603 { global() object
609 { global() object
621 "$TC qdisc del dev $DEV1 clsact" global() string
628 "actions", global() string
635 [ global() array
636 "$TC actions flush action ct", global() string
647 { global() object
653 { global() object
665 "$TC qdisc del dev $DEV1 ingress_block 21 clsact" global() string
[all...]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c29 #define UDPHY_PCS 0x4000
30 #define UDPHY_PMA 0x8000
38 #define DP_LANE_SEL_ALL GENMASK(7, 0)
41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_LCPLL_SSC_EN BIT(0)
55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
[all …]

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