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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ib.c45 * command ring and the hw will fetch the commands from the IB
48 * put in IBs for execution by the requested ring.
52 * amdgpu_ib_get - request an IB (Indirect Buffer)
62 * Returns 0 on success, error on failure.
71 r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type], in amdgpu_ib_get()
72 &ib->sa_bo, size); in amdgpu_ib_get()
74 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); in amdgpu_ib_get()
78 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); in amdgpu_ib_get()
80 ib->flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; in amdgpu_ib_get()
83 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); in amdgpu_ib_get()
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H A Damdgpu_vm.c29 #include <linux/dma-fence-array.h>
32 #include <linux/dma-buf.h>
69 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
73 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
74 * addition to an aperture managed by a page table, VMID 0 also has
79 * incurring the overhead of a page table. VMID 0 is used by the kernel
90 #define START(node) ((node)->start)
91 #define LAST(node) ((node)->last)
100 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
116 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
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H A Dvcn_sw_ring.c27 void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, in vcn_dec_sw_ring_emit_fence() argument
32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); in vcn_dec_sw_ring_emit_fence()
33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
34 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); in vcn_dec_sw_ring_emit_fence()
39 void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring) in vcn_dec_sw_ring_insert_end() argument
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in vcn_dec_sw_ring_insert_end()
44 void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, in vcn_dec_sw_ring_emit_ib() argument
47 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); in vcn_dec_sw_ring_emit_ib()
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H A Damdgpu_amdkfd.c1 // SPDX-License-Identifier: MIT
33 #include <linux/dma-buf.h>
53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; in amdgpu_amdkfd_init()
77 adev->kfd.dev = kgd2kfd_probe(adev, vf); in amdgpu_amdkfd_device_probe()
81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
102 if (adev->enable_mes) { in amdgpu_doorbell_get_kfd_info()
109 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
110 *aperture_size = 0; in amdgpu_doorbell_get_kfd_info()
111 *start_offset = 0; in amdgpu_doorbell_get_kfd_info()
112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * in amdgpu_doorbell_get_kfd_info()
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H A Dvcn_v4_0.c47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300
49 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000
51 #define VCN_HARVEST_MMSCH 0
53 #define RDECODE_MSG_CREATE 0x00000000
54 #define RDECODE_MESSAGE_CREATE 0x00000001
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Draideng.txt3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
13 major number whereas 0 represents minor number. The
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 reg = <0x320000 0x10000>;
26 ranges = <0 0x320000 0x10000>;
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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec6.0-0.dtsi35 compatible = "fsl,sec-v6.0", "fsl,sec-v5.0",
36 "fsl,sec-v4.0";
37 fsl,sec-era = <6>;
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "fsl,sec-v6.0-job-ring",
43 "fsl,sec-v5.2-job-ring",
44 "fsl,sec-v5.0-job-ring",
45 "fsl,sec-v4.4-job-ring",
46 "fsl,sec-v4.0-job-ring";
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H A Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.2-job-ring",
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H A Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
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H A Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges = <0x0 0x30000 0x10000>;
41 reg = <0x30000 0x10000>;
42 interrupts = <58 2 0 0>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
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H A Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
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H A Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
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H A Dqoriq-raid1.0-0.dtsi2 * QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ]
36 compatible = "fsl,raideng-v1.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x320000 0x10000>;
40 ranges = <0 0x320000 0x10000>;
43 compatible = "fsl,raideng-v1.0-job-queue";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 reg = <0x1000 0x1000>;
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H A Dp1023si-post.dtsi4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
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H A Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
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/linux/drivers/dma/
H A Dfsl_raid.h13 * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
47 #define FSL_RE_GFM_POLY 0x1d000000
50 #define FSL_RE_CFG1_CBSI 0x08000000
51 #define FSL_RE_CFG1_CBS0 0x00080000
56 #define FSL_RE_PQ_OPCODE 0x1B
57 #define FSL_RE_XOR_OPCODE 0x1A
58 #define FSL_RE_MOVE_OPCODE 0x8
60 #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */
61 #define FSL_RE_CACHEABLE_IO 0x0
62 #define FSL_RE_BUFFER_OUTPUT 0x0
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp-ss-security.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "fsl,imx8qxp-caam", "fsl,sec-v4.0";
11 compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";
15 compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";
H A Dimx8-ss-security.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/firmware/imx/rsrc.h>
9 compatible = "simple-bus";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 ranges = <0x31400000 0x0 0x31400000 0x90000>;
15 compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0";
16 reg = <0x31400000 0x90000>;
18 #address-cells = <1>;
19 #size-cells = <1>;
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/linux/drivers/gpu/drm/xe/
H A Dxe_exec.c1 // SPDX-License-Identifier: MIT
31 * - Passing in a list BO which are read / written to creating implicit syncs
32 * - Binding at exec time
33 * - Flow controlling the ring at exec time
36 * passed into an exec, using the dma-buf implicit sync uAPI, have binds as
37 * separate operations, and using the DRM scheduler to flow control the ring.
61 * Rebinds / dma-resv usage applies to non-compute mode VMs only as for compute
64 * There is no need to flow control the ring in the exec as we write the ring at
65 * submission time and set the DRM scheduler max job limit SIZE_OF_RING /
67 * ring is available.
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H A Dxe_execlist.c1 // SPDX-License-Identifier: MIT
36 GENMASK_ULL(SW_CTX_ID_WIDTH + SW_CTX_ID_SHIFT - 1, \
40 GENMASK_ULL(XEHP_SW_CTX_ID_WIDTH + XEHP_SW_CTX_ID_SHIFT - 1, \
47 struct xe_gt *gt = hwe->gt; in __start_lrc()
48 struct xe_mmio *mmio = &gt->mmio; in __start_lrc()
56 xe_gt_assert(hwe->gt, FIELD_FIT(XEHP_SW_CTX_ID, ctx_id)); in __start_lrc()
59 xe_gt_assert(hwe->gt, FIELD_FIT(SW_CTX_ID, ctx_id)); in __start_lrc()
63 if (hwe->class == XE_ENGINE_CLASS_COMPUTE) in __start_lrc()
67 xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); in __start_lrc()
68 lrc->ring.old_tail = lrc->ring.tail; in __start_lrc()
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/linux/include/drm/
H A Dgpu_scheduler.h28 #include <linux/dma-fence.h>
36 * DRM_SCHED_FENCE_DONT_PIPELINE - Prevent dependency pipelining
45 * DRM_SCHED_FENCE_FLAG_HAS_DEADLINE_BIT - A fence deadline hint has been set
63 * to an array, and as such should start at 0.
75 * struct drm_sched_entity - A wrapper around a job queue (typically
79 * ring, and the scheduler will alternate between entities based on
96 * Lock protecting the run-queue (@rq) to which this entity belongs,
173 * The dependency fence of the job which is on the top of the job queue.
194 * Points to the finished fence of the last scheduled job. Only written
201 * @last_user: last group leader pushing a job into the entity.
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_exec.h1 /* SPDX-License-Identifier: MIT */
41 #define to_nouveau_exec_job(job) \ argument
42 container_of((job), struct nouveau_exec_job, base)
44 int nouveau_exec_job_init(struct nouveau_exec_job **job,
53 /* Limit the number of IBs per job to half the size of the ring in order in nouveau_exec_push_max_from_ib_max()
54 * to avoid the ring running dry between submissions and preserve one in nouveau_exec_push_max_from_ib_max()
55 * more slot for the job's HW fence. in nouveau_exec_push_max_from_ib_max()
57 return ib_max > 1 ? ib_max / 2 - 1 : 0; in nouveau_exec_push_max_from_ib_max()
/linux/drivers/crypto/caam/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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H A Derror.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2009-2011 Freescale Semiconductor, Inc.
25 for (it = sg; it && tlen > 0 ; it = sg_next(it)) { in caam_dump_sg()
36 buf = it_page + it->offset; in caam_dump_sg()
37 len = min_t(size_t, tlen, it->length); in caam_dump_sg()
40 tlen -= len; in caam_dump_sg()
66 { 0x00, "No error." },
67 …{ 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT…
68 { 0x02, "SGT Null Entry Error." },
69 { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." },
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H A Dcaamprng.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/dma-mapping.h>
27 /* prng per-device context */
43 jctx->err = err ? caam_jr_strstatus(jrdev, err) : 0; in caam_prng_done()
45 complete(&jctx->done); in caam_prng_done()
50 init_job_desc(desc, 0); /* + 1 cmd_sz */ in caam_init_reseed_desc()
63 init_job_desc(desc, 0); /* + 1 cmd_sz */ in caam_init_prng_desc()
70 print_hex_dump_debug("prng job desc@: ", DUMP_PREFIX_ADDRESS, in caam_init_prng_desc()
89 return -EOVERFLOW; in caam_prng_generate()
93 return -ENOMEM; in caam_prng_generate()
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