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/linux/arch/arm/mach-davinci/
H A Dda850.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DA850/OMAP-L138 chip specific setup
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/mfd/da8xx-cfgchip.h>
19 #include <clocksource/timer-davinci.h>
31 #define DA850_PLL1_BASE 0x01e1a000
32 #define DA850_TIMER64P2_BASE 0x01f0c000
33 #define DA850_TIMER64P3_BASE 0x01f0d000
46 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
47 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
[all …]
/linux/include/linux/mfd/wm831x/
H A Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
[all …]
H A Dregulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
18 #define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
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/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
47 memset(pps_header, 0, sizeof(*pps_header)); in drm_dsc_dp_pps_header_init()
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
60 * buffer size in bytes, or 0 on invalid input
76 return 0; in drm_dsc_dp_rc_buffer_size()
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = ("hid-multitouch", "hid_multitouch")
28 "NOT_SEEN_MEANS_UP": BIT(0),
43 "TOUCH_SIZE_SCALING": BIT(15),
65 self.tippressure = 15
66 self.azimuth = 0
74 super().__init__(0, x, y)
80 self.twist = 0
91 Usage Page (0xff00)
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H A Dtest_tablet.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
43 https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/windows-pen-states
66 def from_evdev(cls, evdev, test_button) -> "PenState":
99 ) -> "PenState":
146 def valid_transitions(self) -> Tuple["PenState", ...]:
206 def historically_tolerated_transitions(self) -> Tuple["PenState", ...]:
208 for skipping the in-range state, due to historical reasons.
271 def legal_transitions() -> Dict[str, Tuple["PenState", ...]]:
273 we don't have Invert nor Erase bits, so just move in/out-of-range or proximity.
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/linux/drivers/infiniband/hw/irdma/
H A Di40iw_hw.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
5 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
6 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
7 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
8 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
9 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
10 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
11 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
12 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
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/linux/sound/soc/codecs/
H A Dwm5100.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm5100.h -- WM5100 ALSA SoC Audio driver
26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
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H A Dwm9081.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * wm9081.c -- WM9081 ALSA SoC Audio driver
24 #define WM9081_SOFTWARE_RESET 0x00
25 #define WM9081_ANALOGUE_LINEOUT 0x02
26 #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
27 #define WM9081_VMID_CONTROL 0x04
28 #define WM9081_BIAS_CONTROL_1 0x05
29 #define WM9081_ANALOGUE_MIXER 0x07
30 #define WM9081_ANTI_POP_CONTROL 0x08
31 #define WM9081_ANALOGUE_SPEAKER_1 0x09
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H A Drt5660.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5660.h -- RT5660 ALSA SoC audio driver
16 #define RT5660_RESET 0x00
17 #define RT5660_VENDOR_ID 0xfd
18 #define RT5660_VENDOR_ID1 0xfe
19 #define RT5660_VENDOR_ID2 0xff
20 /* I/O - Output */
21 #define RT5660_SPK_VOL 0x01
22 #define RT5660_LOUT_VOL 0x02
23 /* I/O - Input */
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H A Drt5616.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5616.h -- RT5616 ALSA SoC audio driver
13 #define RT5616_RESET 0x00
14 #define RT5616_VERSION_ID 0xfd
15 #define RT5616_VENDOR_ID 0xfe
16 #define RT5616_DEVICE_ID 0xff
17 /* I/O - Output */
18 #define RT5616_HP_VOL 0x02
19 #define RT5616_LOUT_CTRL1 0x03
20 #define RT5616_LOUT_CTRL2 0x05
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H A Drt5651.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
15 #define RT5651_RESET 0x00
16 #define RT5651_VERSION_ID 0xfd
17 #define RT5651_VENDOR_ID 0xfe
18 #define RT5651_DEVICE_ID 0xff
19 /* I/O - Output */
20 #define RT5651_HP_VOL 0x02
21 #define RT5651_LOUT_CTRL1 0x03
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H A Drt5640.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
18 #define RT5640_RESET 0x00
19 #define RT5640_VENDOR_ID 0xfd
20 #define RT5640_VENDOR_ID1 0xfe
21 #define RT5640_VENDOR_ID2 0xff
22 /* I/O - Output */
23 #define RT5640_SPK_VOL 0x01
24 #define RT5640_HP_VOL 0x02
[all …]
H A Dwm8995.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm8995.h -- WM8995 ALSA SoC Audio driver
18 #define WM8995_SOFTWARE_RESET 0x00
19 #define WM8995_POWER_MANAGEMENT_1 0x01
20 #define WM8995_POWER_MANAGEMENT_2 0x02
21 #define WM8995_POWER_MANAGEMENT_3 0x03
22 #define WM8995_POWER_MANAGEMENT_4 0x04
23 #define WM8995_POWER_MANAGEMENT_5 0x05
24 #define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
25 #define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
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H A Drt5670.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
13 #define RT5670_RESET 0x00
14 #define RT5670_VENDOR_ID 0xfd
15 #define RT5670_VENDOR_ID1 0xfe
16 #define RT5670_VENDOR_ID2 0xff
17 /* I/O - Output */
18 #define RT5670_HP_VOL 0x02
19 #define RT5670_LOUT1 0x03
20 /* I/O - Input */
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/linux/arch/s390/include/asm/
H A Dfpu-insn-asm.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/fpu-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
31 \opd = 0
76 \opd = 15
83 /* VX_NUM - Retrieve vector register number
95 \opd = 0
140 \opd = 15
195 /* RXB - Compute most significant bit used vector registers
199 * RXB bit 0 (instruction bit 36) and whose remaining bits
[all …]
/linux/tools/accounting/
H A Dgetdelays.c1 // SPDX-License-Identifier: GPL-2.0
4 * Utility to get per-pid and per-tgid delay accounting statistics
12 * gcc -I/usr/src/linux/include getdelays.c -o getdelays
38 #define GENLMSG_PAYLOAD(glh) (NLMSG_PAYLOAD(glh, 0) - GENL_HDRLEN)
40 #define NLA_PAYLOAD(len) (len - NLA_HDRLEN)
46 } while (0)
76 fprintf(stderr, "getdelays [-dilv] [-w logfile] [-r bufsize] " in usage()
77 "[-m cpumask] [-t tgid] [-p pid]\n"); in usage()
78 fprintf(stderr, " -d: print delayacct stats\n"); in usage()
79 fprintf(stderr, " -i: print IO accounting (works only with -p)\n"); in usage()
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/linux/arch/csky/abiv2/inc/abi/
H A Dckmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 return mfcr("cr<0, 15>"); in read_mmu_index()
16 mtcr("cr<0, 15>", value); in write_mmu_index()
21 return mfcr("cr<2, 15>"); in read_mmu_entrylo0()
26 return mfcr("cr<3, 15>"); in read_mmu_entrylo1()
31 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
36 return mfcr("cr<4, 15>"); in read_mmu_entryhi()
41 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
46 return mfcr("cr<30, 15>"); in read_mmu_msa0()
51 mtcr("cr<30, 15>", value); in write_mmu_msa0()
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-dcphy.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
8 #include <dt-bindings/phy/phy.h>
29 #define BIAS_CON0 0x0000
32 #define I_RES_059_2UA I_RES_CNTL(0)
40 #define I_DEV_SEL_MASK GENMASK(1, 0)
42 #define I_DEV_DIV_6 I_DEV_SEL(0)
47 #define BIAS_CON1 0x0004
50 #define I_VBG_SEL_780MV I_VBG_SEL(0)
56 #define I_BGR_VREF_810MV I_BGR_VREF_SEL(0)
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/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
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/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include "decode-insn.h"
8 #include "simulate-insn.h"
15 *ptr = *(&regs->a0 + index); in csky_insn_reg_get_val()
17 if (index > 15 && index < 31) in csky_insn_reg_get_val()
18 *ptr = *(&regs->exregs[0] + index - 16); in csky_insn_reg_get_val()
22 *ptr = regs->usp; in csky_insn_reg_get_val()
24 case 15: in csky_insn_reg_get_val()
25 *ptr = regs->lr; in csky_insn_reg_get_val()
28 *ptr = regs->tls; in csky_insn_reg_get_val()
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-rapidio3 On-chip RapidIO controllers and PCIe-to-RapidIO bridges
15 KernelVersion: v3.15
21 0 = small (8-bit destination ID, max. 256 devices),
23 1 = large (16-bit destination ID, max. 65536 devices).
27 KernelVersion: v3.15
33 RapidIO mport device. If value 0xFFFFFFFF is returned this means
46 [rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
47 total 0
48 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
49 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
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/linux/lib/zstd/compress/
H A Dclevels.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
18 /*-===== Pre-defined compression levels =====-*/
25 { /* "default" - for any srcSize > 256 KB */
28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
42 { 22, 23, 23, 6, 5, 32, ZSTD_btlazy2 }, /* level 15 */
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/linux/drivers/net/wireless/broadcom/b43/
H A Dtables_lpphy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 IEEE 802.11a/g LP-PHY and radio device data tables
26 #define B206X_FLAG_A 0x01 /* Flag: Init in A mode */
27 #define B206X_FLAG_G 0x02 /* Flag: Init in G mode */
30 /* { .offset = B2062_N_COMM1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
31 /* { .offset = 0x0001, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
32 /* { .offset = B2062_N_COMM2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
33 /* { .offset = B2062_N_COMM3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
34 …{ .offset = B2062_N_COMM4, .value_a = 0x0001, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLA…
35 /* { .offset = B2062_N_COMM5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */
[all …]

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