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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mt7622.txt4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
[all …]
H A Dsamsung-pinctrl.txt1 Samsung GPIO and Pin Mux/Config controller
3 Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
[all …]
H A Drenesas,pfc-pinctrl.txt1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config)
3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
7 Pin Control
8 -----------
12 - compatible: should be one of the following.
13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
16 - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
17 - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
H A Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
14 #define PIN(_pin, _func, _pull, _drv) \ macro
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
23 PIN(_pin, INPUT, _pull, _drv)
[all …]
H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
[all …]
H A Dexynos850-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama5d3_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
H A Dat91sam9x5_lcd.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mu
[all...]
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
H A Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos3250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
[all …]
H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
[all …]
H A Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
16 * Pin banks
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
[all …]
H A Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
[all …]
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/actions/
H A Ds900-bubblegum-96.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ucrobotics,bubblegum-96", "actions,s900";
12 model = "Bubblegum-96";
22 stdout-path = "serial5:115200n8";
31 vcc_3v1: vcc-3v1 {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-3.1V";
34 regulator-min-microvolt = <3100000>;
35 regulator-max-microvolt = <3100000>;
[all …]
/freebsd/sys/dev/qcom_tlmm/
H A Dqcom_tlmm_ipq4018_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
63 * Set the pin function. This is a hardware and pin specific mapping.
69 int pin, int function) in qcom_tlmm_ipq4018_hw_pin_set_function() argument
75 if (pin >= sc->gpio_npins) in qcom_tlmm_ipq4018_hw_pin_set_function()
78 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin, in qcom_tlmm_ipq4018_hw_pin_set_function()
84 GPIO_WRITE(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin, in qcom_tlmm_ipq4018_hw_pin_set_function()
91 * Get the pin function. This is a hardware and pin specific mapping.
97 int pin, int *function) in qcom_tlmm_ipq4018_hw_pin_get_function() argument
103 if (pin >= sc->gpio_npins) in qcom_tlmm_ipq4018_hw_pin_get_function()
[all …]
/freebsd/sys/arm/mv/
H A Dgpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
99 int pin; member
158 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex)
159 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex)
160 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED)
192 { "marvell,orion-gpio", 1 },
202 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in mv_gpio_probe()
219 device_printf(sc->dev, "No interrupt-parrent found. " in mv_gpio_setup_interrupts()
223 /* While at parent - store interrupt cells prop */ in mv_gpio_setup_interrupts()
[all …]
/freebsd/usr.sbin/gpioctl/
H A Dgpioctl.837 .Cm -l
42 .Cm -t
43 .Ar pin
47 .Cm -c
48 .Ar pin
54 .Cm -n
55 .Ar pin
56 .Ar pin-name
58 .Op Cm -f Ar ctldev
60 .Ar pin
[all …]

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