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/linux/arch/arm64/crypto/
H A Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
19 .set .Lv\b\().4s, \b
45 * x0: 128-bit key
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
53 ld1 {v1.16b}, [x3];
[all …]
H A Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
99 eor RTMP1.16b, s2.16b, s3.16b; \
100 eor RX0.16b, RX0.16b, s1.16b; \
101 eor RX0.16b, RX0.16b, RTMP1.16b; \
103 /* sbox, non-linear part */ \
[all …]
H A Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
192 in_bs_ch \b0\().16b, \b1\().16b, \b2\().16b, \b3\().16b, \
193 \b4\().16b, \b5\().16b, \b6\().16b, \b7\().16b
194 inv_gf256 \b6\().16b, \b5\().16b, \b0\().16b, \b3\().16b, \
195 \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
196 \t0\().16b, \t1\().16b, \t2\().16b, \t3\().16b, \
197 \s0\().16b, \s1\().16b, \s2\().16b, \s3\().16b
198 out_bs_ch \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
[all …]
H A Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
19 .set .Lv\b\().4s, \b
37 * output: r0:r1 (low 128-bits in r0, high in r1)
40 ext T0.16b, m1.16b, m1.16b, #8; \
45 eor T0.16b, T0.16b, T1.16b; \
46 ext T1.16b, RZERO.16b, T0.16b, #8; \
[all …]
H A Dsm4-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-CCM AEAD Algorithm using ARMv8 Crypto Extensions
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31
18 .set .Lv\b\().4s, \b
35 rev64 vctr.16b, vctr.16b; \
49 ld1 {RMAC.16b}, [x1]
57 ld1 {v0.16b-v3.16b}, [x2], #64
60 eor RMAC.16b, RMAC.16b, v0.16b
[all …]
H A Dsm4-ce-asm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 ld1 {v24.16b-v27.16b}, [ptr], #64; \
9 ld1 {v28.16b-v31.16b}, [ptr];
21 ext b0.16b, b0.16b, b0.16b, #8; \
22 rev32 b0.16b, b0.16b;
25 rev32 b0.16b, b0.16b; \
47 ext b0.16b, b0.16b, b0.16b, #8; \
48 ext b1.16b, b1.16b, b1.16b, #8; \
49 rev32 b0.16b, b0.16b; \
50 rev32 b1.16b, b1.16b; \
[all …]
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd.
15 .arch armv8-a+crypto
20 ld1 {v10.4s-v13.4s}, [\rk]
21 ld1 {v14.4s-v17.4s}, [\tmp], #64
22 ld1 {v18.4s-v21.4s}, [\tmp], #64
23 ld1 {v3.4s-v5.4s}, [\tmp]
27 aese \va\().16b, \vk\().16b
28 aesmc \va\().16b, \va\().16b
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
23 - e GRBG 0
24 - e RGGB 1
25 - e BGGR 2
[all …]
/linux/drivers/comedi/drivers/ni_routing/ni_route_values/
H A Dni_mseries.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
42 * DAQ-STC. There is some evidence that using CtrGate values is valid (see
43 * comedi.h). Some information and hints exist in the M-Series user manual
44 * (ni-62xx user-manual 371022K-01).
56 [B(NI_PFI(0))] = {
57 [B(TRIGGER_LINE(0))] = I(18),
58 [B(TRIGGER_LINE(1))] = I(19),
59 [B(TRIGGER_LINE(2))] = I(20),
60 [B(TRIGGER_LINE(3))] = I(21),
[all …]
H A Dni_eseries.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
40 * Note that for e-series devices, the backplane TRIGGER_LINE(6) is generally
53 [B(NI_PFI(0))] = {
54 [B(NI_AI_StartTrigger)] = I(NI_PFI_OUTPUT_AI_START1),
56 [B(NI_PFI(1))] = {
57 [B(NI_AI_ReferenceTrigger)] = I(NI_PFI_OUTPUT_AI_START2),
59 [B(NI_PFI(2))] = {
60 [B(NI_AI_ConvertClock)] = I(NI_PFI_OUTPUT_AI_CONVERT),
62 [B(NI_PFI(3))] = {
[all …]
H A Dni_660x.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
48 [B(NI_PFI(8))] = {
49 [B(NI_CtrInternalOutput(7))] = I(1),
51 [B(NI_PFI(10))] = {
52 [B(NI_CtrGate(7))] = I(1),
54 [B(NI_PFI(11))] = {
55 [B(NI_CtrSource(7))] = I(1),
57 [B(NI_PFI(12))] = {
58 [B(NI_CtrInternalOutput(6))] = I(1),
[all …]
/linux/drivers/md/bcache/
H A Dbtree.c1 // SPDX-License-Identifier: GPL-2.0
21 * All configuration is done via sysfs; see Documentation/admin-guide/bcache.rst.
100 (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
104 #define insert_lock(s, b) ((b)->level <= (s)->lock) argument
107 static inline struct bset *write_block(struct btree *b) in write_block() argument
109 return ((void *) btree_bset_first(b)) + b->written * block_bytes(b->c->cache); in write_block()
112 static void bch_btree_init_next(struct btree *b) in bch_btree_init_next() argument
115 if (b->level && b->keys.nsets) in bch_btree_init_next()
116 bch_btree_sort(&b->keys, &b->c->sort); in bch_btree_init_next()
118 bch_btree_sort_lazy(&b->keys, &b->c->sort); in bch_btree_init_next()
[all …]
/linux/lib/crypto/arm64/
H A Dpolyval-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
22 * two-step process only requires 1 finite field reduction for every 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
84 * Later, the 256-bit result can be extracted as:
96 ext v25.16b, X.16b, X.16b, #8
97 ext v26.16b, Y.16b, Y.16b, #8
98 eor v25.16b, v25.16b, X.16b
99 eor v26.16b, v26.16b, Y.16b
[all …]
/linux/net/ceph/crush/
H A Dhash.c1 // SPDX-License-Identifier: GPL-2.0
9 * Robert Jenkins' function for mixing 32-bit values
11 * a, b = random bits, c = input and output
13 #define crush_hashmix(a, b, c) do { \ argument
14 a = a-b; a = a-c; a = a^(c>>13); \
15 b = b-c; b = b-a; b = b^(a<<8); \
16 c = c-a; c = c-b; c = c^(b>>13); \
17 a = a-b; a = a-c; a = a^(c>>12); \
18 b = b-c; b = b-a; b = b^(a<<16); \
19 c = c-a; c = c-b; c = c^(b>>5); \
[all …]
H A Dcrush.c1 // SPDX-License-Identifier: GPL-2.0
23 * crush_get_bucket_item_weight - Get weight of an item in given bucket
24 * @b: bucket pointer
27 int crush_get_bucket_item_weight(const struct crush_bucket *b, int p) in crush_get_bucket_item_weight() argument
29 if ((__u32)p >= b->size) in crush_get_bucket_item_weight()
32 switch (b->alg) { in crush_get_bucket_item_weight()
34 return ((struct crush_bucket_uniform *)b)->item_weight; in crush_get_bucket_item_weight()
36 return ((struct crush_bucket_list *)b)->item_weights[p]; in crush_get_bucket_item_weight()
38 return ((struct crush_bucket_tree *)b)->node_weights[crush_calc_tree_node(p)]; in crush_get_bucket_item_weight()
40 return ((struct crush_bucket_straw *)b)->item_weights[p]; in crush_get_bucket_item_weight()
[all …]
/linux/arch/loongarch/lib/
H A Dcopy_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 #include <asm/alternative-asm.h>
10 #include <asm/asm-extable.h>
17 b __copy_user_generic
22 ALTERNATIVE "b __copy_user_generic", \
23 "b __copy_user_fast", CPU_FEATURE_UAL
39 1: ld.b t0, a1, 0
40 2: st.b t0, a0, 0
43 PTR_ADDI a2, a2, -1
[all …]
/linux/tools/perf/tests/
H A Dtime-utils-test.c1 // SPDX-License-Identifier: GPL-2.0
6 #include "time-utils.h"
83 evlist__set_first_sample_time(evlist, d->first); in test__perf_time__parse_for_ranges()
84 evlist__set_last_sample_time(evlist, d->last); in test__perf_time__parse_for_ranges()
85 pr_debug("\nperf_time__parse_for_ranges(\"%s\")\n", d->str); in test__perf_time__parse_for_ranges()
87 if (strchr(d->str, '%')) in test__perf_time__parse_for_ranges()
89 d->first, d->las in test__perf_time__parse_for_ranges()
159 u64 b = 1234567123456789ULL; test__time_utils() local
172 u64 b = 1234567123456789ULL; test__time_utils() local
189 u64 b = 7654321ULL * NSEC_PER_SEC; test__time_utils() local
204 u64 b = 7654321ULL * NSEC_PER_SEC; test__time_utils() local
219 u64 b = 11223344ULL * NSEC_PER_SEC; test__time_utils() local
234 u64 b = 11223344ULL * NSEC_PER_SEC; test__time_utils() local
[all...]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _pixfmt-rgb:
23 (including capture queues of mem-to-mem devices) fill the alpha component in
26 but can set the alpha bit to a user-configurable value, the
27 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
32 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
45 - In all the tables that follow, bit 7 is the most significant bit in a byte.
46 - 'r', 'g' and 'b' denote bits of the red, green and blue components
55 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
58 for each component. For instance, the RGB565 format stores a pixel in a 16-bit
[all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_opr.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.c
5 * Samsung MFC (Multi Function Codec - FIMV) driver
20 dev->mfc_ops = s5p_mfc_init_hw_ops_v6(); in s5p_mfc_init_hw_ops()
21 dev->warn_start = S5P_FIMV_ERR_WARNINGS_START_V6; in s5p_mfc_init_hw_ops()
23 dev->mfc_ops = s5p_mfc_init_hw_ops_v5(); in s5p_mfc_init_hw_ops()
24 dev->warn_start = S5P_FIMV_ERR_WARNINGS_START; in s5p_mfc_init_hw_ops()
31 dev->mfc_regs = s5p_mfc_init_regs_v6_plus(dev); in s5p_mfc_init_regs()
35 struct s5p_mfc_priv_buf *b) in s5p_mfc_alloc_priv_buf() argument
37 unsigned int bits = dev->mem_size >> PAGE_SHIFT; in s5p_mfc_alloc_priv_buf()
[all …]
/linux/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
20 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
21 #define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2))) argument
24 #define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT) argument
25 #define GET_CONTEXT_FIELD(b, c, r, F) \ argument
26 GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
28 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
29 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
30 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
[all …]
/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <asm/asm-const.h>
120 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
121 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
131 * 18-bit immediate helper for prefix 18-bit upper immediate si0 field.
323 #define ___PPC_RB(b) (((b) & 0x1f) << 11) argument
332 #define __PPC_RB(b) ___PPC_RB(__REG_##b) argument
336 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) argument
375 #define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b)) argument
377 #define PPC_RAW_DCBAL(a, b) (0x7c2005ec | __PPC_RA(a) | __PPC_RB(b)) argument
[all …]
/linux/arch/arm64/kernel/vdso/
H A Dvgetrandom-chacha.S1 // SPDX-License-Identifier: GPL-2.0
27 * number of blocks of output with nonce 0, taking an input key and 8-bytes
30 * This implementation avoids d8-d15 because they are callee-save in user
39 * x1: 32-byte key input
40 * x2: 8-byte counter input/output
41 * x3: number of 64-byte block to write to output
45 /* copy0 = "expand 32-byte k" */
61 mov state0.16b, copy0.16b
62 mov state1.16b, copy1.16b
63 mov state2.16b, copy2.16b
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Dtest_jhash.h1 // SPDX-License-Identifier: GPL-2.0
9 return (word << shift) | (word >> ((-shift) & 31)); in rol32()
12 #define __jhash_mix(a, b, c) \ argument
14 a -= c; a ^= rol32(c, 4); c += b; \
15 b -= a; b ^= rol32(a, 6); a += c; \
16 c -= b; c ^= rol32(b, 8); b += a; \
17 a -= c; a ^= rol32(c, 16); c += b; \
18 b -= a; b ^= rol32(a, 19); a += c; \
19 c -= b; c ^= rol32(b, 4); b += a; \
22 #define __jhash_final(a, b, c) \ argument
[all …]
/linux/drivers/block/drbd/
H A Ddrbd_bitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
7 Copyright (C) 2004-2008, LINBIT Information Technologies GmbH.
8 Copyright (C) 2004-2008, Philipp Reisner <philipp.reisner@linbit.com>.
9 Copyright (C) 2004-2008, Lars Ellenberg <lars.ellenberg@linbit.com>.
39 * 1 << (50 - 12) bits needed
40 * 38 --> we need u64 to index and count bits
41 * 1 << (38 - 3) bitmap bytes needed
42 * 35 --> we still need u64 to index and count bytes
44 * 1 << (35 - 2) 32bit longs needed
45 * 33 --> we'd even need u64 to index and count 32bit long words.
[all …]
/linux/drivers/md/
H A Ddm-bufio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009-2011 Red Hat, Inc.
10 #include <linux/dm-bufio.h>
12 #include <linux/device-mapper.h>
13 #include <linux/dm-io.h>
55 * dm_buffer->list_mode
63 /*--------------------------------------------------------------*/
91 /*--------------*/
95 lru->cursor = NULL; in lru_init()
96 lru->count = 0; in lru_init()
[all …]

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