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/linux/arch/arm64/crypto/
H A Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
19 .set .Lv\b\().4s, \b
45 * x0: 128-bit key
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
53 ld1 {v1.16b}, [x3];
[all …]
H A Daes-neon.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-neon.S - AES cipher for ARMv8 NEON
5 * Copyright (C) 2013 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
22 /* special case for the neon-bs driver calling into this one for CTS */
45 movi v12.16b, #0x1b
49 ld1 {v16.16b-v19.16b}, [\temp], #64
50 ld1 {v20.16b-v23.16b}, [\temp], #64
51 ld1 {v24.16b-v27.16b}, [\temp], #64
52 ld1 {v28.16b-v31.16b}, [\temp]
71 sub v9.16b, \in\().16b, v15.16b
[all …]
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
16 .set .Lv\b\().2d, \b
17 .set .Lv\b\().16b, \b
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
[all …]
H A Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
192 in_bs_ch \b0\().16b, \b1\().16b, \b2\().16b, \b3\().16b, \
193 \b4\().16b, \b5\().16b, \b6\().16b, \b7\().16b
194 inv_gf256 \b6\().16b, \b5\().16b, \b0\().16b, \b3\().16b, \
195 \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
196 \t0\().16b, \t1\().16b, \t2\().16b, \t3\().16b, \
197 \s0\().16b, \s1\().16b, \s2\().16b, \s3\().16b
198 out_bs_ch \b7\().16b, \b1\().16b, \b4\().16b, \b2\().16b, \
[all …]
H A Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
99 eor RTMP1.16b, s2.16b, s3.16b; \
100 eor RX0.16b, RX0.16b, s1.16b; \
101 eor RX0.16b, RX0.16b, RTMP1.16b; \
103 /* sbox, non-linear part */ \
[all …]
H A Dghash-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
61 .arch armv8-a+crypto
72 ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
73 ext t5.8b, \ad\().8b, \ad\().8b, #2 // A2
74 ext t7.8b, \ad\().8b, \ad\().8b, #3 // A3
80 tbl t3.16b, {\ad\().16b}, perm1.16b // A1
81 tbl t5.16b, {\ad\().16b}, perm2.16b // A2
82 tbl t7.16b, {\ad\().16b}, perm3.16b // A3
88 __pmull_p8_tail \rq, \ad\().8b, SHASH.8b, 8b,, sh1, sh2, sh3, sh4
[all …]
H A Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
19 .set .Lv\b\().4s, \b
37 * output: r0:r1 (low 128-bits in r0, high in r1)
40 ext T0.16b, m1.16b, m1.16b, #8; \
45 eor T0.16b, T0.16b, T1.16b; \
46 ext T1.16b, RZERO.16b, T0.16b, #8; \
[all …]
H A Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
64 ST5( ld1 {v4.16b}, [x1], #16 )
66 st1 {v0.16b-v3.16b}, [x0], #64
67 ST5( st1 {v4.16b}, [x0], #16 )
68 b .LecbencloopNx
73 ld1 {v0.16b}, [x1], #16 /* get next pt block */
[all …]
H A Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
116 movi perm4.8b, #8
118 eor perm1.16b, perm1.16b, perm4.16b
128 tbl bd1.16b, {\bd\().16b}, perm1.16b
129 tbl bd2.16b, {\bd\().16b}, perm2.16b
130 tbl bd3.16b, {\bd\().16b}, perm3.16b
131 tbl bd4.16b, {\bd\().16b}, perm4.16b
[all …]
H A Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
47 eor v3.16b, v3.16b, v0.16b
52 eor v4.16b, v1.16b, v2.16b
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
63 eor v4.16b, v1.16b, v2.16b
[all …]
H A Dsm4-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-CCM AEAD Algorithm using ARMv8 Crypto Extensions
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 24, 25, 26, 27, 28, 29, 30, 31
18 .set .Lv\b\().4s, \b
35 rev64 vctr.16b, vctr.16b; \
49 ld1 {RMAC.16b}, [x1]
57 ld1 {v0.16b-v3.16b}, [x2], #64
60 eor RMAC.16b, RMAC.16b, v0.16b
[all …]
H A Dpolyval-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
22 * two-step process only requires 1 finite field reduction for every 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
84 * Later, the 256-bit result can be extracted as:
96 ext v25.16b, X.16b, X.16b, #8
97 ext v26.16b, Y.16b, Y.16b, #8
98 eor v25.16b, v25.16b, X.16b
99 eor v26.16b, v26.16b, Y.16b
[all …]
H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
18 mov v3.16b, v1.16b
19 b 2f
20 0: mov v2.16b, v1.16b
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
25 aese v0.16b, v3.16b
[all …]
H A Dsm4-ce-asm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 ld1 {v24.16b-v27.16b}, [ptr], #64; \
9 ld1 {v28.16b-v31.16b}, [ptr];
21 ext b0.16b, b0.16b, b0.16b, #8; \
22 rev32 b0.16b, b0.16b;
25 rev32 b0.16b, b0.16b; \
47 ext b0.16b, b0.16b, b0.16b, #8; \
48 ext b1.16b, b1.16b, b1.16b, #8; \
49 rev32 b0.16b, b0.16b; \
50 rev32 b1.16b, b1.16b; \
[all …]
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd.
15 .arch armv8-a+crypto
20 ld1 {v10.4s-v13.4s}, [\rk]
21 ld1 {v14.4s-v17.4s}, [\tmp], #64
22 ld1 {v18.4s-v21.4s}, [\tmp], #64
23 ld1 {v3.4s-v5.4s}, [\tmp]
27 aese \va\().16b, \vk\().16b
28 aesmc \va\().16b, \va\().16b
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
23 - e GRBG 0
24 - e RGGB 1
25 - e BGGR 2
[all …]
/linux/drivers/comedi/drivers/ni_routing/ni_route_values/
H A Dni_mseries.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
42 * DAQ-STC. There is some evidence that using CtrGate values is valid (see
43 * comedi.h). Some information and hints exist in the M-Series user manual
44 * (ni-62xx user-manual 371022K-01).
56 [B(NI_PFI(0))] = {
57 [B(TRIGGER_LINE(0))] = I(18),
58 [B(TRIGGER_LINE(1))] = I(19),
59 [B(TRIGGER_LINE(2))] = I(20),
60 [B(TRIGGER_LINE(3))] = I(21),
[all …]
H A Dni_eseries.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
40 * Note that for e-series devices, the backplane TRIGGER_LINE(6) is generally
53 [B(NI_PFI(0))] = {
54 [B(NI_AI_StartTrigger)] = I(NI_PFI_OUTPUT_AI_START1),
56 [B(NI_PFI(1))] = {
57 [B(NI_AI_ReferenceTrigger)] = I(NI_PFI_OUTPUT_AI_START2),
59 [B(NI_PFI(2))] = {
60 [B(NI_AI_ConvertClock)] = I(NI_PFI_OUTPUT_AI_CONVERT),
62 [B(NI_PFI(3))] = {
[all …]
/linux/fs/bcachefs/
H A Dbtree_cache.c1 // SPDX-License-Identifier: GPL-2.0
23 bc->not_freed[BCH_BTREE_CACHE_NOT_FREED_##counter]++; \
37 if (!c->btree_roots_known[0].b) in bch2_recalc_btree_reserve()
43 if (r->b) in bch2_recalc_btree_reserve()
44 reserve += min_t(unsigned, 1, r->b->c.level) * 8; in bch2_recalc_btree_reserve()
47 c->btree_cache.nr_reserve = reserve; in bch2_recalc_btree_reserve()
52 struct btree_cache *bc = container_of(list, struct btree_cache, live[list->idx]); in btree_cache_can_free()
54 size_t can_free = list->nr; in btree_cache_can_free()
55 if (!list->idx) in btree_cache_can_free()
56 can_free = max_t(ssize_t, 0, can_free - bc->nr_reserve); in btree_cache_can_free()
[all …]
H A Dbset.c1 // SPDX-License-Identifier: GPL-2.0
26 unsigned n = ARRAY_SIZE(iter->data); in __btree_node_iter_used()
28 while (n && __btree_node_iter_set_end(iter, n - 1)) in __btree_node_iter_used()
29 --n; in __btree_node_iter_used()
34 struct bset_tree *bch2_bkey_to_bset(struct btree *b, struct bkey_packed *k) in bch2_bkey_to_bset() argument
36 return bch2_bkey_to_bset_inlined(b, k); in bch2_bkey_to_bset()
40 * There are never duplicate live keys in the btree - but including keys that
50 * prior to the first key greater than the key we're inserting - our insert
55 void bch2_dump_bset(struct bch_fs *c, struct btree *b, in bch2_dump_bset() argument
63 if (!i->u64s) in bch2_dump_bset()
[all …]
H A Dbtree_io.c1 // SPDX-License-Identifier: GPL-2.0
21 #include "super-io.h"
30 (unsigned) BTREE_NODE_LEVEL(bn), bn->keys.seq); in bch2_btree_node_header_to_text()
32 bch2_bpos_to_text(out, bn->min_key); in bch2_btree_node_header_to_text()
35 bch2_bpos_to_text(out, bn->max_key); in bch2_btree_node_header_to_text()
38 void bch2_btree_node_io_unlock(struct btree *b) in bch2_btree_node_io_unlock() argument
40 EBUG_ON(!btree_node_write_in_flight(b)); in bch2_btree_node_io_unlock()
42 clear_btree_node_write_in_flight_inner(b); in bch2_btree_node_io_unlock()
43 clear_btree_node_write_in_flight(b); in bch2_btree_node_io_unlock()
44 wake_up_bit(&b->flags, BTREE_NODE_write_in_flight); in bch2_btree_node_io_unlock()
[all …]
H A Dbtree_update_interior.c1 // SPDX-License-Identifier: GPL-2.0
25 #include "sb-members.h"
26 #include "super-io.h"
45 int bch2_btree_node_check_topology(struct btree_trans *trans, struct btree *b) in bch2_btree_node_check_topology() argument
47 struct bch_fs *c = trans->c; in bch2_btree_node_check_topology()
48 struct bpos node_min = b->key.k.type == KEY_TYPE_btree_ptr_v2 in bch2_btree_node_check_topology()
49 ? bkey_i_to_btree_ptr_v2(&b->key)->v.min_key in bch2_btree_node_check_topology()
50 : b->data->min_key; in bch2_btree_node_check_topology()
57 BUG_ON(b->key.k.type == KEY_TYPE_btree_ptr_v2 && in bch2_btree_node_check_topology()
58 !bpos_eq(bkey_i_to_btree_ptr_v2(&b->key)->v.min_key, in bch2_btree_node_check_topology()
[all …]
/linux/drivers/md/bcache/
H A Dbtree.c1 // SPDX-License-Identifier: GPL-2.0
21 * All configuration is done via sysfs; see Documentation/admin-guide/bcache.rst.
100 (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0))
104 #define insert_lock(s, b) ((b)->level <= (s)->lock) argument
107 static inline struct bset *write_block(struct btree *b) in write_block() argument
109 return ((void *) btree_bset_first(b)) + b->written * block_bytes(b->c->cache); in write_block()
112 static void bch_btree_init_next(struct btree *b) in bch_btree_init_next() argument
115 if (b->level && b->keys.nsets) in bch_btree_init_next()
116 bch_btree_sort(&b->keys, &b->c->sort); in bch_btree_init_next()
118 bch_btree_sort_lazy(&b->keys, &b->c->sort); in bch_btree_init_next()
[all …]
/linux/arch/x86/lib/
H A Dusercopy_32.c1 // SPDX-License-Identifier: GPL-2.0
4 * The non inlined parts of asm-i386/uaccess.h are here.
45 _ASM_EXTABLE_TYPE_REG(0b, 2b, EX_TYPE_UCOPY_LEN4, %2) \
46 _ASM_EXTABLE_UA(1b, 2b) \
52 * clear_user - Zero a block of memory in user space.
72 * __clear_user - Zero a block of memory in user space, with less checking.
134 " addl $-64, %0\n" in __copy_user_intel()
138 " ja 1b\n" in __copy_user_intel()
147 _ASM_EXTABLE_UA(1b, 100b) in __copy_user_intel()
148 _ASM_EXTABLE_UA(2b, 100b) in __copy_user_intel()
[all …]
/linux/arch/loongarch/lib/
H A Dcopy_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 #include <asm/alternative-asm.h>
10 #include <asm/asm-extable.h>
19 ALTERNATIVE "b __copy_user_generic", \
20 "b __copy_user_fast", CPU_FEATURE_UAL
35 1: ld.b t0, a1, 0
36 2: st.b t0, a0, 0
39 addi.d a2, a2, -1
40 bgtz a2, 1b
[all …]

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