1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/power/xlnx-zynqmp-power.h> 20#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 21 22/ { 23 compatible = "xlnx,zynqmp"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "arm,cortex-a53"; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 operating-points-v2 = <&cpu_opp_table>; 36 reg = <0x0>; 37 cpu-idle-states = <&CPU_SLEEP_0>; 38 next-level-cache = <&L2>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x1>; 46 operating-points-v2 = <&cpu_opp_table>; 47 cpu-idle-states = <&CPU_SLEEP_0>; 48 next-level-cache = <&L2>; 49 }; 50 51 cpu2: cpu@2 { 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 next-level-cache = <&L2>; 59 }; 60 61 cpu3: cpu@3 { 62 compatible = "arm,cortex-a53"; 63 device_type = "cpu"; 64 enable-method = "psci"; 65 reg = <0x3>; 66 operating-points-v2 = <&cpu_opp_table>; 67 cpu-idle-states = <&CPU_SLEEP_0>; 68 next-level-cache = <&L2>; 69 }; 70 71 L2: l2-cache { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 }; 76 77 idle-states { 78 entry-method = "psci"; 79 80 CPU_SLEEP_0: cpu-sleep-0 { 81 compatible = "arm,idle-state"; 82 arm,psci-suspend-param = <0x40000000>; 83 local-timer-stop; 84 entry-latency-us = <300>; 85 exit-latency-us = <600>; 86 min-residency-us = <10000>; 87 }; 88 }; 89 }; 90 91 cpu_opp_table: opp-table-cpu { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 opp00 { 95 opp-hz = /bits/ 64 <1199999988>; 96 opp-microvolt = <1000000>; 97 clock-latency-ns = <500000>; 98 }; 99 opp01 { 100 opp-hz = /bits/ 64 <599999994>; 101 opp-microvolt = <1000000>; 102 clock-latency-ns = <500000>; 103 }; 104 opp02 { 105 opp-hz = /bits/ 64 <399999996>; 106 opp-microvolt = <1000000>; 107 clock-latency-ns = <500000>; 108 }; 109 opp03 { 110 opp-hz = /bits/ 64 <299999997>; 111 opp-microvolt = <1000000>; 112 clock-latency-ns = <500000>; 113 }; 114 }; 115 116 reserved-memory { 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 rproc_0_fw_image: memory@3ed00000 { 122 no-map; 123 reg = <0x0 0x3ed00000 0x0 0x40000>; 124 }; 125 126 rproc_1_fw_image: memory@3ef00000 { 127 no-map; 128 reg = <0x0 0x3ef00000 0x0 0x40000>; 129 }; 130 }; 131 132 zynqmp_ipi: zynqmp-ipi { 133 bootph-all; 134 compatible = "xlnx,zynqmp-ipi-mailbox"; 135 interrupt-parent = <&gic>; 136 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 137 xlnx,ipi-id = <0>; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 142 ipi_mailbox_pmu1: mailbox@ff9905c0 { 143 bootph-all; 144 compatible = "xlnx,zynqmp-ipi-dest-mailbox"; 145 reg = <0x0 0xff9905c0 0x0 0x20>, 146 <0x0 0xff9905e0 0x0 0x20>, 147 <0x0 0xff990e80 0x0 0x20>, 148 <0x0 0xff990ea0 0x0 0x20>; 149 reg-names = "local_request_region", 150 "local_response_region", 151 "remote_request_region", 152 "remote_response_region"; 153 #mbox-cells = <1>; 154 xlnx,ipi-id = <4>; 155 }; 156 }; 157 158 dcc: dcc { 159 compatible = "arm,dcc"; 160 status = "disabled"; 161 bootph-all; 162 }; 163 164 pmu { 165 compatible = "arm,armv8-pmuv3"; 166 interrupt-parent = <&gic>; 167 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-affinity = <&cpu0>, 172 <&cpu1>, 173 <&cpu2>, 174 <&cpu3>; 175 }; 176 177 psci { 178 compatible = "arm,psci-0.2"; 179 method = "smc"; 180 }; 181 182 firmware { 183 zynqmp_firmware: zynqmp-firmware { 184 compatible = "xlnx,zynqmp-firmware"; 185 #power-domain-cells = <1>; 186 method = "smc"; 187 bootph-all; 188 189 zynqmp_power: zynqmp-power { 190 bootph-all; 191 compatible = "xlnx,zynqmp-power"; 192 interrupt-parent = <&gic>; 193 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 194 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 195 mbox-names = "tx", "rx"; 196 }; 197 198 nvmem-firmware { 199 compatible = "xlnx,zynqmp-nvmem-fw"; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 203 soc_revision: soc-revision@0 { 204 reg = <0x0 0x4>; 205 }; 206 }; 207 208 zynqmp_pcap: pcap { 209 compatible = "xlnx,zynqmp-pcap-fpga"; 210 }; 211 212 xlnx_aes: zynqmp-aes { 213 compatible = "xlnx,zynqmp-aes"; 214 }; 215 216 zynqmp_reset: reset-controller { 217 compatible = "xlnx,zynqmp-reset"; 218 #reset-cells = <1>; 219 }; 220 221 pinctrl0: pinctrl { 222 compatible = "xlnx,zynqmp-pinctrl"; 223 status = "disabled"; 224 }; 225 226 modepin_gpio: gpio { 227 compatible = "xlnx,zynqmp-gpio-modepin"; 228 gpio-controller; 229 #gpio-cells = <2>; 230 }; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv8-timer"; 236 interrupt-parent = <&gic>; 237 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 241 }; 242 243 fpga_full: fpga-full { 244 compatible = "fpga-region"; 245 fpga-mgr = <&zynqmp_pcap>; 246 #address-cells = <2>; 247 #size-cells = <2>; 248 ranges; 249 }; 250 251 remoteproc { 252 compatible = "xlnx,zynqmp-r5fss"; 253 xlnx,cluster-mode = <1>; 254 255 r5f-0 { 256 compatible = "xlnx,zynqmp-r5f"; 257 power-domains = <&zynqmp_firmware PD_RPU_0>; 258 memory-region = <&rproc_0_fw_image>; 259 }; 260 261 r5f-1 { 262 compatible = "xlnx,zynqmp-r5f"; 263 power-domains = <&zynqmp_firmware PD_RPU_1>; 264 memory-region = <&rproc_1_fw_image>; 265 }; 266 }; 267 268 amba: axi { 269 compatible = "simple-bus"; 270 bootph-all; 271 #address-cells = <2>; 272 #size-cells = <2>; 273 ranges; 274 275 can0: can@ff060000 { 276 compatible = "xlnx,zynq-can-1.0"; 277 status = "disabled"; 278 clock-names = "can_clk", "pclk"; 279 reg = <0x0 0xff060000 0x0 0x1000>; 280 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-parent = <&gic>; 282 tx-fifo-depth = <0x40>; 283 rx-fifo-depth = <0x40>; 284 power-domains = <&zynqmp_firmware PD_CAN_0>; 285 }; 286 287 can1: can@ff070000 { 288 compatible = "xlnx,zynq-can-1.0"; 289 status = "disabled"; 290 clock-names = "can_clk", "pclk"; 291 reg = <0x0 0xff070000 0x0 0x1000>; 292 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-parent = <&gic>; 294 tx-fifo-depth = <0x40>; 295 rx-fifo-depth = <0x40>; 296 power-domains = <&zynqmp_firmware PD_CAN_1>; 297 }; 298 299 cci: cci@fd6e0000 { 300 compatible = "arm,cci-400"; 301 status = "disabled"; 302 reg = <0x0 0xfd6e0000 0x0 0x9000>; 303 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 307 pmu@9000 { 308 compatible = "arm,cci-400-pmu,r1"; 309 reg = <0x9000 0x5000>; 310 interrupt-parent = <&gic>; 311 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 316 }; 317 }; 318 319 /* GDMA */ 320 fpd_dma_chan1: dma-controller@fd500000 { 321 status = "disabled"; 322 compatible = "xlnx,zynqmp-dma-1.0"; 323 reg = <0x0 0xfd500000 0x0 0x1000>; 324 interrupt-parent = <&gic>; 325 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 326 clock-names = "clk_main", "clk_apb"; 327 #dma-cells = <1>; 328 xlnx,bus-width = <128>; 329 iommus = <&smmu 0x14e8>; 330 power-domains = <&zynqmp_firmware PD_GDMA>; 331 }; 332 333 fpd_dma_chan2: dma-controller@fd510000 { 334 status = "disabled"; 335 compatible = "xlnx,zynqmp-dma-1.0"; 336 reg = <0x0 0xfd510000 0x0 0x1000>; 337 interrupt-parent = <&gic>; 338 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 339 clock-names = "clk_main", "clk_apb"; 340 #dma-cells = <1>; 341 xlnx,bus-width = <128>; 342 iommus = <&smmu 0x14e9>; 343 power-domains = <&zynqmp_firmware PD_GDMA>; 344 }; 345 346 fpd_dma_chan3: dma-controller@fd520000 { 347 status = "disabled"; 348 compatible = "xlnx,zynqmp-dma-1.0"; 349 reg = <0x0 0xfd520000 0x0 0x1000>; 350 interrupt-parent = <&gic>; 351 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 352 clock-names = "clk_main", "clk_apb"; 353 #dma-cells = <1>; 354 xlnx,bus-width = <128>; 355 iommus = <&smmu 0x14ea>; 356 power-domains = <&zynqmp_firmware PD_GDMA>; 357 }; 358 359 fpd_dma_chan4: dma-controller@fd530000 { 360 status = "disabled"; 361 compatible = "xlnx,zynqmp-dma-1.0"; 362 reg = <0x0 0xfd530000 0x0 0x1000>; 363 interrupt-parent = <&gic>; 364 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 365 clock-names = "clk_main", "clk_apb"; 366 #dma-cells = <1>; 367 xlnx,bus-width = <128>; 368 iommus = <&smmu 0x14eb>; 369 power-domains = <&zynqmp_firmware PD_GDMA>; 370 }; 371 372 fpd_dma_chan5: dma-controller@fd540000 { 373 status = "disabled"; 374 compatible = "xlnx,zynqmp-dma-1.0"; 375 reg = <0x0 0xfd540000 0x0 0x1000>; 376 interrupt-parent = <&gic>; 377 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 378 clock-names = "clk_main", "clk_apb"; 379 #dma-cells = <1>; 380 xlnx,bus-width = <128>; 381 iommus = <&smmu 0x14ec>; 382 power-domains = <&zynqmp_firmware PD_GDMA>; 383 }; 384 385 fpd_dma_chan6: dma-controller@fd550000 { 386 status = "disabled"; 387 compatible = "xlnx,zynqmp-dma-1.0"; 388 reg = <0x0 0xfd550000 0x0 0x1000>; 389 interrupt-parent = <&gic>; 390 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 391 clock-names = "clk_main", "clk_apb"; 392 #dma-cells = <1>; 393 xlnx,bus-width = <128>; 394 iommus = <&smmu 0x14ed>; 395 power-domains = <&zynqmp_firmware PD_GDMA>; 396 }; 397 398 fpd_dma_chan7: dma-controller@fd560000 { 399 status = "disabled"; 400 compatible = "xlnx,zynqmp-dma-1.0"; 401 reg = <0x0 0xfd560000 0x0 0x1000>; 402 interrupt-parent = <&gic>; 403 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 404 clock-names = "clk_main", "clk_apb"; 405 #dma-cells = <1>; 406 xlnx,bus-width = <128>; 407 iommus = <&smmu 0x14ee>; 408 power-domains = <&zynqmp_firmware PD_GDMA>; 409 }; 410 411 fpd_dma_chan8: dma-controller@fd570000 { 412 status = "disabled"; 413 compatible = "xlnx,zynqmp-dma-1.0"; 414 reg = <0x0 0xfd570000 0x0 0x1000>; 415 interrupt-parent = <&gic>; 416 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 417 clock-names = "clk_main", "clk_apb"; 418 #dma-cells = <1>; 419 xlnx,bus-width = <128>; 420 iommus = <&smmu 0x14ef>; 421 power-domains = <&zynqmp_firmware PD_GDMA>; 422 }; 423 424 gic: interrupt-controller@f9010000 { 425 compatible = "arm,gic-400"; 426 #interrupt-cells = <3>; 427 reg = <0x0 0xf9010000 0x0 0x10000>, 428 <0x0 0xf9020000 0x0 0x20000>, 429 <0x0 0xf9040000 0x0 0x20000>, 430 <0x0 0xf9060000 0x0 0x20000>; 431 interrupt-controller; 432 interrupt-parent = <&gic>; 433 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 434 }; 435 436 gpu: gpu@fd4b0000 { 437 status = "disabled"; 438 compatible = "xlnx,zynqmp-mali", "arm,mali-400"; 439 reg = <0x0 0xfd4b0000 0x0 0x10000>; 440 interrupt-parent = <&gic>; 441 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; 448 clock-names = "bus", "core"; 449 power-domains = <&zynqmp_firmware PD_GPU>; 450 }; 451 452 /* LPDDMA default allows only secured access. inorder to enable 453 * These dma channels, Users should ensure that these dma 454 * Channels are allowed for non secure access. 455 */ 456 lpd_dma_chan1: dma-controller@ffa80000 { 457 status = "disabled"; 458 compatible = "xlnx,zynqmp-dma-1.0"; 459 reg = <0x0 0xffa80000 0x0 0x1000>; 460 interrupt-parent = <&gic>; 461 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 462 clock-names = "clk_main", "clk_apb"; 463 #dma-cells = <1>; 464 xlnx,bus-width = <64>; 465 iommus = <&smmu 0x868>; 466 power-domains = <&zynqmp_firmware PD_ADMA>; 467 }; 468 469 lpd_dma_chan2: dma-controller@ffa90000 { 470 status = "disabled"; 471 compatible = "xlnx,zynqmp-dma-1.0"; 472 reg = <0x0 0xffa90000 0x0 0x1000>; 473 interrupt-parent = <&gic>; 474 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 475 clock-names = "clk_main", "clk_apb"; 476 #dma-cells = <1>; 477 xlnx,bus-width = <64>; 478 iommus = <&smmu 0x869>; 479 power-domains = <&zynqmp_firmware PD_ADMA>; 480 }; 481 482 lpd_dma_chan3: dma-controller@ffaa0000 { 483 status = "disabled"; 484 compatible = "xlnx,zynqmp-dma-1.0"; 485 reg = <0x0 0xffaa0000 0x0 0x1000>; 486 interrupt-parent = <&gic>; 487 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 488 clock-names = "clk_main", "clk_apb"; 489 #dma-cells = <1>; 490 xlnx,bus-width = <64>; 491 iommus = <&smmu 0x86a>; 492 power-domains = <&zynqmp_firmware PD_ADMA>; 493 }; 494 495 lpd_dma_chan4: dma-controller@ffab0000 { 496 status = "disabled"; 497 compatible = "xlnx,zynqmp-dma-1.0"; 498 reg = <0x0 0xffab0000 0x0 0x1000>; 499 interrupt-parent = <&gic>; 500 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 501 clock-names = "clk_main", "clk_apb"; 502 #dma-cells = <1>; 503 xlnx,bus-width = <64>; 504 iommus = <&smmu 0x86b>; 505 power-domains = <&zynqmp_firmware PD_ADMA>; 506 }; 507 508 lpd_dma_chan5: dma-controller@ffac0000 { 509 status = "disabled"; 510 compatible = "xlnx,zynqmp-dma-1.0"; 511 reg = <0x0 0xffac0000 0x0 0x1000>; 512 interrupt-parent = <&gic>; 513 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 514 clock-names = "clk_main", "clk_apb"; 515 #dma-cells = <1>; 516 xlnx,bus-width = <64>; 517 iommus = <&smmu 0x86c>; 518 power-domains = <&zynqmp_firmware PD_ADMA>; 519 }; 520 521 lpd_dma_chan6: dma-controller@ffad0000 { 522 status = "disabled"; 523 compatible = "xlnx,zynqmp-dma-1.0"; 524 reg = <0x0 0xffad0000 0x0 0x1000>; 525 interrupt-parent = <&gic>; 526 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 527 clock-names = "clk_main", "clk_apb"; 528 #dma-cells = <1>; 529 xlnx,bus-width = <64>; 530 iommus = <&smmu 0x86d>; 531 power-domains = <&zynqmp_firmware PD_ADMA>; 532 }; 533 534 lpd_dma_chan7: dma-controller@ffae0000 { 535 status = "disabled"; 536 compatible = "xlnx,zynqmp-dma-1.0"; 537 reg = <0x0 0xffae0000 0x0 0x1000>; 538 interrupt-parent = <&gic>; 539 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 540 clock-names = "clk_main", "clk_apb"; 541 #dma-cells = <1>; 542 xlnx,bus-width = <64>; 543 iommus = <&smmu 0x86e>; 544 power-domains = <&zynqmp_firmware PD_ADMA>; 545 }; 546 547 lpd_dma_chan8: dma-controller@ffaf0000 { 548 status = "disabled"; 549 compatible = "xlnx,zynqmp-dma-1.0"; 550 reg = <0x0 0xffaf0000 0x0 0x1000>; 551 interrupt-parent = <&gic>; 552 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 553 clock-names = "clk_main", "clk_apb"; 554 #dma-cells = <1>; 555 xlnx,bus-width = <64>; 556 iommus = <&smmu 0x86f>; 557 power-domains = <&zynqmp_firmware PD_ADMA>; 558 }; 559 560 mc: memory-controller@fd070000 { 561 compatible = "xlnx,zynqmp-ddrc-2.40a"; 562 reg = <0x0 0xfd070000 0x0 0x30000>; 563 interrupt-parent = <&gic>; 564 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 565 }; 566 567 nand0: nand-controller@ff100000 { 568 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 569 status = "disabled"; 570 reg = <0x0 0xff100000 0x0 0x1000>; 571 clock-names = "controller", "bus"; 572 interrupt-parent = <&gic>; 573 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 iommus = <&smmu 0x872>; 577 power-domains = <&zynqmp_firmware PD_NAND>; 578 }; 579 580 gem0: ethernet@ff0b0000 { 581 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 582 status = "disabled"; 583 interrupt-parent = <&gic>; 584 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 586 reg = <0x0 0xff0b0000 0x0 0x1000>; 587 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 588 iommus = <&smmu 0x874>; 589 power-domains = <&zynqmp_firmware PD_ETH_0>; 590 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 591 reset-names = "gem0_rst"; 592 }; 593 594 gem1: ethernet@ff0c0000 { 595 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 596 status = "disabled"; 597 interrupt-parent = <&gic>; 598 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 600 reg = <0x0 0xff0c0000 0x0 0x1000>; 601 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 602 iommus = <&smmu 0x875>; 603 power-domains = <&zynqmp_firmware PD_ETH_1>; 604 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 605 reset-names = "gem1_rst"; 606 }; 607 608 gem2: ethernet@ff0d0000 { 609 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 610 status = "disabled"; 611 interrupt-parent = <&gic>; 612 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 614 reg = <0x0 0xff0d0000 0x0 0x1000>; 615 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 616 iommus = <&smmu 0x876>; 617 power-domains = <&zynqmp_firmware PD_ETH_2>; 618 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 619 reset-names = "gem2_rst"; 620 }; 621 622 gem3: ethernet@ff0e0000 { 623 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 624 status = "disabled"; 625 interrupt-parent = <&gic>; 626 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 628 reg = <0x0 0xff0e0000 0x0 0x1000>; 629 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 630 iommus = <&smmu 0x877>; 631 power-domains = <&zynqmp_firmware PD_ETH_3>; 632 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 633 reset-names = "gem3_rst"; 634 }; 635 636 gpio: gpio@ff0a0000 { 637 compatible = "xlnx,zynqmp-gpio-1.0"; 638 status = "disabled"; 639 #gpio-cells = <0x2>; 640 gpio-controller; 641 interrupt-parent = <&gic>; 642 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 643 interrupt-controller; 644 #interrupt-cells = <2>; 645 reg = <0x0 0xff0a0000 0x0 0x1000>; 646 power-domains = <&zynqmp_firmware PD_GPIO>; 647 }; 648 649 i2c0: i2c@ff020000 { 650 compatible = "cdns,i2c-r1p14"; 651 status = "disabled"; 652 interrupt-parent = <&gic>; 653 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 654 clock-frequency = <400000>; 655 reg = <0x0 0xff020000 0x0 0x1000>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 power-domains = <&zynqmp_firmware PD_I2C_0>; 659 }; 660 661 i2c1: i2c@ff030000 { 662 compatible = "cdns,i2c-r1p14"; 663 status = "disabled"; 664 interrupt-parent = <&gic>; 665 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 666 clock-frequency = <400000>; 667 reg = <0x0 0xff030000 0x0 0x1000>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 power-domains = <&zynqmp_firmware PD_I2C_1>; 671 }; 672 673 pcie: pcie@fd0e0000 { 674 compatible = "xlnx,nwl-pcie-2.11"; 675 status = "disabled"; 676 #address-cells = <3>; 677 #size-cells = <2>; 678 #interrupt-cells = <1>; 679 msi-controller; 680 device_type = "pci"; 681 interrupt-parent = <&gic>; 682 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ 686 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ 687 interrupt-names = "misc", "dummy", "intx", 688 "msi1", "msi0"; 689 msi-parent = <&pcie>; 690 reg = <0x0 0xfd0e0000 0x0 0x1000>, 691 <0x0 0xfd480000 0x0 0x1000>, 692 <0x80 0x00000000 0x0 0x1000000>; 693 reg-names = "breg", "pcireg", "cfg"; 694 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 695 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 696 bus-range = <0x00 0xff>; 697 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 698 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 699 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 700 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 701 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 702 iommus = <&smmu 0x4d0>; 703 power-domains = <&zynqmp_firmware PD_PCIE>; 704 pcie_intc: legacy-interrupt-controller { 705 interrupt-controller; 706 #address-cells = <0>; 707 #interrupt-cells = <1>; 708 }; 709 }; 710 711 qspi: spi@ff0f0000 { 712 bootph-all; 713 compatible = "xlnx,zynqmp-qspi-1.0"; 714 status = "disabled"; 715 clock-names = "ref_clk", "pclk"; 716 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-parent = <&gic>; 718 num-cs = <1>; 719 reg = <0x0 0xff0f0000 0x0 0x1000>, 720 <0x0 0xc0000000 0x0 0x8000000>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 iommus = <&smmu 0x873>; 724 power-domains = <&zynqmp_firmware PD_QSPI>; 725 }; 726 727 psgtr: phy@fd400000 { 728 compatible = "xlnx,zynqmp-psgtr-v1.1"; 729 status = "disabled"; 730 reg = <0x0 0xfd400000 0x0 0x40000>, 731 <0x0 0xfd3d0000 0x0 0x1000>; 732 reg-names = "serdes", "siou"; 733 #phy-cells = <4>; 734 }; 735 736 rtc: rtc@ffa60000 { 737 compatible = "xlnx,zynqmp-rtc"; 738 status = "disabled"; 739 reg = <0x0 0xffa60000 0x0 0x100>; 740 interrupt-parent = <&gic>; 741 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 743 interrupt-names = "alarm", "sec"; 744 calibration = <0x7FFF>; 745 }; 746 747 sata: ahci@fd0c0000 { 748 compatible = "ceva,ahci-1v84"; 749 status = "disabled"; 750 reg = <0x0 0xfd0c0000 0x0 0x2000>; 751 interrupt-parent = <&gic>; 752 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 753 power-domains = <&zynqmp_firmware PD_SATA>; 754 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 755 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 756 <&smmu 0x4c2>, <&smmu 0x4c3>; 757 }; 758 759 sdhci0: mmc@ff160000 { 760 bootph-all; 761 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 762 status = "disabled"; 763 interrupt-parent = <&gic>; 764 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 765 reg = <0x0 0xff160000 0x0 0x1000>; 766 clock-names = "clk_xin", "clk_ahb"; 767 iommus = <&smmu 0x870>; 768 #clock-cells = <1>; 769 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 770 power-domains = <&zynqmp_firmware PD_SD_0>; 771 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; 772 }; 773 774 sdhci1: mmc@ff170000 { 775 bootph-all; 776 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 777 status = "disabled"; 778 interrupt-parent = <&gic>; 779 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 780 reg = <0x0 0xff170000 0x0 0x1000>; 781 clock-names = "clk_xin", "clk_ahb"; 782 iommus = <&smmu 0x871>; 783 #clock-cells = <1>; 784 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 785 power-domains = <&zynqmp_firmware PD_SD_1>; 786 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; 787 }; 788 789 smmu: iommu@fd800000 { 790 compatible = "arm,mmu-500"; 791 reg = <0x0 0xfd800000 0x0 0x20000>; 792 #iommu-cells = <1>; 793 status = "disabled"; 794 #global-interrupts = <1>; 795 interrupt-parent = <&gic>; 796 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 813 }; 814 815 spi0: spi@ff040000 { 816 compatible = "cdns,spi-r1p6"; 817 status = "disabled"; 818 interrupt-parent = <&gic>; 819 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 820 reg = <0x0 0xff040000 0x0 0x1000>; 821 clock-names = "ref_clk", "pclk"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 power-domains = <&zynqmp_firmware PD_SPI_0>; 825 }; 826 827 spi1: spi@ff050000 { 828 compatible = "cdns,spi-r1p6"; 829 status = "disabled"; 830 interrupt-parent = <&gic>; 831 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 832 reg = <0x0 0xff050000 0x0 0x1000>; 833 clock-names = "ref_clk", "pclk"; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 power-domains = <&zynqmp_firmware PD_SPI_1>; 837 }; 838 839 ttc0: timer@ff110000 { 840 compatible = "cdns,ttc"; 841 status = "disabled"; 842 interrupt-parent = <&gic>; 843 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 846 reg = <0x0 0xff110000 0x0 0x1000>; 847 timer-width = <32>; 848 power-domains = <&zynqmp_firmware PD_TTC_0>; 849 }; 850 851 ttc1: timer@ff120000 { 852 compatible = "cdns,ttc"; 853 status = "disabled"; 854 interrupt-parent = <&gic>; 855 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 858 reg = <0x0 0xff120000 0x0 0x1000>; 859 timer-width = <32>; 860 power-domains = <&zynqmp_firmware PD_TTC_1>; 861 }; 862 863 ttc2: timer@ff130000 { 864 compatible = "cdns,ttc"; 865 status = "disabled"; 866 interrupt-parent = <&gic>; 867 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 870 reg = <0x0 0xff130000 0x0 0x1000>; 871 timer-width = <32>; 872 power-domains = <&zynqmp_firmware PD_TTC_2>; 873 }; 874 875 ttc3: timer@ff140000 { 876 compatible = "cdns,ttc"; 877 status = "disabled"; 878 interrupt-parent = <&gic>; 879 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 882 reg = <0x0 0xff140000 0x0 0x1000>; 883 timer-width = <32>; 884 power-domains = <&zynqmp_firmware PD_TTC_3>; 885 }; 886 887 uart0: serial@ff000000 { 888 bootph-all; 889 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 890 status = "disabled"; 891 interrupt-parent = <&gic>; 892 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 893 reg = <0x0 0xff000000 0x0 0x1000>; 894 clock-names = "uart_clk", "pclk"; 895 power-domains = <&zynqmp_firmware PD_UART_0>; 896 }; 897 898 uart1: serial@ff010000 { 899 bootph-all; 900 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 901 status = "disabled"; 902 interrupt-parent = <&gic>; 903 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 904 reg = <0x0 0xff010000 0x0 0x1000>; 905 clock-names = "uart_clk", "pclk"; 906 power-domains = <&zynqmp_firmware PD_UART_1>; 907 }; 908 909 usb0: usb@ff9d0000 { 910 #address-cells = <2>; 911 #size-cells = <2>; 912 status = "disabled"; 913 compatible = "xlnx,zynqmp-dwc3"; 914 reg = <0x0 0xff9d0000 0x0 0x100>; 915 power-domains = <&zynqmp_firmware PD_USB_0>; 916 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 917 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 918 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 919 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 920 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 921 ranges; 922 923 dwc3_0: usb@fe200000 { 924 compatible = "snps,dwc3"; 925 reg = <0x0 0xfe200000 0x0 0x40000>; 926 interrupt-parent = <&gic>; 927 interrupt-names = "host", "peripheral", "otg"; 928 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 931 clock-names = "bus_early", "ref"; 932 iommus = <&smmu 0x860>; 933 snps,quirk-frame-length-adjustment = <0x20>; 934 snps,resume-hs-terminations; 935 /* dma-coherent; */ 936 }; 937 }; 938 939 usb1: usb@ff9e0000 { 940 #address-cells = <2>; 941 #size-cells = <2>; 942 status = "disabled"; 943 compatible = "xlnx,zynqmp-dwc3"; 944 reg = <0x0 0xff9e0000 0x0 0x100>; 945 power-domains = <&zynqmp_firmware PD_USB_1>; 946 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 947 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 948 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 949 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 950 ranges; 951 952 dwc3_1: usb@fe300000 { 953 compatible = "snps,dwc3"; 954 reg = <0x0 0xfe300000 0x0 0x40000>; 955 interrupt-parent = <&gic>; 956 interrupt-names = "host", "peripheral", "otg"; 957 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 960 clock-names = "bus_early", "ref"; 961 iommus = <&smmu 0x861>; 962 snps,quirk-frame-length-adjustment = <0x20>; 963 snps,resume-hs-terminations; 964 /* dma-coherent; */ 965 }; 966 }; 967 968 watchdog0: watchdog@fd4d0000 { 969 compatible = "cdns,wdt-r1p2"; 970 status = "disabled"; 971 interrupt-parent = <&gic>; 972 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 973 reg = <0x0 0xfd4d0000 0x0 0x1000>; 974 timeout-sec = <60>; 975 reset-on-timeout; 976 }; 977 978 lpd_watchdog: watchdog@ff150000 { 979 compatible = "cdns,wdt-r1p2"; 980 status = "disabled"; 981 interrupt-parent = <&gic>; 982 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 983 reg = <0x0 0xff150000 0x0 0x1000>; 984 timeout-sec = <10>; 985 }; 986 987 xilinx_ams: ams@ffa50000 { 988 compatible = "xlnx,zynqmp-ams"; 989 status = "disabled"; 990 interrupt-parent = <&gic>; 991 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 992 reg = <0x0 0xffa50000 0x0 0x800>; 993 #address-cells = <1>; 994 #size-cells = <1>; 995 #io-channel-cells = <1>; 996 ranges = <0 0 0xffa50800 0x800>; 997 998 ams_ps: ams-ps@0 { 999 compatible = "xlnx,zynqmp-ams-ps"; 1000 status = "disabled"; 1001 reg = <0x0 0x400>; 1002 }; 1003 1004 ams_pl: ams-pl@400 { 1005 compatible = "xlnx,zynqmp-ams-pl"; 1006 status = "disabled"; 1007 reg = <0x400 0x400>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 }; 1011 }; 1012 1013 zynqmp_dpdma: dma-controller@fd4c0000 { 1014 compatible = "xlnx,zynqmp-dpdma"; 1015 status = "disabled"; 1016 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1017 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1018 interrupt-parent = <&gic>; 1019 clock-names = "axi_clk"; 1020 power-domains = <&zynqmp_firmware PD_DP>; 1021 #dma-cells = <1>; 1022 }; 1023 1024 zynqmp_dpsub: display@fd4a0000 { 1025 bootph-all; 1026 compatible = "xlnx,zynqmp-dpsub-1.7"; 1027 status = "disabled"; 1028 reg = <0x0 0xfd4a0000 0x0 0x1000>, 1029 <0x0 0xfd4aa000 0x0 0x1000>, 1030 <0x0 0xfd4ab000 0x0 0x1000>, 1031 <0x0 0xfd4ac000 0x0 0x1000>; 1032 reg-names = "dp", "blend", "av_buf", "aud"; 1033 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1034 interrupt-parent = <&gic>; 1035 clock-names = "dp_apb_clk", "dp_aud_clk", 1036 "dp_vtc_pixel_clk_in"; 1037 power-domains = <&zynqmp_firmware PD_DP>; 1038 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 1039 dma-names = "vid0", "vid1", "vid2", "gfx0"; 1040 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 1041 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 1042 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 1043 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 1044 1045 ports { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 port@0 { 1050 reg = <0>; 1051 }; 1052 port@1 { 1053 reg = <1>; 1054 }; 1055 port@2 { 1056 reg = <2>; 1057 }; 1058 port@3 { 1059 reg = <3>; 1060 }; 1061 port@4 { 1062 reg = <4>; 1063 }; 1064 port@5 { 1065 reg = <5>; 1066 }; 1067 }; 1068 }; 1069 }; 1070}; 1071