xref: /titanic_41/usr/src/uts/sun/io/zs_common.c (revision 193974072f41a843678abf5f61979c748687e66b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  *	Serial I/O driver for Z8530 chips
28  */
29 
30 
31 #include	<sys/types.h>
32 #include	<sys/param.h>
33 #include	<sys/systm.h>
34 #include	<sys/sysmacros.h>
35 #include	<sys/stropts.h>
36 #include	<sys/stream.h>
37 #include	<sys/stat.h>
38 #include	<sys/mkdev.h>
39 #include	<sys/cmn_err.h>
40 #include	<sys/errno.h>
41 #include	<sys/kmem.h>
42 #include	<sys/zsdev.h>
43 #include	<sys/debug.h>
44 #include	<sys/machsystm.h>
45 
46 #include	<sys/conf.h>
47 #include	<sys/sunddi.h>
48 #include	<sys/errno.h>
49 
50 #define	 ZS_TRACING
51 #ifdef  ZS_TRACING
52 #include <sys/vtrace.h>
53 
54 /*
55  * Temp tracepoint definitions
56  */
57 #define	TR_FAC_ZS		51
58 
59 #define	TR_ZS_H_INT_START	1
60 #define	TR_ZS_H_INT_END		2
61 #define	TR_ZS_INT_START		3
62 #define	TR_ZS_INT_END		4
63 
64 #define	TR_FAC_ZS_INT		52
65 #define	TR_READ_START		1
66 #define	TR_READ_END		2
67 
68 #endif  /* ZSH_TRACING */
69 
70 #define	KIOIP		KSTAT_INTR_PTR(zs->intrstats)
71 
72 #ifndef	MAXZS
73 #define	MAXZS		4
74 #endif
75 int maxzs = MAXZS;
76 
77 int nzs = 0;
78 
79 struct zscom *zscom;
80 struct zscom *zscurr;
81 struct zscom *zslast;
82 struct zs_prog *zs_prog;
83 char  *zssoftCAR;
84 int	zs_watchdog_count = 10;	/* countdown to determine if tx hung */
85 
86 int zs_drain_check = 15000000;		/* tunable: exit drain check time */
87 
88 #ifdef ZS_DEBUG
89 char zs_h_log[ZS_H_LOG_MAX +10];
90 int zs_h_log_n = 0;
91 #define	zs_h_log_add(c) \
92 	{ \
93 		if (zs_h_log_n >= ZS_H_LOG_MAX) \
94 			zs_h_log_n = 0; \
95 		zs_h_log[zs_h_log_n++] = c; \
96 		zs_h_log[zs_h_log_n] = '\0'; \
97 	}
98 
99 #else /* NO_ZS_DEBUG */
100 #define	zs_h_log_add(c)
101 #endif /* ZS_DEBUG */
102 
103 
104 /*
105  * Driver data
106  */
107 
108 #define	GETPROP(dip, str, defval) \
109 	ddi_getprop(DDI_DEV_T_ANY, (dip), DDI_PROP_DONTPASS, (str), (defval))
110 
111 int	zs_usec_delay = 1;
112 int	zssoftpend;
113 ddi_softintr_t zs_softintr_id;
114 time_t	default_dtrlow = 3;	/* hold dtr low nearly this long on close */
115 static ddi_iblock_cookie_t zs_iblock;
116 static ddi_iblock_cookie_t zs_hi_iblock;
117 static int zs_addedsoft = 0;
118 
119 
120 /*
121  * Driver information for auto-configuration stuff.
122  */
123 
124 static int zsprobe(dev_info_t *dev);
125 static int zsattach(dev_info_t *dev, ddi_attach_cmd_t cmd);
126 static int zsdetach(dev_info_t *dev, ddi_detach_cmd_t cmd);
127 void	zsopinit(struct zscom *zs, struct zsops *zso);
128 
129 static void zsnull_intr(struct zscom *zs);
130 static int zsnull_softint(struct zscom *zs);
131 static int zsnull_suspend(struct zscom *zs);
132 static int zsnull_resume(struct zscom *zs);
133 
134 struct zsops zsops_null = {
135 			zsnull_intr,
136 			zsnull_intr,
137 			zsnull_intr,
138 			zsnull_intr,
139 			zsnull_softint,
140 			zsnull_suspend,
141 			zsnull_resume
142 };
143 
144 extern struct streamtab asynctab;	/* default -- from zs_async.c */
145 
146 uint_t zs_high_intr(caddr_t argzs);
147 uint_t zsintr(caddr_t intarg);
148 
149 extern int zsc_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg,
150 void **result);
151 
152 extern int ddi_create_internal_pathname(dev_info_t *dip, char *name,
153     int spec_type, minor_t minor_num);
154 
155 extern struct streamtab zsstab;
156 int		zssoftpend;		/* soft interrupt pending */
157 kmutex_t	zs_soft_lock;		/* adapt.lock,to use to protect data */
158 					/* common to sev. streams or ports   */
159 kmutex_t	zs_curr_lock;		/* lock protecting zscurr */
160 
161 extern kcondvar_t lbolt_cv;
162 
163 /*
164  * curently the only spin lock level 12 for all ocasions
165  */
166 
167 #define	ZSS_CONF_FLAG   (D_NEW | D_MP)
168 
169 static  struct cb_ops cb_zs_ops = {
170 	nulldev,		/* cb_open */
171 	nulldev,		/* cb_close */
172 	nodev,			/* cb_strategy */
173 	nodev,			/* cb_print */
174 	nodev,			/* cb_dump */
175 	nodev,			/* cb_read */
176 	nodev,			/* cb_write */
177 	nodev,			/* cb_ioctl */
178 	nodev,			/* cb_devmap */
179 	nodev,			/* cb_mmap */
180 	nodev,			/* cb_segmap */
181 	nochpoll,		/* cb_chpoll */
182 	ddi_prop_op,		/* cb_prop_op */
183 	&asynctab,		/* cb_stream */
184 	(int)(ZSS_CONF_FLAG)	/* cb_flag */
185 };
186 
187 struct dev_ops zs_ops = {
188 	DEVO_REV,		/* devo_rev */
189 	0,			/* devo_refcnt */
190 	zsc_info,		/* devo_getinfo */
191 	nulldev,		/* devo_identify */
192 	zsprobe,		/* devo_probe */
193 	zsattach,		/* devo_attach */
194 	zsdetach,		/* devo_detach */
195 	nodev,			/* devo_reset */
196 	&cb_zs_ops,		/* devo_cb_ops */
197 	(struct bus_ops *)NULL,	/* devo_bus_ops */
198 	ddi_power,		/* devo_power */
199 	ddi_quiesce_not_supported,	/* devo_quiesce */
200 };
201 
202 
203 /*
204  * This is the loadable module wrapper.
205  */
206 
207 #include <sys/modctl.h>
208 
209 /*
210  * Module linkage information for the kernel.
211  */
212 
213 extern struct mod_ops mod_driverops;
214 
215 static struct modldrv modldrv = {
216 		&mod_driverops, /* Type of module.  This one is a driver */
217 		"Z8530 serial driver",
218 		&zs_ops,	/* driver ops */
219 };
220 
221 static struct modlinkage modlinkage = {
222 			MODREV_1, (void *)&modldrv, NULL
223 };
224 
225 int
_init(void)226 _init(void)
227 {
228 	return (mod_install(&modlinkage));
229 }
230 
231 int
_fini(void)232 _fini(void)
233 {
234 	return (EBUSY);
235 }
236 
237 int
_info(struct modinfo * modinfop)238 _info(struct modinfo *modinfop)
239 {
240 	return (mod_info(&modlinkage, modinfop));
241 }
242 
243 static int
zsprobe(dev_info_t * dev)244 zsprobe(dev_info_t *dev)
245 {
246 	struct zscc_device *zsaddr;
247 	int	rval;
248 	auto char	c;
249 
250 	rval = DDI_PROBE_FAILURE;
251 
252 	/*
253 	 * temporarily map in  registers
254 	 */
255 	if (ddi_map_regs(dev, 0, (caddr_t *)&zsaddr, 0, 0)) {
256 		cmn_err(CE_WARN, "zsprobe: unable to map registers");
257 		return (rval);
258 	}
259 
260 	/*
261 	 * NON-DDI Compliant call
262 	 */
263 	mon_clock_stop();
264 
265 	/*
266 	 * get in sync with the chip
267 	 */
268 
269 	if (ddi_peek8(dev, (char *)&zsaddr->zscc_control, &c) != DDI_SUCCESS) {
270 		goto out;
271 	}
272 	drv_usecwait(2);
273 
274 	/*
275 	 * The traditional test for the presence of an 8530 has been to write
276 	 * a 15 (octal 017) to its control register address, then read it back.
277 	 * A Z8530 will respond to this with the contents of Read-Register 15.
278 	 * If this address were memory, or something else, we would expect to
279 	 * see the 15 again.  Normally, the contents of RR15 will be entirely
280 	 * different.  A Z8530 does not use the D0 and D2 bits of register 15,
281 	 * so they should equal zero.  Compatable chips should do the same.
282 	 * Beware of "enhanced" SCC's that do not guarantee this.
283 	 */
284 	if (ddi_poke8(dev, (char *)&zsaddr->zscc_control, '\017')
285 	    != DDI_SUCCESS) {
286 		goto out;
287 	}
288 	drv_usecwait(2);
289 	if (ddi_peek8(dev, (char *)&zsaddr->zscc_control, &c) != DDI_SUCCESS) {
290 		goto out;
291 	}
292 	drv_usecwait(2);
293 	if (c & 5) {
294 		goto out;
295 	}
296 
297 	rval = DDI_PROBE_SUCCESS;
298 
299 out:
300 	/*
301 	 * NON-DDI Compliant call
302 	 */
303 	mon_clock_start();
304 
305 	ddi_unmap_regs(dev, 0, (caddr_t *)&zsaddr, 0, 0);
306 	return (rval);
307 }
308 
309 /*ARGSUSED*/
310 static int
zsattach(dev_info_t * dev,ddi_attach_cmd_t cmd)311 zsattach(dev_info_t *dev, ddi_attach_cmd_t cmd)
312 {
313 	struct zscom	*zs;
314 	int		loops, i;
315 	uint_t		s;
316 	int		rtsdtr_bits = 0;
317 	char			softcd;
318 	uchar_t	rr;
319 	short			speed[2];
320 	int			current_chip = ddi_get_instance(dev);
321 	struct zscc_device	*tmpzs;		/* for mapping purposes */
322 	char name[16];
323 	int keyboard_prop;
324 
325 	switch (cmd) {
326 	case DDI_ATTACH:
327 		break;
328 
329 	case DDI_RESUME:
330 		zs = &zscom[current_chip*2];
331 		/*
332 		 * Try to resume first channel
333 		 */
334 		if (!zs->zs_resume || (zs->zs_resume)(zs) != DDI_SUCCESS)
335 			return (DDI_FAILURE);
336 		/*
337 		 * And the second channel
338 		 */
339 		zs++;
340 		if (!zs->zs_resume || (zs->zs_resume)(zs) != DDI_SUCCESS) {
341 			zs--;
342 			if (!zs->zs_suspend ||
343 			    (zs->zs_suspend)(zs) != DDI_SUCCESS)
344 				cmn_err(CE_WARN,
345 				    "zs: inconsistent suspend/resume state");
346 			return (DDI_FAILURE);
347 		}
348 		return (DDI_SUCCESS);
349 
350 	default:
351 		return (DDI_FAILURE);
352 	}
353 
354 	if (zscom == NULL) {
355 		mutex_init(&zs_soft_lock, NULL, MUTEX_DRIVER, (void *)ZS_PL);
356 		mutex_init(&zs_curr_lock, NULL, MUTEX_DRIVER, (void *)ZS_PL_HI);
357 		zscom = kmem_zalloc(maxzs * sizeof (struct zscom), KM_SLEEP);
358 		zs_prog = kmem_zalloc(maxzs * sizeof (struct zs_prog),
359 		    KM_SLEEP);
360 		zssoftCAR = kmem_zalloc(maxzs, KM_SLEEP);
361 		/* don't set nzs until arrays are allocated */
362 		membar_producer();
363 		nzs = maxzs;
364 		zscurr = &zscom[(current_chip*2) + 1];
365 		zslast = &zscom[current_chip*2];
366 		i = GETPROP(dev, "zs-usec-delay", 0);
367 		zs_usec_delay = (i <= 0) ? 1 : i;
368 	}
369 
370 	if (2 * current_chip >=  maxzs) {
371 		cmn_err(CE_WARN,
372 		    "zs: unable to allocate resources for  chip %d.",
373 		    current_chip);
374 		cmn_err(CE_WARN, "Change zs:maxzs in /etc/system");
375 		return (DDI_FAILURE);
376 	}
377 	zs = &zscom[current_chip*2];
378 
379 	/*
380 	 * map in the device registers
381 	 */
382 	if (ddi_map_regs(dev, 0, (caddr_t *)&zs->zs_addr, 0, 0)) {
383 		cmn_err(CE_WARN, "zs%d: unable to map registers\n",
384 		    current_chip);
385 		return (DDI_FAILURE);
386 	}
387 
388 	tmpzs = zs->zs_addr;
389 
390 	/*
391 	 * Non-DDI compliant Sun-Ness specfic call(s)
392 	 */
393 
394 	/*
395 	 * Stop the monitor's polling interrupt.
396 	 *
397 	 * I know that this is not exactly obvious. On all sunmon PROM
398 	 * machines, the PROM has can have a high level periodic clock
399 	 * interrupt going at this time. It uses this periodic interrupt
400 	 * to poll the console tty or kbd uart to check for things like
401 	 * BREAK or L1-A (abort). While we're probing this device out we
402 	 * have to shut that off so the PROM won't get confused by what
403 	 * we're doing to the zs. This has caused some pretty funny bugs
404 	 * in its time.
405 	 *
406 	 * For OPENPROM machines, the prom  takes level12 interrupts directly,
407 	 * but we call this routine anyway (I forget why).
408 	 */
409 	mon_clock_stop();
410 
411 	/*
412 	 * Go critical to keep uart from urking.
413 	 */
414 	s = ddi_enter_critical();
415 
416 	/*
417 	 * We are about to issue a full reset to this chip.
418 	 * First, now that interrupts are blocked, we will delay up to a
419 	 * half-second, checking both channels for any stray activity.
420 	 * Next we will preserve the time constants from both channels,
421 	 * so that they can be restored after the reset.  This is especially
422 	 * important for the console device.  Finally, do the reset and
423 	 * follow it with an extended recovery while the chip settles down.
424 	 */
425 	for (loops = 0; loops++ <= 500; DELAY(1000)) {
426 		SCC_READA(1, rr);
427 		if ((rr & ZSRR1_ALL_SENT) == 0) continue;
428 		SCC_READB(1, rr);
429 		if ((rr & ZSRR1_ALL_SENT) == 0) continue;
430 		SCC_READA(0, rr);
431 		if ((rr & ZSRR0_TX_READY) == 0) continue;
432 		SCC_READB(0, rr);
433 		if ((rr & ZSRR0_TX_READY) != 0) break;
434 	}
435 
436 	SCC_READA(12, speed[0]);
437 	SCC_READA(13, rr);
438 	speed[0] |= rr << 8;
439 	SCC_READB(12, speed[1]);
440 	SCC_READB(13, rr);
441 	speed[1] |= rr << 8;
442 
443 	SCC_WRITE(9, ZSWR9_RESET_WORLD);
444 	DELAY(10);
445 
446 	/*
447 	 * Set up the other components of the zscom structs for this chip.
448 	 */
449 	for (i = 0; i < 2; i++) {
450 		/*
451 		 * Property for ignoring DCD.
452 		 * We switch between 'a' and 'b' ports for this device.
453 		 */
454 		static char prop[] = "port-a-ignore-cd";
455 
456 		/*
457 		 * For this channel, set the hardware address, allocate the
458 		 * high-level mutex, and update the zscurr pointer.
459 		 * The high-level lock is shared by both channels because
460 		 * 8530 register addressing is non-atomic and asymetrical.
461 		 * Multiple threads crossing paths during this operation
462 		 * could trash the chip, and thus, possibly the system console.
463 		 */
464 		if (i == 0) {		/* port A */
465 			zs->zs_addr = (struct zscc_device *)
466 			    ((uintptr_t)tmpzs | ZSOFF);
467 			(zs+1)->zs_excl_hi = zs->zs_excl_hi = &zs_curr_lock;
468 		} else {		/* port B */
469 			zs++;
470 			zs->zs_addr = (struct zscc_device *)
471 			    ((uintptr_t)tmpzs & ~ZSOFF);
472 			zscurr = zs;
473 		}
474 		zs->zs_unit = current_chip * 2 + i;
475 		zs->zs_dip = dev;
476 		zs->zs_excl = kmem_zalloc(sizeof (kmutex_t), KM_SLEEP);
477 		mutex_init(zs->zs_excl, NULL, MUTEX_DRIVER, (void *)ZS_PL);
478 		zs->zs_ocexcl = kmem_zalloc(sizeof (kmutex_t), KM_SLEEP);
479 		mutex_init(zs->zs_ocexcl, NULL, MUTEX_DRIVER, (void *)ZS_PL);
480 
481 		zsopinit(zs, &zsops_null);
482 
483 		prop[5] = 'a' + i;
484 		softcd = GETPROP((dev_info_t *)(dev), prop, 0);
485 		zssoftCAR[zs->zs_unit] = softcd;
486 		if (softcd)
487 			rtsdtr_bits = ZSWR5_RTS | ZSWR5_DTR;
488 
489 		keyboard_prop = GETPROP((dev_info_t *)(zs->zs_dip),
490 		    "keyboard", 0);
491 
492 		mutex_enter(&zs_curr_lock);
493 
494 		/*
495 		 * Set up the default asynch modes
496 		 * so the monitor will still work
497 		 */
498 		SCC_WRITE(4, ZSWR4_PARITY_EVEN | ZSWR4_1_STOP | ZSWR4_X16_CLK);
499 		SCC_WRITE(3, ZSWR3_RX_8);
500 		SCC_WRITE(11, ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD);
501 		SCC_WRITE(12, (speed[i] & 0xff));
502 		SCC_WRITE(13, (speed[i] >> 8) & 0xff);
503 		SCC_WRITE(14, ZSWR14_BAUD_FROM_PCLK);
504 		SCC_WRITE(3, ZSWR3_RX_8 | ZSWR3_RX_ENABLE);
505 		SCC_WRITE(5, ZSWR5_TX_ENABLE | ZSWR5_TX_8 | rtsdtr_bits);
506 		SCC_WRITE(14, ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK);
507 
508 		/*
509 		 * The SYNC pin on the second SCC (keyboard & mouse) may not
510 		 * be connected and noise creates transitions on this line.
511 		 * This floods the system with interrupts, unless the
512 		 * Sync/Hunt Interrupt Enable is cleared.  So write
513 		 * register 15 with everything we need but that one.
514 		 */
515 		if (keyboard_prop) {
516 			SCC_WRITE(15, ZSR15_BREAK | ZSR15_TX_UNDER |
517 			    ZSR15_CTS | ZSR15_CD);
518 		}
519 
520 		SCC_WRITE0(ZSWR0_RESET_ERRORS);
521 		SCC_WRITE0(ZSWR0_RESET_STATUS);
522 		mutex_exit(&zs_curr_lock);
523 
524 		zs->zs_dtrlow = gethrestime_sec() - default_dtrlow;
525 		cv_init(&zs->zs_flags_cv, NULL, CV_DEFAULT, NULL);
526 		zsa_init(zs);
527 	}
528 
529 	mutex_enter(&zs_curr_lock);
530 	SCC_WRITE(9, ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT);
531 	DELAY(4000);
532 	mutex_exit(&zs_curr_lock);
533 
534 	/*
535 	 * Two levels of interrupt - chip interrupts at a high level (12),
536 	 * (which is seen below as zs_high_intr), and then as a secondary
537 	 * stage soft interrupt as seen in zsintr below.
538 	 *
539 	 * Because zs_high_intr does a window save, as well as calls to
540 	 * other functions, we cannot install it as a "fast" interrupt
541 	 * that would execute right out of the trap window.  Too bad...
542 	 */
543 	if (ddi_add_intr(dev, (uint_t)0, &zs_hi_iblock,
544 	    (ddi_idevice_cookie_t *)0, zs_high_intr,
545 	    (caddr_t)0) != DDI_SUCCESS) {
546 		cmn_err(CE_PANIC, "cannot set high level zs interrupt");
547 		/*NOTREACHED*/
548 	}
549 
550 	if (zs_addedsoft == 0) {
551 		if (ddi_add_softintr(dev, DDI_SOFTINT_HIGH, &zs_softintr_id,
552 		    &zs_iblock, (ddi_idevice_cookie_t *)0,
553 		    zsintr, (caddr_t)0) != DDI_SUCCESS) {
554 			cmn_err(CE_PANIC,
555 			    "cannot set second stage zs interrupt");
556 			/*NOTREACHED*/
557 		}
558 
559 		zs_addedsoft++;	/* we only need one zsintr! */
560 	}
561 
562 	if (zs > zslast)
563 		zslast = zs;
564 
565 	(void) ddi_exit_critical(s);
566 
567 	/*
568 	 * Non-DDI compliant Sun-Ness specific call
569 	 */
570 	mon_clock_start();	/* re-enable monitor's polling interrupt */
571 
572 	if (!GETPROP(zs->zs_dip, "keyboard", 0)) {
573 		static char *serial_line = DDI_NT_SERIAL_MB;
574 		static char *dial_out = DDI_NT_SERIAL_MB_DO;
575 
576 		/*
577 		 * Export names for channel a or b consconfig match...
578 		 * The names exported to the filesystem include the
579 		 * designated tty'a' type name and may not match the PROM
580 		 * pathname.
581 		 * Note the special name "obp-console-name" used in these calls.
582 		 * This keeps the ports and devlinks programs from seeing these
583 		 * names. (But allows ddi_pathname_to_dev_t to see them.)
584 		 * We don't need to do this if the instance number is zero,
585 		 * because we'll create them below, in this case.
586 		 */
587 
588 		if (ddi_get_instance(dev) != 0)  {
589 
590 			/*
591 			 * Select a node type unused by ddi/devfs
592 			 */
593 			static char *obp_type = "obp-console-name";
594 
595 			(void) strcpy(name, "a");
596 			if (ddi_create_minor_node(dev, name, S_IFCHR,
597 			    ddi_get_instance(dev) * 2,
598 			    obp_type, NULL) == DDI_FAILURE) {
599 				ddi_remove_minor_node(dev, NULL);
600 				return (DDI_FAILURE);
601 			}
602 			(void) strcpy(name, "b");
603 			if (ddi_create_minor_node(dev, name, S_IFCHR,
604 			    (ddi_get_instance(dev) * 2) + 1,
605 			    obp_type, NULL) == DDI_FAILURE) {
606 				ddi_remove_minor_node(dev, NULL);
607 				return (DDI_FAILURE);
608 			}
609 		}
610 
611 		/*
612 		 * Export normal device names...
613 		 */
614 		(void) sprintf(name, "%c", (ddi_get_instance(dev) + 'a'));
615 		if (ddi_create_minor_node(dev, name, S_IFCHR,
616 		    ddi_get_instance(dev) * 2,
617 		    serial_line, NULL) == DDI_FAILURE) {
618 			ddi_remove_minor_node(dev, NULL);
619 			return (DDI_FAILURE);
620 		}
621 		(void) sprintf(name, "%c", (ddi_get_instance(dev) + 'b'));
622 		if (ddi_create_minor_node(dev, name, S_IFCHR,
623 		    (ddi_get_instance(dev) * 2) + 1,
624 		    serial_line, NULL) == DDI_FAILURE) {
625 			ddi_remove_minor_node(dev, NULL);
626 			return (DDI_FAILURE);
627 		}
628 		(void) sprintf(name, "%c,cu", (ddi_get_instance(dev) + 'a'));
629 		if (ddi_create_minor_node(dev, name, S_IFCHR,
630 		    (ddi_get_instance(dev) * 2) | OUTLINE,
631 		    dial_out, NULL) == DDI_FAILURE) {
632 			ddi_remove_minor_node(dev, NULL);
633 			return (DDI_FAILURE);
634 		}
635 		(void) sprintf(name, "%c,cu", (ddi_get_instance(dev) + 'b'));
636 		if (ddi_create_minor_node(dev, name, S_IFCHR,
637 		    ((ddi_get_instance(dev)  * 2) + 1) | OUTLINE,
638 		    dial_out, NULL) == DDI_FAILURE) {
639 			ddi_remove_minor_node(dev, NULL);
640 			return (DDI_FAILURE);
641 		}
642 	} else {
643 
644 		/*
645 		 * Create keyboard and mouse nodes which devfs doesn't see
646 		 */
647 
648 		/*
649 		 * This set of minor nodes is for use with the consconfig_dacf
650 		 * module for the sun4u platforms.  (See PSARC/1998/212)
651 		 */
652 		if (ddi_create_internal_pathname(dev, "keyboard", S_IFCHR,
653 		    ddi_get_instance(dev) * 2) == DDI_FAILURE) {
654 			ddi_remove_minor_node(dev, NULL);
655 			return (DDI_FAILURE);
656 		}
657 
658 		if (ddi_create_internal_pathname(dev, "mouse", S_IFCHR,
659 		    (ddi_get_instance(dev) * 2) + 1) == DDI_FAILURE) {
660 			ddi_remove_minor_node(dev, NULL);
661 			return (DDI_FAILURE);
662 		}
663 
664 		/*
665 		 * These minor nodes are for use with pre-sun4u platforms.
666 		 * Either one set or the other will be opened by consconfig.
667 		 */
668 		(void) strcpy(name, "a");
669 		if (ddi_create_internal_pathname(dev, name, S_IFCHR,
670 		    ddi_get_instance(dev) * 2) == DDI_FAILURE) {
671 			ddi_remove_minor_node(dev, NULL);
672 			return (DDI_FAILURE);
673 		}
674 
675 		(void) strcpy(name, "b");
676 		if (ddi_create_internal_pathname(dev, name, S_IFCHR,
677 		    (ddi_get_instance(dev) * 2) + 1) == DDI_FAILURE) {
678 			ddi_remove_minor_node(dev, NULL);
679 			return (DDI_FAILURE);
680 		}
681 
682 	}
683 
684 	ddi_report_dev(dev);
685 	/*
686 	 * Initialize power management bookkeeping; components are
687 	 * created idle.
688 	 */
689 	if (pm_create_components(dev, 3) == DDI_SUCCESS) {
690 		(void) pm_busy_component(dev, 0);
691 		pm_set_normal_power(dev, 0, 1);
692 		pm_set_normal_power(dev, 1, 1);
693 		pm_set_normal_power(dev, 2, 1);
694 	} else {
695 		return (DDI_FAILURE);
696 	}
697 
698 	(void) sprintf(name, "zsc%d", current_chip);
699 	zs->intrstats = kstat_create("zs", current_chip, name, "controller",
700 	    KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT);
701 	if (zs->intrstats) {
702 		kstat_install(zs->intrstats);
703 	}
704 
705 	return (DDI_SUCCESS);
706 }
707 
708 static int
zsdetach(dev_info_t * dev,ddi_detach_cmd_t cmd)709 zsdetach(dev_info_t *dev, ddi_detach_cmd_t cmd)
710 {
711 	struct zscom *zs;
712 	int	current_chip = ddi_get_instance(dev);
713 
714 	switch (cmd) {
715 	case DDI_DETACH:
716 		return (DDI_FAILURE);
717 
718 	case DDI_SUSPEND:
719 		zs = &zscom[current_chip*2];
720 		/*
721 		 * Try to suspend first channel
722 		 */
723 		if (!zs->zs_suspend || (zs->zs_suspend)(zs) != DDI_SUCCESS)
724 			return (DDI_FAILURE);
725 		/*
726 		 * And the second channel
727 		 */
728 		zs++;
729 		if (!zs->zs_suspend || (zs->zs_suspend)(zs) != DDI_SUCCESS) {
730 			zs--;
731 			if (!zs->zs_resume ||
732 			    (zs->zs_resume)(zs) != DDI_SUCCESS)
733 				cmn_err(CE_WARN,
734 				    "zs: inconsistent suspend/resume state");
735 			return (DDI_FAILURE);
736 		}
737 		return (DDI_SUCCESS);
738 
739 	default:
740 		return (DDI_FAILURE);
741 	}
742 }
743 
744 /*
745  * SCC High Level Interrupt Handler
746  *
747  * This routine fields the level 12 interrupts generated by the 8530 chips.
748  * When the SCC interrupts the conditions that triggered it are available
749  * for reference in Read Register 3 of the A channel (RR3A).  We process
750  * all the pending interrupts before returning.  The maximum interrupts
751  * that will be processed before returning is set to 6, which is twice
752  * the size of RX-FIFO.
753  * We keep a pointer to the B side of the most recently interrupting chip
754  * in zscurr.
755  */
756 
757 /*
758  * 'argzs' actually 'struct zscom *argzs'
759  */
760 
761 #define	ZSRR3_INT_PENDING (ZSRR3_IP_B_STAT | ZSRR3_IP_B_TX | ZSRR3_IP_B_RX |\
762 			ZSRR3_IP_A_STAT | ZSRR3_IP_A_TX | ZSRR3_IP_A_RX)
763 
764 #define	ZSRR1_ANY_ERRORS (ZSRR1_PE | ZSRR1_DO | ZSRR1_FE | ZSRR1_RXEOF)
765 #define	ZS_HIGH_INTR_LOOPLIMIT 6
766 
767 /*ARGSUSED*/
768 uint_t
zs_high_intr(caddr_t argzs)769 zs_high_intr(caddr_t argzs)
770 {
771 	struct zscom	*zs;
772 	uchar_t	stat, isource, count;
773 	int		unit;
774 
775 	TRACE_0(TR_FAC_ZS, TR_ZS_H_INT_START, "zs_h_int start");
776 	mutex_enter(&zs_curr_lock);
777 	zs = zscurr;				/* Points at Channel B */
778 
779 	ZSNEXTPOLL(zs, zscurr);
780 
781 	SCC_READA(3, isource);
782 start_zs_h:
783 	count = ZS_HIGH_INTR_LOOPLIMIT;
784 	while ((isource & ZSRR3_INT_PENDING) && (count--)) {
785 		if (isource & ZSRR3_IP_B_STAT)
786 			(zs->zs_xsint)(zs);
787 		else {
788 			if (isource & ZSRR3_IP_B_TX)
789 				(zs->zs_txint)(zs);
790 			if (isource & ZSRR3_IP_B_RX) {
791 				SCC_READ(1, stat);
792 				if (stat & ZSRR1_ANY_ERRORS)
793 					(zs->zs_srint)(zs);
794 				else if ((SCC_READ0()) & ZSRR0_RX_READY)
795 					(zs->zs_rxint)(zs);
796 			}
797 		}
798 
799 		zs -= 1;
800 		if (isource & ZSRR3_IP_A_STAT)
801 			(zs->zs_xsint)(zs);
802 		else {
803 			if (isource & ZSRR3_IP_A_TX)
804 				(zs->zs_txint)(zs);
805 			if (isource & ZSRR3_IP_A_RX) {
806 				SCC_READ(1, stat);
807 				if (stat & ZSRR1_ANY_ERRORS)
808 					(zs->zs_srint)(zs);
809 				else if ((SCC_READ0()) & ZSRR0_RX_READY)
810 					(zs->zs_rxint)(zs);
811 			}
812 		}
813 
814 		zs = zscurr;
815 		SCC_READA(3, isource);
816 	}
817 
818 	if (count == ZS_HIGH_INTR_LOOPLIMIT) {
819 		unit = (nzs >> 1) - 1;
820 		while (unit--) {
821 			zs += 2;	/* Always Channel B */
822 			if (zs > zslast)
823 				zs = &zscom[1];
824 			if (!zs->zs_ops)
825 				continue;
826 			SCC_READA(3, isource);
827 			if (isource & ZSRR3_INT_PENDING) {
828 				zscurr = zs;	/* update zscurr and */
829 				goto start_zs_h;
830 			}
831 		}
832 		if (zs->intrstats) {
833 			KIOIP->intrs[KSTAT_INTR_HARD]++;
834 		}
835 		mutex_exit(&zs_curr_lock);
836 		TRACE_0(TR_FAC_ZS, TR_ZS_H_INT_END, "zs_h_int end");
837 		return (DDI_INTR_UNCLAIMED);	/* Must not be for us. */
838 	}
839 	if (zs->intrstats) {
840 		KIOIP->intrs[KSTAT_INTR_HARD]++;
841 	}
842 	mutex_exit(&zs_curr_lock);	/* we're done with zscurr */
843 	TRACE_0(TR_FAC_ZS, TR_ZS_H_INT_END, "zs_h_int end");
844 	return (DDI_INTR_CLAIMED);
845 }
846 
847 /*
848  * Handle a second-stage interrupt.
849  */
850 /*ARGSUSED*/
851 uint_t
zsintr(caddr_t intarg)852 zsintr(caddr_t intarg)
853 {
854 	struct zscom *zs;
855 	int    rv;
856 
857 	/*
858 	 * Test and clear soft interrupt.
859 	 */
860 	TRACE_0(TR_FAC_ZS, TR_ZS_INT_START,
861 	    "zs_int start");
862 
863 	mutex_enter(&zs_curr_lock);
864 	rv = zssoftpend;
865 	if (rv != 0) {
866 		zssoftpend = 0;
867 	}
868 	mutex_exit(&zs_curr_lock);
869 
870 	if (rv) {
871 		for (zs = &zscom[0]; zs <= zslast; zs++) {
872 			if (zs->zs_flags & ZS_NEEDSOFT) {
873 				zs->zs_flags &= ~ZS_NEEDSOFT;
874 				(*zs->zs_ops->zsop_softint)(zs);
875 				if (zs->intrstats) {
876 					KIOIP->intrs[KSTAT_INTR_SOFT]++;
877 				}
878 			}
879 		}
880 	}
881 	TRACE_0(TR_FAC_ZS, TR_ZS_INT_END,
882 	    "zs_int end");
883 	return (rv);
884 }
885 
886 void
setzssoft(void)887 setzssoft(void)
888 {
889 	ddi_trigger_softintr(zs_softintr_id);
890 }
891 
892 /*
893  * Install a new ops vector into low level vector routine addresses
894  */
895 void
zsopinit(struct zscom * zs,struct zsops * zso)896 zsopinit(struct zscom *zs, struct zsops *zso)
897 {
898 	zs->zs_txint	= zso->zsop_txint;
899 	zs->zs_xsint	= zso->zsop_xsint;
900 	zs->zs_rxint	= zso->zsop_rxint;
901 	zs->zs_srint	= zso->zsop_srint;
902 	zs->zs_suspend	= zso->zsop_suspend;
903 	zs->zs_resume	= zso->zsop_resume;
904 	zs->zs_ops	= zso;
905 	zs->zs_flags	= 0;
906 }
907 
908 /*
909  * Set or get the modem control status.
910  *
911  * This routine relies on the fact that the bits of interest in RR0 (CD and
912  * CTS) do not overlap the bits of interest in WR5 (RTS and DTR).  Thus, they
913  * can be combined into a single 'int' without harm.
914  */
915 int
zsmctl(struct zscom * zs,int bits,int how)916 zsmctl(struct zscom *zs, int bits, int how)
917 {
918 	int mbits, obits;
919 	time_t now, held;
920 
921 	ASSERT(mutex_owned(zs->zs_excl_hi));
922 	ASSERT(mutex_owned(zs->zs_excl));
923 
924 again:
925 	mbits = zs->zs_wreg[5] & (ZSWR5_RTS|ZSWR5_DTR);
926 	SCC_WRITE0(ZSWR0_RESET_STATUS);
927 	mbits |= SCC_READ0() & (ZSRR0_CD|ZSRR0_CTS);
928 	ZSDELAY();
929 	obits = mbits;
930 
931 	switch (how) {
932 
933 	case DMSET:
934 		mbits = bits;
935 		break;
936 
937 	case DMBIS:
938 		mbits |= bits;
939 		break;
940 
941 	case DMBIC:
942 		mbits &= ~bits;
943 		break;
944 
945 	case DMGET:
946 		return (mbits);
947 	}
948 
949 	now = gethrestime_sec();
950 	held = now - zs->zs_dtrlow;
951 
952 	/*
953 	 * if DTR is going low, stash current time away
954 	 */
955 	if (~mbits & obits & ZSWR5_DTR)
956 		zs->zs_dtrlow = now;
957 
958 	/*
959 	 * if DTR is going high, sleep until it has been low a bit
960 	 */
961 	if ((mbits & ~obits & ZSWR5_DTR) && (held < default_dtrlow)) {
962 		mutex_exit(zs->zs_excl_hi);
963 		cv_wait(&lbolt_cv, zs->zs_excl);
964 		if (zs->zs_suspended)
965 			(void) ddi_dev_is_needed(zs->zs_dip, 0, 1);
966 		mutex_enter(zs->zs_excl_hi);
967 		goto again;
968 	}
969 
970 	zs->zs_wreg[5] &= ~(ZSWR5_RTS|ZSWR5_DTR);
971 	SCC_BIS(5, mbits & (ZSWR5_RTS|ZSWR5_DTR));
972 	return (mbits);
973 }
974 
975 /*
976  * Program the Z8530 registers.
977  */
978 void
zs_program(struct zs_prog * zspp)979 zs_program(struct zs_prog *zspp)
980 {
981 	struct zscom *zs = zspp->zs;
982 	int	loops;
983 	uchar_t	c;
984 	uchar_t wr10 = 0, wr14 = 0;
985 
986 	ASSERT(mutex_owned(zs->zs_excl));
987 	ASSERT(mutex_owned(zs->zs_excl_hi));
988 
989 	/*
990 	 * There are some special cases to account for before reprogramming.
991 	 * We might be transmitting, so delay 100,000 usec (worst case at 110
992 	 * baud) for this to finish, then disable the receiver until later,
993 	 * reset the External Status Change latches and the error bits, and
994 	 * drain the receive FIFO.
995 	 * XXX: Doing any kind of reset (WR9) here causes trouble!
996 	 */
997 	if (zspp->flags & ZSP_SYNC) {
998 		SCC_WRITE(7, SDLCFLAG);
999 		wr10 = ZSWR10_PRESET_ONES;
1000 		if (zspp->flags & ZSP_NRZI)
1001 			wr10 |= ZSWR10_NRZI;
1002 		SCC_WRITE(10, wr10);
1003 	} else {
1004 		for (loops = 1000; loops > 0; --loops) {
1005 			SCC_READ(1, c);
1006 			if (c & ZSRR1_ALL_SENT)
1007 				break;
1008 			DELAY(100);
1009 		}
1010 		SCC_WRITE(3, 0);
1011 		SCC_WRITE0(ZSWR0_RESET_STATUS);
1012 		SCC_WRITE0(ZSWR0_RESET_ERRORS);
1013 		c = SCC_READDATA();		/* Empty the FIFO */
1014 		c = SCC_READDATA();
1015 		c = SCC_READDATA();
1016 	}
1017 
1018 	/*
1019 	 * Programming the SCC is done in three phases.
1020 	 * Phase one sets operating modes:
1021 	 */
1022 	SCC_WRITE(4, zspp->wr4);
1023 	SCC_WRITE(11, zspp->wr11);
1024 	SCC_WRITE(12, zspp->wr12);
1025 	SCC_WRITE(13, zspp->wr13);
1026 	if (zspp->flags & ZSP_PLL) {
1027 		SCC_WRITE(14, ZSWR14_DPLL_SRC_BAUD);
1028 		SCC_WRITE(14, ZSWR14_DPLL_NRZI);
1029 	} else
1030 		SCC_WRITE(14, ZSWR14_DPLL_DISABLE);
1031 
1032 	/*
1033 	 * Phase two enables special hardware functions:
1034 	 */
1035 	wr14 = ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA;
1036 	if (zspp->flags & ZSP_LOOP)
1037 		wr14 |= ZSWR14_LOCAL_LOOPBACK;
1038 	if (zspp->flags & ZSP_ECHO)
1039 		wr14 |= ZSWR14_AUTO_ECHO;
1040 	SCC_WRITE(14, wr14);
1041 	SCC_WRITE(3, zspp->wr3);
1042 	SCC_WRITE(5, zspp->wr5);
1043 
1044 	SCC_WRITE0(ZSWR0_RESET_TXCRC);
1045 
1046 	if (zspp->flags & ZSP_PARITY_SPECIAL) {
1047 		SCC_WRITE(1, ZSWR1_PARITY_SPECIAL);
1048 	} else {
1049 		SCC_WRITE(1, 0);
1050 	}
1051 
1052 	/*
1053 	 * Phase three enables interrupt sources:
1054 	 */
1055 	SCC_WRITE(15, zspp->wr15);
1056 	SCC_WRITE0(ZSWR0_RESET_STATUS);
1057 	SCC_WRITE0(ZSWR0_RESET_ERRORS);
1058 	SCC_BIS(1, ZSWR1_INIT);
1059 }
1060 
1061 static void
zsnull_intr(struct zscom * zs)1062 zsnull_intr(struct zscom *zs)
1063 {
1064 	short	c;
1065 
1066 	SCC_WRITE0(ZSWR0_RESET_TXINT);
1067 	SCC_WRITE0(ZSWR0_RESET_STATUS);
1068 	c = SCC_READDATA();
1069 	ZSDELAY();
1070 #ifdef lint
1071 	c = c;
1072 #endif /* lint */
1073 	SCC_WRITE0(ZSWR0_RESET_ERRORS);
1074 }
1075 
1076 static int
zsnull_softint(struct zscom * zs)1077 zsnull_softint(struct zscom *zs)
1078 {
1079 	cmn_err(CE_WARN, "zs%d: unexpected soft int\n", zs->zs_unit);
1080 	return (0);
1081 }
1082 
1083 /*
1084  * These will be called on suspend/resume for un-opened zs ports.
1085  */
1086 static int
zsnull_suspend(struct zscom * zs)1087 zsnull_suspend(struct zscom *zs)
1088 {
1089 	struct zs_prog	*zspp = &zs_prog[zs->zs_unit];
1090 
1091 	/*
1092 	 * Get a copy of the current registers
1093 	 */
1094 	mutex_enter(zs->zs_excl);
1095 	mutex_enter(zs->zs_excl_hi);
1096 	zspp->zs = zs;
1097 	zspp->flags = 0;
1098 	zspp->wr3 = zs->zs_wreg[3];
1099 	zspp->wr4 = zs->zs_wreg[4];
1100 	zspp->wr5 = zs->zs_wreg[5];
1101 	zspp->wr11 = zs->zs_wreg[11];
1102 	zspp->wr12 = zs->zs_wreg[12];
1103 	zspp->wr13 = zs->zs_wreg[13];
1104 	zspp->wr15 = zs->zs_wreg[15];
1105 	mutex_exit(zs->zs_excl_hi);
1106 	mutex_exit(zs->zs_excl);
1107 
1108 	return (DDI_SUCCESS);
1109 }
1110 
1111 static int
zsnull_resume(struct zscom * zs)1112 zsnull_resume(struct zscom *zs)
1113 {
1114 	struct zs_prog	*zspp = &zs_prog[zs->zs_unit];
1115 
1116 	/*
1117 	 * Restore registers
1118 	 */
1119 	mutex_enter(zs->zs_excl);
1120 	mutex_enter(zs->zs_excl_hi);
1121 	zs_program(zspp);
1122 	SCC_WRITE(9, ZSWR9_MASTER_IE);
1123 	DELAY(4000);
1124 	mutex_exit(zs->zs_excl_hi);
1125 	mutex_exit(zs->zs_excl);
1126 	return (DDI_SUCCESS);
1127 }
1128