1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 17 /* 18 * Test the various forms NPS 1K/2K non-power of 2 variants that we have. 19 * Specifically: 20 * 21 * o 3 Channels (1K, 1P) 22 * o 6 channels (2K, 1P) 23 * o 5 channels (2K, 1P) 24 * o 10 channels (1K, 1P) 25 */ 26 27 #include "zen_umc_test.h" 28 29 /* 30 * Our first lovely non-power of 2 configuration. This is a 1K 3 channel config. 31 * Back to normal sized DIMMs. 32 */ 33 static const zen_umc_t zen_umc_nps_3ch_1k = { 34 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 35 .umc_tom2 = 48ULL * 1024ULL * 1024ULL * 1024ULL, 36 .umc_df_rev = DF_REV_4D2, 37 .umc_decomp = { 38 .dfd_sock_mask = 0x01, 39 .dfd_die_mask = 0x00, 40 .dfd_node_mask = 0x20, 41 .dfd_comp_mask = 0x1f, 42 .dfd_sock_shift = 0, 43 .dfd_die_shift = 0, 44 .dfd_node_shift = 5, 45 .dfd_comp_shift = 0 46 }, 47 .umc_ndfs = 1, 48 .umc_dfs = { { 49 .zud_dfno = 0, 50 .zud_dram_nrules = 1, 51 .zud_nchan = 3, 52 .zud_cs_nremap = 0, 53 .zud_hole_base = 0, 54 .zud_rules = { { 55 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 56 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 57 .ddr_base = 0, 58 .ddr_limit = 48ULL * 1024ULL * 1024ULL * 1024ULL, 59 .ddr_dest_fabid = 0, 60 .ddr_sock_ileave_bits = 0, 61 .ddr_die_ileave_bits = 0, 62 .ddr_addr_start = 8, 63 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH_1K 64 } }, 65 .zud_chan = { { 66 .chan_flags = UMC_CHAN_F_ECC_EN, 67 .chan_fabid = 0, 68 .chan_instid = 0, 69 .chan_logid = 0, 70 .chan_nrules = 1, 71 .chan_type = UMC_DIMM_T_DDR5, 72 .chan_rules = { { 73 .ddr_flags = DF_DRAM_F_VALID | 74 DF_DRAM_F_HASH_16_18 | 75 DF_DRAM_F_HASH_21_23 | 76 DF_DRAM_F_HASH_30_32, 77 .ddr_base = 0, 78 .ddr_limit = 48ULL * 1024ULL * 1024ULL * 79 1024ULL, 80 .ddr_dest_fabid = 0, 81 .ddr_sock_ileave_bits = 0, 82 .ddr_die_ileave_bits = 0, 83 .ddr_addr_start = 8, 84 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH_1K 85 } }, 86 .chan_dimms = { { 87 .ud_flags = UMC_DIMM_F_VALID, 88 .ud_width = UMC_DIMM_W_X4, 89 .ud_kind = UMC_DIMM_K_RDIMM, 90 .ud_dimmno = 0, 91 .ud_cs = { { 92 .ucs_flags = UMC_CS_F_DECODE_EN, 93 .ucs_base = { 94 .udb_base = 0, 95 .udb_valid = B_TRUE 96 }, 97 .ucs_base_mask = 0x3ffffffff, 98 .ucs_nbanks = 0x5, 99 .ucs_ncol = 0xa, 100 .ucs_nrow_lo = 0x10, 101 .ucs_nbank_groups = 0x3, 102 .ucs_row_low_bit = 0x12, 103 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 104 0xe }, 105 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 106 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 107 .ucs_subchan = 0x6 108 } } 109 } }, 110 }, { 111 .chan_flags = UMC_CHAN_F_ECC_EN, 112 .chan_fabid = 1, 113 .chan_instid = 1, 114 .chan_logid = 1, 115 .chan_nrules = 1, 116 .chan_type = UMC_DIMM_T_DDR5, 117 .chan_rules = { { 118 .ddr_flags = DF_DRAM_F_VALID | 119 DF_DRAM_F_HASH_16_18 | 120 DF_DRAM_F_HASH_21_23 | 121 DF_DRAM_F_HASH_30_32, 122 .ddr_base = 0, 123 .ddr_limit = 48ULL * 1024ULL * 1024ULL * 124 1024ULL, 125 .ddr_dest_fabid = 0, 126 .ddr_sock_ileave_bits = 0, 127 .ddr_die_ileave_bits = 0, 128 .ddr_addr_start = 8, 129 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH_1K 130 } }, 131 .chan_dimms = { { 132 .ud_flags = UMC_DIMM_F_VALID, 133 .ud_width = UMC_DIMM_W_X4, 134 .ud_kind = UMC_DIMM_K_RDIMM, 135 .ud_dimmno = 0, 136 .ud_cs = { { 137 .ucs_flags = UMC_CS_F_DECODE_EN, 138 .ucs_base = { 139 .udb_base = 0, 140 .udb_valid = B_TRUE 141 }, 142 .ucs_base_mask = 0x3ffffffff, 143 .ucs_nbanks = 0x5, 144 .ucs_ncol = 0xa, 145 .ucs_nrow_lo = 0x10, 146 .ucs_nbank_groups = 0x3, 147 .ucs_row_low_bit = 0x12, 148 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 149 0xe }, 150 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 151 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 152 .ucs_subchan = 0x6 153 } } 154 } }, 155 }, { 156 .chan_flags = UMC_CHAN_F_ECC_EN, 157 .chan_fabid = 2, 158 .chan_instid = 2, 159 .chan_logid = 2, 160 .chan_nrules = 1, 161 .chan_type = UMC_DIMM_T_DDR5, 162 .chan_rules = { { 163 .ddr_flags = DF_DRAM_F_VALID | 164 DF_DRAM_F_HASH_16_18 | 165 DF_DRAM_F_HASH_21_23 | 166 DF_DRAM_F_HASH_30_32, 167 .ddr_base = 0, 168 .ddr_limit = 48ULL * 1024ULL * 1024ULL * 169 1024ULL, 170 .ddr_dest_fabid = 0, 171 .ddr_sock_ileave_bits = 0, 172 .ddr_die_ileave_bits = 0, 173 .ddr_addr_start = 8, 174 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_3CH_1K 175 } }, 176 .chan_dimms = { { 177 .ud_flags = UMC_DIMM_F_VALID, 178 .ud_width = UMC_DIMM_W_X4, 179 .ud_kind = UMC_DIMM_K_RDIMM, 180 .ud_dimmno = 0, 181 .ud_cs = { { 182 .ucs_flags = UMC_CS_F_DECODE_EN, 183 .ucs_base = { 184 .udb_base = 0, 185 .udb_valid = B_TRUE 186 }, 187 .ucs_base_mask = 0x3ffffffff, 188 .ucs_nbanks = 0x5, 189 .ucs_ncol = 0xa, 190 .ucs_nrow_lo = 0x10, 191 .ucs_nbank_groups = 0x3, 192 .ucs_row_low_bit = 0x12, 193 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 194 0xe }, 195 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 196 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 197 .ucs_subchan = 0x6 198 } } 199 } }, 200 } } 201 } } 202 }; 203 204 /* 205 * Next we have a 6 channel variant that uses a 2K based hash. 206 */ 207 static const zen_umc_t zen_umc_nps_6ch_2k = { 208 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 209 .umc_tom2 = 96ULL * 1024ULL * 1024ULL * 1024ULL, 210 .umc_df_rev = DF_REV_4D2, 211 .umc_decomp = { 212 .dfd_sock_mask = 0x01, 213 .dfd_die_mask = 0x00, 214 .dfd_node_mask = 0x20, 215 .dfd_comp_mask = 0x1f, 216 .dfd_sock_shift = 0, 217 .dfd_die_shift = 0, 218 .dfd_node_shift = 5, 219 .dfd_comp_shift = 0 220 }, 221 .umc_ndfs = 1, 222 .umc_dfs = { { 223 .zud_dfno = 0, 224 .zud_dram_nrules = 1, 225 .zud_nchan = 6, 226 .zud_cs_nremap = 0, 227 .zud_hole_base = 0, 228 .zud_rules = { { 229 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 230 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 231 .ddr_base = 0, 232 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL, 233 .ddr_dest_fabid = 0, 234 .ddr_sock_ileave_bits = 0, 235 .ddr_die_ileave_bits = 0, 236 .ddr_addr_start = 8, 237 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 238 } }, 239 .zud_chan = { { 240 .chan_flags = UMC_CHAN_F_ECC_EN, 241 .chan_fabid = 0, 242 .chan_instid = 0, 243 .chan_logid = 0, 244 .chan_nrules = 1, 245 .chan_type = UMC_DIMM_T_DDR5, 246 .chan_rules = { { 247 .ddr_flags = DF_DRAM_F_VALID | 248 DF_DRAM_F_HASH_16_18 | 249 DF_DRAM_F_HASH_21_23 | 250 DF_DRAM_F_HASH_30_32, 251 .ddr_base = 0, 252 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 253 1024ULL, 254 .ddr_dest_fabid = 0, 255 .ddr_sock_ileave_bits = 0, 256 .ddr_die_ileave_bits = 0, 257 .ddr_addr_start = 8, 258 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 259 } }, 260 .chan_dimms = { { 261 .ud_flags = UMC_DIMM_F_VALID, 262 .ud_width = UMC_DIMM_W_X4, 263 .ud_kind = UMC_DIMM_K_RDIMM, 264 .ud_dimmno = 0, 265 .ud_cs = { { 266 .ucs_flags = UMC_CS_F_DECODE_EN, 267 .ucs_base = { 268 .udb_base = 0, 269 .udb_valid = B_TRUE 270 }, 271 .ucs_base_mask = 0x3ffffffff, 272 .ucs_nbanks = 0x5, 273 .ucs_ncol = 0xa, 274 .ucs_nrow_lo = 0x10, 275 .ucs_nbank_groups = 0x3, 276 .ucs_row_low_bit = 0x12, 277 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 278 0xe }, 279 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 280 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 281 .ucs_subchan = 0x6 282 } } 283 } }, 284 }, { 285 .chan_flags = UMC_CHAN_F_ECC_EN, 286 .chan_fabid = 1, 287 .chan_instid = 1, 288 .chan_logid = 1, 289 .chan_nrules = 1, 290 .chan_type = UMC_DIMM_T_DDR5, 291 .chan_rules = { { 292 .ddr_flags = DF_DRAM_F_VALID | 293 DF_DRAM_F_HASH_16_18 | 294 DF_DRAM_F_HASH_21_23 | 295 DF_DRAM_F_HASH_30_32, 296 .ddr_base = 0, 297 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 298 1024ULL, 299 .ddr_dest_fabid = 0, 300 .ddr_sock_ileave_bits = 0, 301 .ddr_die_ileave_bits = 0, 302 .ddr_addr_start = 8, 303 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 304 } }, 305 .chan_dimms = { { 306 .ud_flags = UMC_DIMM_F_VALID, 307 .ud_width = UMC_DIMM_W_X4, 308 .ud_kind = UMC_DIMM_K_RDIMM, 309 .ud_dimmno = 0, 310 .ud_cs = { { 311 .ucs_flags = UMC_CS_F_DECODE_EN, 312 .ucs_base = { 313 .udb_base = 0, 314 .udb_valid = B_TRUE 315 }, 316 .ucs_base_mask = 0x3ffffffff, 317 .ucs_nbanks = 0x5, 318 .ucs_ncol = 0xa, 319 .ucs_nrow_lo = 0x10, 320 .ucs_nbank_groups = 0x3, 321 .ucs_row_low_bit = 0x12, 322 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 323 0xe }, 324 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 325 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 326 .ucs_subchan = 0x6 327 } } 328 } }, 329 }, { 330 .chan_flags = UMC_CHAN_F_ECC_EN, 331 .chan_fabid = 2, 332 .chan_instid = 2, 333 .chan_logid = 2, 334 .chan_nrules = 1, 335 .chan_type = UMC_DIMM_T_DDR5, 336 .chan_rules = { { 337 .ddr_flags = DF_DRAM_F_VALID | 338 DF_DRAM_F_HASH_16_18 | 339 DF_DRAM_F_HASH_21_23 | 340 DF_DRAM_F_HASH_30_32, 341 .ddr_base = 0, 342 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 343 1024ULL, 344 .ddr_dest_fabid = 0, 345 .ddr_sock_ileave_bits = 0, 346 .ddr_die_ileave_bits = 0, 347 .ddr_addr_start = 8, 348 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 349 } }, 350 .chan_dimms = { { 351 .ud_flags = UMC_DIMM_F_VALID, 352 .ud_width = UMC_DIMM_W_X4, 353 .ud_kind = UMC_DIMM_K_RDIMM, 354 .ud_dimmno = 0, 355 .ud_cs = { { 356 .ucs_flags = UMC_CS_F_DECODE_EN, 357 .ucs_base = { 358 .udb_base = 0, 359 .udb_valid = B_TRUE 360 }, 361 .ucs_base_mask = 0x3ffffffff, 362 .ucs_nbanks = 0x5, 363 .ucs_ncol = 0xa, 364 .ucs_nrow_lo = 0x10, 365 .ucs_nbank_groups = 0x3, 366 .ucs_row_low_bit = 0x12, 367 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 368 0xe }, 369 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 370 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 371 .ucs_subchan = 0x6 372 } } 373 } }, 374 }, { 375 .chan_flags = UMC_CHAN_F_ECC_EN, 376 .chan_fabid = 3, 377 .chan_instid = 3, 378 .chan_logid = 3, 379 .chan_nrules = 1, 380 .chan_type = UMC_DIMM_T_DDR5, 381 .chan_rules = { { 382 .ddr_flags = DF_DRAM_F_VALID | 383 DF_DRAM_F_HASH_16_18 | 384 DF_DRAM_F_HASH_21_23 | 385 DF_DRAM_F_HASH_30_32, 386 .ddr_base = 0, 387 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 388 1024ULL, 389 .ddr_dest_fabid = 0, 390 .ddr_sock_ileave_bits = 0, 391 .ddr_die_ileave_bits = 0, 392 .ddr_addr_start = 8, 393 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 394 } }, 395 .chan_dimms = { { 396 .ud_flags = UMC_DIMM_F_VALID, 397 .ud_width = UMC_DIMM_W_X4, 398 .ud_kind = UMC_DIMM_K_RDIMM, 399 .ud_dimmno = 0, 400 .ud_cs = { { 401 .ucs_flags = UMC_CS_F_DECODE_EN, 402 .ucs_base = { 403 .udb_base = 0, 404 .udb_valid = B_TRUE 405 }, 406 .ucs_base_mask = 0x3ffffffff, 407 .ucs_nbanks = 0x5, 408 .ucs_ncol = 0xa, 409 .ucs_nrow_lo = 0x10, 410 .ucs_nbank_groups = 0x3, 411 .ucs_row_low_bit = 0x12, 412 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 413 0xe }, 414 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 415 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 416 .ucs_subchan = 0x6 417 } } 418 } }, 419 }, { 420 .chan_flags = UMC_CHAN_F_ECC_EN, 421 .chan_fabid = 4, 422 .chan_instid = 4, 423 .chan_logid = 4, 424 .chan_nrules = 1, 425 .chan_type = UMC_DIMM_T_DDR5, 426 .chan_rules = { { 427 .ddr_flags = DF_DRAM_F_VALID | 428 DF_DRAM_F_HASH_16_18 | 429 DF_DRAM_F_HASH_21_23 | 430 DF_DRAM_F_HASH_30_32, 431 .ddr_base = 0, 432 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 433 1024ULL, 434 .ddr_dest_fabid = 0, 435 .ddr_sock_ileave_bits = 0, 436 .ddr_die_ileave_bits = 0, 437 .ddr_addr_start = 8, 438 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 439 } }, 440 .chan_dimms = { { 441 .ud_flags = UMC_DIMM_F_VALID, 442 .ud_width = UMC_DIMM_W_X4, 443 .ud_kind = UMC_DIMM_K_RDIMM, 444 .ud_dimmno = 0, 445 .ud_cs = { { 446 .ucs_flags = UMC_CS_F_DECODE_EN, 447 .ucs_base = { 448 .udb_base = 0, 449 .udb_valid = B_TRUE 450 }, 451 .ucs_base_mask = 0x3ffffffff, 452 .ucs_nbanks = 0x5, 453 .ucs_ncol = 0xa, 454 .ucs_nrow_lo = 0x10, 455 .ucs_nbank_groups = 0x3, 456 .ucs_row_low_bit = 0x12, 457 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 458 0xe }, 459 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 460 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 461 .ucs_subchan = 0x6 462 } } 463 } }, 464 }, { 465 .chan_flags = UMC_CHAN_F_ECC_EN, 466 .chan_fabid = 5, 467 .chan_instid = 5, 468 .chan_logid = 5, 469 .chan_nrules = 1, 470 .chan_type = UMC_DIMM_T_DDR5, 471 .chan_rules = { { 472 .ddr_flags = DF_DRAM_F_VALID | 473 DF_DRAM_F_HASH_16_18 | 474 DF_DRAM_F_HASH_21_23 | 475 DF_DRAM_F_HASH_30_32, 476 .ddr_base = 0, 477 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 478 1024ULL, 479 .ddr_dest_fabid = 0, 480 .ddr_sock_ileave_bits = 0, 481 .ddr_die_ileave_bits = 0, 482 .ddr_addr_start = 8, 483 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_6CH_2K 484 } }, 485 .chan_dimms = { { 486 .ud_flags = UMC_DIMM_F_VALID, 487 .ud_width = UMC_DIMM_W_X4, 488 .ud_kind = UMC_DIMM_K_RDIMM, 489 .ud_dimmno = 0, 490 .ud_cs = { { 491 .ucs_flags = UMC_CS_F_DECODE_EN, 492 .ucs_base = { 493 .udb_base = 0, 494 .udb_valid = B_TRUE 495 }, 496 .ucs_base_mask = 0x3ffffffff, 497 .ucs_nbanks = 0x5, 498 .ucs_ncol = 0xa, 499 .ucs_nrow_lo = 0x10, 500 .ucs_nbank_groups = 0x3, 501 .ucs_row_low_bit = 0x12, 502 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 503 0xe }, 504 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 505 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 506 .ucs_subchan = 0x6 507 } } 508 } }, 509 } } 510 } } 511 }; 512 513 /* 514 * 5 Channel hash, 2K 515 */ 516 static const zen_umc_t zen_umc_nps_5ch_2k = { 517 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 518 .umc_tom2 = 80ULL * 1024ULL * 1024ULL * 1024ULL, 519 .umc_df_rev = DF_REV_4D2, 520 .umc_decomp = { 521 .dfd_sock_mask = 0x01, 522 .dfd_die_mask = 0x00, 523 .dfd_node_mask = 0x20, 524 .dfd_comp_mask = 0x1f, 525 .dfd_sock_shift = 0, 526 .dfd_die_shift = 0, 527 .dfd_node_shift = 5, 528 .dfd_comp_shift = 0 529 }, 530 .umc_ndfs = 1, 531 .umc_dfs = { { 532 .zud_dfno = 0, 533 .zud_dram_nrules = 1, 534 .zud_nchan = 5, 535 .zud_cs_nremap = 0, 536 .zud_hole_base = 0, 537 .zud_rules = { { 538 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 539 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 540 .ddr_base = 0, 541 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 1024ULL, 542 .ddr_dest_fabid = 0, 543 .ddr_sock_ileave_bits = 0, 544 .ddr_die_ileave_bits = 0, 545 .ddr_addr_start = 8, 546 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH_2K 547 } }, 548 .zud_chan = { { 549 .chan_flags = UMC_CHAN_F_ECC_EN, 550 .chan_fabid = 0, 551 .chan_instid = 0, 552 .chan_logid = 0, 553 .chan_nrules = 1, 554 .chan_type = UMC_DIMM_T_DDR5, 555 .chan_rules = { { 556 .ddr_flags = DF_DRAM_F_VALID | 557 DF_DRAM_F_HASH_16_18 | 558 DF_DRAM_F_HASH_21_23 | 559 DF_DRAM_F_HASH_30_32, 560 .ddr_base = 0, 561 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 562 1024ULL, 563 .ddr_dest_fabid = 0, 564 .ddr_sock_ileave_bits = 0, 565 .ddr_die_ileave_bits = 0, 566 .ddr_addr_start = 8, 567 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH_2K 568 } }, 569 .chan_dimms = { { 570 .ud_flags = UMC_DIMM_F_VALID, 571 .ud_width = UMC_DIMM_W_X4, 572 .ud_kind = UMC_DIMM_K_RDIMM, 573 .ud_dimmno = 0, 574 .ud_cs = { { 575 .ucs_flags = UMC_CS_F_DECODE_EN, 576 .ucs_base = { 577 .udb_base = 0, 578 .udb_valid = B_TRUE 579 }, 580 .ucs_base_mask = 0x3ffffffff, 581 .ucs_nbanks = 0x5, 582 .ucs_ncol = 0xa, 583 .ucs_nrow_lo = 0x10, 584 .ucs_nbank_groups = 0x3, 585 .ucs_row_low_bit = 0x12, 586 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 587 0xe }, 588 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 589 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 590 .ucs_subchan = 0x6 591 } } 592 } }, 593 }, { 594 .chan_flags = UMC_CHAN_F_ECC_EN, 595 .chan_fabid = 1, 596 .chan_instid = 1, 597 .chan_logid = 1, 598 .chan_nrules = 1, 599 .chan_type = UMC_DIMM_T_DDR5, 600 .chan_rules = { { 601 .ddr_flags = DF_DRAM_F_VALID | 602 DF_DRAM_F_HASH_16_18 | 603 DF_DRAM_F_HASH_21_23 | 604 DF_DRAM_F_HASH_30_32, 605 .ddr_base = 0, 606 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 607 1024ULL, 608 .ddr_dest_fabid = 0, 609 .ddr_sock_ileave_bits = 0, 610 .ddr_die_ileave_bits = 0, 611 .ddr_addr_start = 8, 612 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH_2K 613 } }, 614 .chan_dimms = { { 615 .ud_flags = UMC_DIMM_F_VALID, 616 .ud_width = UMC_DIMM_W_X4, 617 .ud_kind = UMC_DIMM_K_RDIMM, 618 .ud_dimmno = 0, 619 .ud_cs = { { 620 .ucs_flags = UMC_CS_F_DECODE_EN, 621 .ucs_base = { 622 .udb_base = 0, 623 .udb_valid = B_TRUE 624 }, 625 .ucs_base_mask = 0x3ffffffff, 626 .ucs_nbanks = 0x5, 627 .ucs_ncol = 0xa, 628 .ucs_nrow_lo = 0x10, 629 .ucs_nbank_groups = 0x3, 630 .ucs_row_low_bit = 0x12, 631 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 632 0xe }, 633 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 634 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 635 .ucs_subchan = 0x6 636 } } 637 } }, 638 }, { 639 .chan_flags = UMC_CHAN_F_ECC_EN, 640 .chan_fabid = 2, 641 .chan_instid = 2, 642 .chan_logid = 2, 643 .chan_nrules = 1, 644 .chan_type = UMC_DIMM_T_DDR5, 645 .chan_rules = { { 646 .ddr_flags = DF_DRAM_F_VALID | 647 DF_DRAM_F_HASH_16_18 | 648 DF_DRAM_F_HASH_21_23 | 649 DF_DRAM_F_HASH_30_32, 650 .ddr_base = 0, 651 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 652 1024ULL, 653 .ddr_dest_fabid = 0, 654 .ddr_sock_ileave_bits = 0, 655 .ddr_die_ileave_bits = 0, 656 .ddr_addr_start = 8, 657 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH_2K 658 } }, 659 .chan_dimms = { { 660 .ud_flags = UMC_DIMM_F_VALID, 661 .ud_width = UMC_DIMM_W_X4, 662 .ud_kind = UMC_DIMM_K_RDIMM, 663 .ud_dimmno = 0, 664 .ud_cs = { { 665 .ucs_flags = UMC_CS_F_DECODE_EN, 666 .ucs_base = { 667 .udb_base = 0, 668 .udb_valid = B_TRUE 669 }, 670 .ucs_base_mask = 0x3ffffffff, 671 .ucs_nbanks = 0x5, 672 .ucs_ncol = 0xa, 673 .ucs_nrow_lo = 0x10, 674 .ucs_nbank_groups = 0x3, 675 .ucs_row_low_bit = 0x12, 676 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 677 0xe }, 678 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 679 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 680 .ucs_subchan = 0x6 681 } } 682 } }, 683 }, { 684 .chan_flags = UMC_CHAN_F_ECC_EN, 685 .chan_fabid = 3, 686 .chan_instid = 3, 687 .chan_logid = 3, 688 .chan_nrules = 1, 689 .chan_type = UMC_DIMM_T_DDR5, 690 .chan_rules = { { 691 .ddr_flags = DF_DRAM_F_VALID | 692 DF_DRAM_F_HASH_16_18 | 693 DF_DRAM_F_HASH_21_23 | 694 DF_DRAM_F_HASH_30_32, 695 .ddr_base = 0, 696 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 697 1024ULL, 698 .ddr_dest_fabid = 0, 699 .ddr_sock_ileave_bits = 0, 700 .ddr_die_ileave_bits = 0, 701 .ddr_addr_start = 8, 702 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH_2K 703 } }, 704 .chan_dimms = { { 705 .ud_flags = UMC_DIMM_F_VALID, 706 .ud_width = UMC_DIMM_W_X4, 707 .ud_kind = UMC_DIMM_K_RDIMM, 708 .ud_dimmno = 0, 709 .ud_cs = { { 710 .ucs_flags = UMC_CS_F_DECODE_EN, 711 .ucs_base = { 712 .udb_base = 0, 713 .udb_valid = B_TRUE 714 }, 715 .ucs_base_mask = 0x3ffffffff, 716 .ucs_nbanks = 0x5, 717 .ucs_ncol = 0xa, 718 .ucs_nrow_lo = 0x10, 719 .ucs_nbank_groups = 0x3, 720 .ucs_row_low_bit = 0x12, 721 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 722 0xe }, 723 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 724 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 725 .ucs_subchan = 0x6 726 } } 727 } }, 728 }, { 729 .chan_flags = UMC_CHAN_F_ECC_EN, 730 .chan_fabid = 4, 731 .chan_instid = 4, 732 .chan_logid = 4, 733 .chan_nrules = 1, 734 .chan_type = UMC_DIMM_T_DDR5, 735 .chan_rules = { { 736 .ddr_flags = DF_DRAM_F_VALID | 737 DF_DRAM_F_HASH_16_18 | 738 DF_DRAM_F_HASH_21_23 | 739 DF_DRAM_F_HASH_30_32, 740 .ddr_base = 0, 741 .ddr_limit = 80ULL * 1024ULL * 1024ULL * 742 1024ULL, 743 .ddr_dest_fabid = 0, 744 .ddr_sock_ileave_bits = 0, 745 .ddr_die_ileave_bits = 0, 746 .ddr_addr_start = 8, 747 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH_2K 748 } }, 749 .chan_dimms = { { 750 .ud_flags = UMC_DIMM_F_VALID, 751 .ud_width = UMC_DIMM_W_X4, 752 .ud_kind = UMC_DIMM_K_RDIMM, 753 .ud_dimmno = 0, 754 .ud_cs = { { 755 .ucs_flags = UMC_CS_F_DECODE_EN, 756 .ucs_base = { 757 .udb_base = 0, 758 .udb_valid = B_TRUE 759 }, 760 .ucs_base_mask = 0x3ffffffff, 761 .ucs_nbanks = 0x5, 762 .ucs_ncol = 0xa, 763 .ucs_nrow_lo = 0x10, 764 .ucs_nbank_groups = 0x3, 765 .ucs_row_low_bit = 0x12, 766 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 767 0xe }, 768 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 769 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 770 .ucs_subchan = 0x6 771 } } 772 } }, 773 } } 774 } } 775 }; 776 777 static const zen_umc_t zen_umc_nps_10ch_1k = { 778 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 779 .umc_tom2 = 160ULL * 1024ULL * 1024ULL * 1024ULL, 780 .umc_df_rev = DF_REV_4D2, 781 .umc_decomp = { 782 .dfd_sock_mask = 0x01, 783 .dfd_die_mask = 0x00, 784 .dfd_node_mask = 0x20, 785 .dfd_comp_mask = 0x1f, 786 .dfd_sock_shift = 0, 787 .dfd_die_shift = 0, 788 .dfd_node_shift = 5, 789 .dfd_comp_shift = 0 790 }, 791 .umc_ndfs = 1, 792 .umc_dfs = { { 793 .zud_dfno = 0, 794 .zud_dram_nrules = 1, 795 .zud_nchan = 10, 796 .zud_cs_nremap = 0, 797 .zud_hole_base = 0, 798 .zud_rules = { { 799 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 800 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 801 .ddr_base = 0, 802 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1024ULL, 803 .ddr_dest_fabid = 0, 804 .ddr_sock_ileave_bits = 0, 805 .ddr_die_ileave_bits = 0, 806 .ddr_addr_start = 8, 807 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 808 } }, 809 .zud_chan = { { 810 .chan_flags = UMC_CHAN_F_ECC_EN, 811 .chan_fabid = 0, 812 .chan_instid = 0, 813 .chan_logid = 0, 814 .chan_nrules = 1, 815 .chan_type = UMC_DIMM_T_DDR5, 816 .chan_rules = { { 817 .ddr_flags = DF_DRAM_F_VALID | 818 DF_DRAM_F_HASH_16_18 | 819 DF_DRAM_F_HASH_21_23 | 820 DF_DRAM_F_HASH_30_32, 821 .ddr_base = 0, 822 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 823 1024ULL, 824 .ddr_dest_fabid = 0, 825 .ddr_sock_ileave_bits = 0, 826 .ddr_die_ileave_bits = 0, 827 .ddr_addr_start = 8, 828 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 829 } }, 830 .chan_dimms = { { 831 .ud_flags = UMC_DIMM_F_VALID, 832 .ud_width = UMC_DIMM_W_X4, 833 .ud_kind = UMC_DIMM_K_RDIMM, 834 .ud_dimmno = 0, 835 .ud_cs = { { 836 .ucs_flags = UMC_CS_F_DECODE_EN, 837 .ucs_base = { 838 .udb_base = 0, 839 .udb_valid = B_TRUE 840 }, 841 .ucs_base_mask = 0x3ffffffff, 842 .ucs_nbanks = 0x5, 843 .ucs_ncol = 0xa, 844 .ucs_nrow_lo = 0x10, 845 .ucs_nbank_groups = 0x3, 846 .ucs_row_low_bit = 0x12, 847 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 848 0xe }, 849 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 850 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 851 .ucs_subchan = 0x6 852 } } 853 } }, 854 }, { 855 .chan_flags = UMC_CHAN_F_ECC_EN, 856 .chan_fabid = 1, 857 .chan_instid = 1, 858 .chan_logid = 1, 859 .chan_nrules = 1, 860 .chan_type = UMC_DIMM_T_DDR5, 861 .chan_rules = { { 862 .ddr_flags = DF_DRAM_F_VALID | 863 DF_DRAM_F_HASH_16_18 | 864 DF_DRAM_F_HASH_21_23 | 865 DF_DRAM_F_HASH_30_32, 866 .ddr_base = 0, 867 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 868 1024ULL, 869 .ddr_dest_fabid = 0, 870 .ddr_sock_ileave_bits = 0, 871 .ddr_die_ileave_bits = 0, 872 .ddr_addr_start = 8, 873 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 874 } }, 875 .chan_dimms = { { 876 .ud_flags = UMC_DIMM_F_VALID, 877 .ud_width = UMC_DIMM_W_X4, 878 .ud_kind = UMC_DIMM_K_RDIMM, 879 .ud_dimmno = 0, 880 .ud_cs = { { 881 .ucs_flags = UMC_CS_F_DECODE_EN, 882 .ucs_base = { 883 .udb_base = 0, 884 .udb_valid = B_TRUE 885 }, 886 .ucs_base_mask = 0x3ffffffff, 887 .ucs_nbanks = 0x5, 888 .ucs_ncol = 0xa, 889 .ucs_nrow_lo = 0x10, 890 .ucs_nbank_groups = 0x3, 891 .ucs_row_low_bit = 0x12, 892 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 893 0xe }, 894 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 895 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 896 .ucs_subchan = 0x6 897 } } 898 } }, 899 }, { 900 .chan_flags = UMC_CHAN_F_ECC_EN, 901 .chan_fabid = 2, 902 .chan_instid = 2, 903 .chan_logid = 2, 904 .chan_nrules = 1, 905 .chan_type = UMC_DIMM_T_DDR5, 906 .chan_rules = { { 907 .ddr_flags = DF_DRAM_F_VALID | 908 DF_DRAM_F_HASH_16_18 | 909 DF_DRAM_F_HASH_21_23 | 910 DF_DRAM_F_HASH_30_32, 911 .ddr_base = 0, 912 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 913 1024ULL, 914 .ddr_dest_fabid = 0, 915 .ddr_sock_ileave_bits = 0, 916 .ddr_die_ileave_bits = 0, 917 .ddr_addr_start = 8, 918 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 919 } }, 920 .chan_dimms = { { 921 .ud_flags = UMC_DIMM_F_VALID, 922 .ud_width = UMC_DIMM_W_X4, 923 .ud_kind = UMC_DIMM_K_RDIMM, 924 .ud_dimmno = 0, 925 .ud_cs = { { 926 .ucs_flags = UMC_CS_F_DECODE_EN, 927 .ucs_base = { 928 .udb_base = 0, 929 .udb_valid = B_TRUE 930 }, 931 .ucs_base_mask = 0x3ffffffff, 932 .ucs_nbanks = 0x5, 933 .ucs_ncol = 0xa, 934 .ucs_nrow_lo = 0x10, 935 .ucs_nbank_groups = 0x3, 936 .ucs_row_low_bit = 0x12, 937 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 938 0xe }, 939 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 940 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 941 .ucs_subchan = 0x6 942 } } 943 } }, 944 }, { 945 .chan_flags = UMC_CHAN_F_ECC_EN, 946 .chan_fabid = 3, 947 .chan_instid = 3, 948 .chan_logid = 3, 949 .chan_nrules = 1, 950 .chan_type = UMC_DIMM_T_DDR5, 951 .chan_rules = { { 952 .ddr_flags = DF_DRAM_F_VALID | 953 DF_DRAM_F_HASH_16_18 | 954 DF_DRAM_F_HASH_21_23 | 955 DF_DRAM_F_HASH_30_32, 956 .ddr_base = 0, 957 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 958 1024ULL, 959 .ddr_dest_fabid = 0, 960 .ddr_sock_ileave_bits = 0, 961 .ddr_die_ileave_bits = 0, 962 .ddr_addr_start = 8, 963 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 964 } }, 965 .chan_dimms = { { 966 .ud_flags = UMC_DIMM_F_VALID, 967 .ud_width = UMC_DIMM_W_X4, 968 .ud_kind = UMC_DIMM_K_RDIMM, 969 .ud_dimmno = 0, 970 .ud_cs = { { 971 .ucs_flags = UMC_CS_F_DECODE_EN, 972 .ucs_base = { 973 .udb_base = 0, 974 .udb_valid = B_TRUE 975 }, 976 .ucs_base_mask = 0x3ffffffff, 977 .ucs_nbanks = 0x5, 978 .ucs_ncol = 0xa, 979 .ucs_nrow_lo = 0x10, 980 .ucs_nbank_groups = 0x3, 981 .ucs_row_low_bit = 0x12, 982 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 983 0xe }, 984 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 985 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 986 .ucs_subchan = 0x6 987 } } 988 } }, 989 }, { 990 .chan_flags = UMC_CHAN_F_ECC_EN, 991 .chan_fabid = 4, 992 .chan_instid = 4, 993 .chan_logid = 4, 994 .chan_nrules = 1, 995 .chan_type = UMC_DIMM_T_DDR5, 996 .chan_rules = { { 997 .ddr_flags = DF_DRAM_F_VALID | 998 DF_DRAM_F_HASH_16_18 | 999 DF_DRAM_F_HASH_21_23 | 1000 DF_DRAM_F_HASH_30_32, 1001 .ddr_base = 0, 1002 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1003 1024ULL, 1004 .ddr_dest_fabid = 0, 1005 .ddr_sock_ileave_bits = 0, 1006 .ddr_die_ileave_bits = 0, 1007 .ddr_addr_start = 8, 1008 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 1009 } }, 1010 .chan_dimms = { { 1011 .ud_flags = UMC_DIMM_F_VALID, 1012 .ud_width = UMC_DIMM_W_X4, 1013 .ud_kind = UMC_DIMM_K_RDIMM, 1014 .ud_dimmno = 0, 1015 .ud_cs = { { 1016 .ucs_flags = UMC_CS_F_DECODE_EN, 1017 .ucs_base = { 1018 .udb_base = 0, 1019 .udb_valid = B_TRUE 1020 }, 1021 .ucs_base_mask = 0x3ffffffff, 1022 .ucs_nbanks = 0x5, 1023 .ucs_ncol = 0xa, 1024 .ucs_nrow_lo = 0x10, 1025 .ucs_nbank_groups = 0x3, 1026 .ucs_row_low_bit = 0x12, 1027 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1028 0xe }, 1029 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1030 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1031 .ucs_subchan = 0x6 1032 } } 1033 } }, 1034 }, { 1035 .chan_flags = UMC_CHAN_F_ECC_EN, 1036 .chan_fabid = 5, 1037 .chan_instid = 5, 1038 .chan_logid = 5, 1039 .chan_nrules = 1, 1040 .chan_type = UMC_DIMM_T_DDR5, 1041 .chan_rules = { { 1042 .ddr_flags = DF_DRAM_F_VALID | 1043 DF_DRAM_F_HASH_16_18 | 1044 DF_DRAM_F_HASH_21_23 | 1045 DF_DRAM_F_HASH_30_32, 1046 .ddr_base = 0, 1047 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1048 1024ULL, 1049 .ddr_dest_fabid = 0, 1050 .ddr_sock_ileave_bits = 0, 1051 .ddr_die_ileave_bits = 0, 1052 .ddr_addr_start = 8, 1053 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 1054 } }, 1055 .chan_dimms = { { 1056 .ud_flags = UMC_DIMM_F_VALID, 1057 .ud_width = UMC_DIMM_W_X4, 1058 .ud_kind = UMC_DIMM_K_RDIMM, 1059 .ud_dimmno = 0, 1060 .ud_cs = { { 1061 .ucs_flags = UMC_CS_F_DECODE_EN, 1062 .ucs_base = { 1063 .udb_base = 0, 1064 .udb_valid = B_TRUE 1065 }, 1066 .ucs_base_mask = 0x3ffffffff, 1067 .ucs_nbanks = 0x5, 1068 .ucs_ncol = 0xa, 1069 .ucs_nrow_lo = 0x10, 1070 .ucs_nbank_groups = 0x3, 1071 .ucs_row_low_bit = 0x12, 1072 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1073 0xe }, 1074 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1075 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1076 .ucs_subchan = 0x6 1077 } } 1078 } }, 1079 }, { 1080 .chan_flags = UMC_CHAN_F_ECC_EN, 1081 .chan_fabid = 6, 1082 .chan_instid = 6, 1083 .chan_logid = 6, 1084 .chan_nrules = 1, 1085 .chan_type = UMC_DIMM_T_DDR5, 1086 .chan_rules = { { 1087 .ddr_flags = DF_DRAM_F_VALID | 1088 DF_DRAM_F_HASH_16_18 | 1089 DF_DRAM_F_HASH_21_23 | 1090 DF_DRAM_F_HASH_30_32, 1091 .ddr_base = 0, 1092 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1093 1024ULL, 1094 .ddr_dest_fabid = 0, 1095 .ddr_sock_ileave_bits = 0, 1096 .ddr_die_ileave_bits = 0, 1097 .ddr_addr_start = 8, 1098 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 1099 } }, 1100 .chan_dimms = { { 1101 .ud_flags = UMC_DIMM_F_VALID, 1102 .ud_width = UMC_DIMM_W_X4, 1103 .ud_kind = UMC_DIMM_K_RDIMM, 1104 .ud_dimmno = 0, 1105 .ud_cs = { { 1106 .ucs_flags = UMC_CS_F_DECODE_EN, 1107 .ucs_base = { 1108 .udb_base = 0, 1109 .udb_valid = B_TRUE 1110 }, 1111 .ucs_base_mask = 0x3ffffffff, 1112 .ucs_nbanks = 0x5, 1113 .ucs_ncol = 0xa, 1114 .ucs_nrow_lo = 0x10, 1115 .ucs_nbank_groups = 0x3, 1116 .ucs_row_low_bit = 0x12, 1117 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1118 0xe }, 1119 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1120 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1121 .ucs_subchan = 0x6 1122 } } 1123 } }, 1124 }, { 1125 .chan_flags = UMC_CHAN_F_ECC_EN, 1126 .chan_fabid = 7, 1127 .chan_instid = 7, 1128 .chan_logid = 7, 1129 .chan_nrules = 1, 1130 .chan_type = UMC_DIMM_T_DDR5, 1131 .chan_rules = { { 1132 .ddr_flags = DF_DRAM_F_VALID | 1133 DF_DRAM_F_HASH_16_18 | 1134 DF_DRAM_F_HASH_21_23 | 1135 DF_DRAM_F_HASH_30_32, 1136 .ddr_base = 0, 1137 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1138 1024ULL, 1139 .ddr_dest_fabid = 0, 1140 .ddr_sock_ileave_bits = 0, 1141 .ddr_die_ileave_bits = 0, 1142 .ddr_addr_start = 8, 1143 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 1144 } }, 1145 .chan_dimms = { { 1146 .ud_flags = UMC_DIMM_F_VALID, 1147 .ud_width = UMC_DIMM_W_X4, 1148 .ud_kind = UMC_DIMM_K_RDIMM, 1149 .ud_dimmno = 0, 1150 .ud_cs = { { 1151 .ucs_flags = UMC_CS_F_DECODE_EN, 1152 .ucs_base = { 1153 .udb_base = 0, 1154 .udb_valid = B_TRUE 1155 }, 1156 .ucs_base_mask = 0x3ffffffff, 1157 .ucs_nbanks = 0x5, 1158 .ucs_ncol = 0xa, 1159 .ucs_nrow_lo = 0x10, 1160 .ucs_nbank_groups = 0x3, 1161 .ucs_row_low_bit = 0x12, 1162 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1163 0xe }, 1164 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1165 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1166 .ucs_subchan = 0x6 1167 } } 1168 } }, 1169 }, { 1170 .chan_flags = UMC_CHAN_F_ECC_EN, 1171 .chan_fabid = 8, 1172 .chan_instid = 8, 1173 .chan_logid = 8, 1174 .chan_nrules = 1, 1175 .chan_type = UMC_DIMM_T_DDR5, 1176 .chan_rules = { { 1177 .ddr_flags = DF_DRAM_F_VALID | 1178 DF_DRAM_F_HASH_16_18 | 1179 DF_DRAM_F_HASH_21_23 | 1180 DF_DRAM_F_HASH_30_32, 1181 .ddr_base = 0, 1182 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1183 1024ULL, 1184 .ddr_dest_fabid = 0, 1185 .ddr_sock_ileave_bits = 0, 1186 .ddr_die_ileave_bits = 0, 1187 .ddr_addr_start = 8, 1188 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 1189 } }, 1190 .chan_dimms = { { 1191 .ud_flags = UMC_DIMM_F_VALID, 1192 .ud_width = UMC_DIMM_W_X4, 1193 .ud_kind = UMC_DIMM_K_RDIMM, 1194 .ud_dimmno = 0, 1195 .ud_cs = { { 1196 .ucs_flags = UMC_CS_F_DECODE_EN, 1197 .ucs_base = { 1198 .udb_base = 0, 1199 .udb_valid = B_TRUE 1200 }, 1201 .ucs_base_mask = 0x3ffffffff, 1202 .ucs_nbanks = 0x5, 1203 .ucs_ncol = 0xa, 1204 .ucs_nrow_lo = 0x10, 1205 .ucs_nbank_groups = 0x3, 1206 .ucs_row_low_bit = 0x12, 1207 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1208 0xe }, 1209 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1210 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1211 .ucs_subchan = 0x6 1212 } } 1213 } }, 1214 }, { 1215 .chan_flags = UMC_CHAN_F_ECC_EN, 1216 .chan_fabid = 9, 1217 .chan_instid = 9, 1218 .chan_logid = 9, 1219 .chan_nrules = 1, 1220 .chan_type = UMC_DIMM_T_DDR5, 1221 .chan_rules = { { 1222 .ddr_flags = DF_DRAM_F_VALID | 1223 DF_DRAM_F_HASH_16_18 | 1224 DF_DRAM_F_HASH_21_23 | 1225 DF_DRAM_F_HASH_30_32, 1226 .ddr_base = 0, 1227 .ddr_limit = 160ULL * 1024ULL * 1024ULL * 1228 1024ULL, 1229 .ddr_dest_fabid = 0, 1230 .ddr_sock_ileave_bits = 0, 1231 .ddr_die_ileave_bits = 0, 1232 .ddr_addr_start = 8, 1233 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS1_10CH_1K 1234 } }, 1235 .chan_dimms = { { 1236 .ud_flags = UMC_DIMM_F_VALID, 1237 .ud_width = UMC_DIMM_W_X4, 1238 .ud_kind = UMC_DIMM_K_RDIMM, 1239 .ud_dimmno = 0, 1240 .ud_cs = { { 1241 .ucs_flags = UMC_CS_F_DECODE_EN, 1242 .ucs_base = { 1243 .udb_base = 0, 1244 .udb_valid = B_TRUE 1245 }, 1246 .ucs_base_mask = 0x3ffffffff, 1247 .ucs_nbanks = 0x5, 1248 .ucs_ncol = 0xa, 1249 .ucs_nrow_lo = 0x10, 1250 .ucs_nbank_groups = 0x3, 1251 .ucs_row_low_bit = 0x12, 1252 .ucs_bank_bits = { 0xf, 0x10, 0x11, 0xd, 1253 0xe }, 1254 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 1255 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 1256 .ucs_subchan = 0x6 1257 } } 1258 } }, 1259 } } 1260 } } 1261 }; 1262 1263 const umc_decode_test_t zen_umc_test_np2_k[] = { { 1264 .udt_desc = "DF 4D2 NPS 1K 3ch (0)", 1265 .udt_umc = &zen_umc_nps_3ch_1k, 1266 .udt_pa = 0x95, 1267 .udt_pass = B_TRUE, 1268 .udt_norm_addr = 0x95, 1269 .udt_sock = 0, 1270 .udt_die = 0, 1271 .udt_comp = 0, 1272 .udt_dimm_no = 0, 1273 .udt_dimm_col = 0x15, 1274 .udt_dimm_row = 0x0, 1275 .udt_dimm_bank = 0x0, 1276 .udt_dimm_bank_group = 0x0, 1277 .udt_dimm_subchan = 0x0, 1278 .udt_dimm_rm = 0, 1279 .udt_dimm_cs = 0 1280 }, { 1281 .udt_desc = "DF 4D2 NPS 1K 3ch (1)", 1282 .udt_umc = &zen_umc_nps_3ch_1k, 1283 .udt_pa = 0x195, 1284 .udt_pass = B_TRUE, 1285 .udt_norm_addr = 0x95, 1286 .udt_sock = 0, 1287 .udt_die = 0, 1288 .udt_comp = 1, 1289 .udt_dimm_no = 0, 1290 .udt_dimm_col = 0x15, 1291 .udt_dimm_row = 0x0, 1292 .udt_dimm_bank = 0x0, 1293 .udt_dimm_bank_group = 0x0, 1294 .udt_dimm_subchan = 0x0, 1295 .udt_dimm_rm = 0, 1296 .udt_dimm_cs = 0 1297 }, { 1298 .udt_desc = "DF 4D2 NPS 1K 3ch (2)", 1299 .udt_umc = &zen_umc_nps_3ch_1k, 1300 .udt_pa = 0x295, 1301 .udt_pass = B_TRUE, 1302 .udt_norm_addr = 0x95, 1303 .udt_sock = 0, 1304 .udt_die = 0, 1305 .udt_comp = 2, 1306 .udt_dimm_no = 0, 1307 .udt_dimm_col = 0x15, 1308 .udt_dimm_row = 0x0, 1309 .udt_dimm_bank = 0x0, 1310 .udt_dimm_bank_group = 0x0, 1311 .udt_dimm_subchan = 0x0, 1312 .udt_dimm_rm = 0, 1313 .udt_dimm_cs = 0 1314 }, { 1315 .udt_desc = "DF 4D2 NPS 1K 3ch (3)", 1316 .udt_umc = &zen_umc_nps_3ch_1k, 1317 .udt_pa = 0xc95, 1318 .udt_pass = B_TRUE, 1319 .udt_norm_addr = 0x395, 1320 .udt_sock = 0, 1321 .udt_die = 0, 1322 .udt_comp = 0, 1323 .udt_dimm_no = 0, 1324 .udt_dimm_col = 0x75, 1325 .udt_dimm_row = 0x0, 1326 .udt_dimm_bank = 0x0, 1327 .udt_dimm_bank_group = 0x0, 1328 .udt_dimm_subchan = 0x0, 1329 .udt_dimm_rm = 0, 1330 .udt_dimm_cs = 0 1331 }, { 1332 .udt_desc = "DF 4D2 NPS 1K 3ch (4)", 1333 .udt_umc = &zen_umc_nps_3ch_1k, 1334 .udt_pa = 0xd95, 1335 .udt_pass = B_TRUE, 1336 .udt_norm_addr = 0x395, 1337 .udt_sock = 0, 1338 .udt_die = 0, 1339 .udt_comp = 1, 1340 .udt_dimm_no = 0, 1341 .udt_dimm_col = 0x75, 1342 .udt_dimm_row = 0x0, 1343 .udt_dimm_bank = 0x0, 1344 .udt_dimm_bank_group = 0x0, 1345 .udt_dimm_subchan = 0x0, 1346 .udt_dimm_rm = 0, 1347 .udt_dimm_cs = 0 1348 }, { 1349 .udt_desc = "DF 4D2 NPS 1K 3ch (5)", 1350 .udt_umc = &zen_umc_nps_3ch_1k, 1351 .udt_pa = 0xe95, 1352 .udt_pass = B_TRUE, 1353 .udt_norm_addr = 0x395, 1354 .udt_sock = 0, 1355 .udt_die = 0, 1356 .udt_comp = 2, 1357 .udt_dimm_no = 0, 1358 .udt_dimm_col = 0x75, 1359 .udt_dimm_row = 0x0, 1360 .udt_dimm_bank = 0x0, 1361 .udt_dimm_bank_group = 0x0, 1362 .udt_dimm_subchan = 0x0, 1363 .udt_dimm_rm = 0, 1364 .udt_dimm_cs = 0 1365 }, { 1366 .udt_desc = "DF 4D2 NPS 1K 3ch (6)", 1367 .udt_umc = &zen_umc_nps_3ch_1k, 1368 .udt_pa = 0xf95, 1369 .udt_pass = B_TRUE, 1370 .udt_norm_addr = 0x795, 1371 .udt_sock = 0, 1372 .udt_die = 0, 1373 .udt_comp = 0, 1374 .udt_dimm_no = 0, 1375 .udt_dimm_col = 0xf5, 1376 .udt_dimm_row = 0x0, 1377 .udt_dimm_bank = 0x0, 1378 .udt_dimm_bank_group = 0x0, 1379 .udt_dimm_subchan = 0x0, 1380 .udt_dimm_rm = 0, 1381 .udt_dimm_cs = 0 1382 }, { 1383 .udt_desc = "DF 4D2 NPS 1K 3ch (7)", 1384 .udt_umc = &zen_umc_nps_3ch_1k, 1385 .udt_pa = 0x1c95, 1386 .udt_pass = B_TRUE, 1387 .udt_norm_addr = 0x795, 1388 .udt_sock = 0, 1389 .udt_die = 0, 1390 .udt_comp = 1, 1391 .udt_dimm_no = 0, 1392 .udt_dimm_col = 0xf5, 1393 .udt_dimm_row = 0x0, 1394 .udt_dimm_bank = 0x0, 1395 .udt_dimm_bank_group = 0x0, 1396 .udt_dimm_subchan = 0x0, 1397 .udt_dimm_rm = 0, 1398 .udt_dimm_cs = 0 1399 }, { 1400 .udt_desc = "DF 4D2 NPS 1K 3ch (8)", 1401 .udt_umc = &zen_umc_nps_3ch_1k, 1402 .udt_pa = 0x1d95, 1403 .udt_pass = B_TRUE, 1404 .udt_norm_addr = 0x795, 1405 .udt_sock = 0, 1406 .udt_die = 0, 1407 .udt_comp = 2, 1408 .udt_dimm_no = 0, 1409 .udt_dimm_col = 0xf5, 1410 .udt_dimm_row = 0x0, 1411 .udt_dimm_bank = 0x0, 1412 .udt_dimm_bank_group = 0x0, 1413 .udt_dimm_subchan = 0x0, 1414 .udt_dimm_rm = 0, 1415 .udt_dimm_cs = 0 1416 }, { 1417 .udt_desc = "DF 4D2 NPS 1K 3ch (9)", 1418 .udt_umc = &zen_umc_nps_3ch_1k, 1419 .udt_pa = 0x2032f0695, 1420 .udt_pass = B_TRUE, 1421 .udt_norm_addr = 0xabba5995, 1422 .udt_sock = 0, 1423 .udt_die = 0, 1424 .udt_comp = 0, 1425 .udt_dimm_no = 0, 1426 .udt_dimm_col = 0x335, 1427 .udt_dimm_row = 0x2aee, 1428 .udt_dimm_bank = 0x2, 1429 .udt_dimm_bank_group = 0x4, 1430 .udt_dimm_subchan = 0x0, 1431 .udt_dimm_rm = 0, 1432 .udt_dimm_cs = 0 1433 }, { 1434 .udt_desc = "DF 4D2 NPS 1K 3ch (10)", 1435 .udt_umc = &zen_umc_nps_3ch_1k, 1436 .udt_pa = 0x2032f0795, 1437 .udt_pass = B_TRUE, 1438 .udt_norm_addr = 0xabba5995, 1439 .udt_sock = 0, 1440 .udt_die = 0, 1441 .udt_comp = 1, 1442 .udt_dimm_no = 0, 1443 .udt_dimm_col = 0x335, 1444 .udt_dimm_row = 0x2aee, 1445 .udt_dimm_bank = 0x2, 1446 .udt_dimm_bank_group = 0x4, 1447 .udt_dimm_subchan = 0x0, 1448 .udt_dimm_rm = 0, 1449 .udt_dimm_cs = 0 1450 }, { 1451 .udt_desc = "DF 4D2 NPS 1K 3ch (11)", 1452 .udt_umc = &zen_umc_nps_3ch_1k, 1453 .udt_pa = 0x2032f1495, 1454 .udt_pass = B_TRUE, 1455 .udt_norm_addr = 0xabba5995, 1456 .udt_sock = 0, 1457 .udt_die = 0, 1458 .udt_comp = 2, 1459 .udt_dimm_no = 0, 1460 .udt_dimm_col = 0x335, 1461 .udt_dimm_row = 0x2aee, 1462 .udt_dimm_bank = 0x2, 1463 .udt_dimm_bank_group = 0x4, 1464 .udt_dimm_subchan = 0x0, 1465 .udt_dimm_rm = 0, 1466 .udt_dimm_cs = 0 1467 }, { 1468 .udt_desc = "DF 4D2 NPS 2K 6ch (0)", 1469 .udt_umc = &zen_umc_nps_6ch_2k, 1470 .udt_pa = 0x2b, 1471 .udt_pass = B_TRUE, 1472 .udt_norm_addr = 0x2b, 1473 .udt_sock = 0, 1474 .udt_die = 0, 1475 .udt_comp = 0, 1476 .udt_dimm_no = 0, 1477 .udt_dimm_col = 0xa, 1478 .udt_dimm_row = 0, 1479 .udt_dimm_bank = 0, 1480 .udt_dimm_bank_group = 0, 1481 .udt_dimm_subchan = 0, 1482 .udt_dimm_rm = 0, 1483 .udt_dimm_cs = 0 1484 }, { 1485 .udt_desc = "DF 4D2 NPS 2K 6ch (1)", 1486 .udt_umc = &zen_umc_nps_6ch_2k, 1487 .udt_pa = 0x12b, 1488 .udt_pass = B_TRUE, 1489 .udt_norm_addr = 0x2b, 1490 .udt_sock = 0, 1491 .udt_die = 0, 1492 .udt_comp = 1, 1493 .udt_dimm_no = 0, 1494 .udt_dimm_col = 0xa, 1495 .udt_dimm_row = 0, 1496 .udt_dimm_bank = 0, 1497 .udt_dimm_bank_group = 0, 1498 .udt_dimm_subchan = 0, 1499 .udt_dimm_rm = 0, 1500 .udt_dimm_cs = 0 1501 }, { 1502 .udt_desc = "DF 4D2 NPS 2K 6ch (2)", 1503 .udt_umc = &zen_umc_nps_6ch_2k, 1504 .udt_pa = 0x102b, 1505 .udt_pass = B_TRUE, 1506 .udt_norm_addr = 0x2b, 1507 .udt_sock = 0, 1508 .udt_die = 0, 1509 .udt_comp = 2, 1510 .udt_dimm_no = 0, 1511 .udt_dimm_col = 0xa, 1512 .udt_dimm_row = 0, 1513 .udt_dimm_bank = 0, 1514 .udt_dimm_bank_group = 0, 1515 .udt_dimm_subchan = 0, 1516 .udt_dimm_rm = 0, 1517 .udt_dimm_cs = 0 1518 }, { 1519 .udt_desc = "DF 4D2 NPS 2K 6ch (3)", 1520 .udt_umc = &zen_umc_nps_6ch_2k, 1521 .udt_pa = 0x112b, 1522 .udt_pass = B_TRUE, 1523 .udt_norm_addr = 0x2b, 1524 .udt_sock = 0, 1525 .udt_die = 0, 1526 .udt_comp = 3, 1527 .udt_dimm_no = 0, 1528 .udt_dimm_col = 0xa, 1529 .udt_dimm_row = 0, 1530 .udt_dimm_bank = 0, 1531 .udt_dimm_bank_group = 0, 1532 .udt_dimm_subchan = 0, 1533 .udt_dimm_rm = 0, 1534 .udt_dimm_cs = 0 1535 }, { 1536 .udt_desc = "DF 4D2 NPS 2K 6ch (4)", 1537 .udt_umc = &zen_umc_nps_6ch_2k, 1538 .udt_pa = 0x202b, 1539 .udt_pass = B_TRUE, 1540 .udt_norm_addr = 0x2b, 1541 .udt_sock = 0, 1542 .udt_die = 0, 1543 .udt_comp = 4, 1544 .udt_dimm_no = 0, 1545 .udt_dimm_col = 0xa, 1546 .udt_dimm_row = 0, 1547 .udt_dimm_bank = 0, 1548 .udt_dimm_bank_group = 0, 1549 .udt_dimm_subchan = 0, 1550 .udt_dimm_rm = 0, 1551 .udt_dimm_cs = 0 1552 }, { 1553 .udt_desc = "DF 4D2 NPS 2K 6ch (5)", 1554 .udt_umc = &zen_umc_nps_6ch_2k, 1555 .udt_pa = 0x212b, 1556 .udt_pass = B_TRUE, 1557 .udt_norm_addr = 0x2b, 1558 .udt_sock = 0, 1559 .udt_die = 0, 1560 .udt_comp = 5, 1561 .udt_dimm_no = 0, 1562 .udt_dimm_col = 0xa, 1563 .udt_dimm_row = 0, 1564 .udt_dimm_bank = 0, 1565 .udt_dimm_bank_group = 0, 1566 .udt_dimm_subchan = 0, 1567 .udt_dimm_rm = 0, 1568 .udt_dimm_cs = 0 1569 }, { 1570 .udt_desc = "DF 4D2 NPS 2K 6ch (0)", 1571 .udt_umc = &zen_umc_nps_6ch_2k, 1572 .udt_pa = 0x2b, 1573 .udt_pass = B_TRUE, 1574 .udt_norm_addr = 0x2b, 1575 .udt_sock = 0, 1576 .udt_die = 0, 1577 .udt_comp = 0, 1578 .udt_dimm_no = 0, 1579 .udt_dimm_col = 0xa, 1580 .udt_dimm_row = 0, 1581 .udt_dimm_bank = 0, 1582 .udt_dimm_bank_group = 0, 1583 .udt_dimm_subchan = 0, 1584 .udt_dimm_rm = 0, 1585 .udt_dimm_cs = 0 1586 }, { 1587 /* 1588 * This next set shows that we honor the hash of bit 8, but don't hash 1589 * other bits. 1590 */ 1591 .udt_desc = "DF 4D2 NPS 2K 6ch (6)", 1592 .udt_umc = &zen_umc_nps_6ch_2k, 1593 .udt_pa = 0x68002b, 1594 .udt_pass = B_TRUE, 1595 .udt_norm_addr = 0x11502b, 1596 .udt_sock = 0, 1597 .udt_die = 0, 1598 .udt_comp = 0x5, 1599 .udt_dimm_no = 0, 1600 .udt_dimm_col = 0x20a, 1601 .udt_dimm_row = 0x4, 1602 .udt_dimm_bank = 0x2, 1603 .udt_dimm_bank_group = 0x2, 1604 .udt_dimm_subchan = 0, 1605 .udt_dimm_rm = 0, 1606 .udt_dimm_cs = 0 1607 }, { 1608 .udt_desc = "DF 4D2 NPS 2K 6ch (7)", 1609 .udt_umc = &zen_umc_nps_6ch_2k, 1610 .udt_pa = 0x68012b, 1611 .udt_pass = B_TRUE, 1612 .udt_norm_addr = 0x11502b, 1613 .udt_sock = 0, 1614 .udt_die = 0, 1615 .udt_comp = 0x4, 1616 .udt_dimm_no = 0, 1617 .udt_dimm_col = 0x20a, 1618 .udt_dimm_row = 0x4, 1619 .udt_dimm_bank = 0x2, 1620 .udt_dimm_bank_group = 0x2, 1621 .udt_dimm_subchan = 0, 1622 .udt_dimm_rm = 0, 1623 .udt_dimm_cs = 0 1624 }, { 1625 .udt_desc = "DF 4D2 NPS 2K 6ch (8)", 1626 .udt_umc = &zen_umc_nps_6ch_2k, 1627 .udt_pa = 0x67f02b, 1628 .udt_pass = B_TRUE, 1629 .udt_norm_addr = 0x11502b, 1630 .udt_sock = 0, 1631 .udt_die = 0, 1632 .udt_comp = 0x3, 1633 .udt_dimm_no = 0, 1634 .udt_dimm_col = 0x20a, 1635 .udt_dimm_row = 0x4, 1636 .udt_dimm_bank = 0x2, 1637 .udt_dimm_bank_group = 0x2, 1638 .udt_dimm_subchan = 0, 1639 .udt_dimm_rm = 0, 1640 .udt_dimm_cs = 0 1641 }, { 1642 .udt_desc = "DF 4D2 NPS 2K 6ch (9)", 1643 .udt_umc = &zen_umc_nps_6ch_2k, 1644 .udt_pa = 0x67f12b, 1645 .udt_pass = B_TRUE, 1646 .udt_norm_addr = 0x11502b, 1647 .udt_sock = 0, 1648 .udt_die = 0, 1649 .udt_comp = 0x2, 1650 .udt_dimm_no = 0, 1651 .udt_dimm_col = 0x20a, 1652 .udt_dimm_row = 0x4, 1653 .udt_dimm_bank = 0x2, 1654 .udt_dimm_bank_group = 0x2, 1655 .udt_dimm_subchan = 0, 1656 .udt_dimm_rm = 0, 1657 .udt_dimm_cs = 0 1658 }, { 1659 .udt_desc = "DF 4D2 NPS 2K 6ch (10)", 1660 .udt_umc = &zen_umc_nps_6ch_2k, 1661 .udt_pa = 0x67e02b, 1662 .udt_pass = B_TRUE, 1663 .udt_norm_addr = 0x11502b, 1664 .udt_sock = 0, 1665 .udt_die = 0, 1666 .udt_comp = 0x1, 1667 .udt_dimm_no = 0, 1668 .udt_dimm_col = 0x20a, 1669 .udt_dimm_row = 0x4, 1670 .udt_dimm_bank = 0x2, 1671 .udt_dimm_bank_group = 0x2, 1672 .udt_dimm_subchan = 0, 1673 .udt_dimm_rm = 0, 1674 .udt_dimm_cs = 0 1675 }, { 1676 .udt_desc = "DF 4D2 NPS 2K 6ch (11)", 1677 .udt_umc = &zen_umc_nps_6ch_2k, 1678 .udt_pa = 0x67e12b, 1679 .udt_pass = B_TRUE, 1680 .udt_norm_addr = 0x11502b, 1681 .udt_sock = 0, 1682 .udt_die = 0, 1683 .udt_comp = 0x0, 1684 .udt_dimm_no = 0, 1685 .udt_dimm_col = 0x20a, 1686 .udt_dimm_row = 0x4, 1687 .udt_dimm_bank = 0x2, 1688 .udt_dimm_bank_group = 0x2, 1689 .udt_dimm_subchan = 0, 1690 .udt_dimm_rm = 0, 1691 .udt_dimm_cs = 0 1692 }, { 1693 /* 1694 * Next, confirm that we preserve bits 9-11 properly as we walk across 1695 * things. Use both bit 21 and bit 30 hashes. This also deals with the 1696 * bit 14 addition to bit 8. 1697 */ 1698 .udt_desc = "DF 4D2 NPS 2K 6ch (12)", 1699 .udt_umc = &zen_umc_nps_6ch_2k, 1700 .udt_pa = 0x1cff23e2b, 1701 .udt_pass = B_TRUE, 1702 .udt_norm_addr = 0x4d530f2b, 1703 .udt_sock = 0, 1704 .udt_die = 0, 1705 .udt_comp = 0, 1706 .udt_dimm_no = 0, 1707 .udt_dimm_col = 0x1ea, 1708 .udt_dimm_row = 0x1354, 1709 .udt_dimm_bank = 0x0, 1710 .udt_dimm_bank_group = 0x6, 1711 .udt_dimm_subchan = 0, 1712 .udt_dimm_rm = 0, 1713 .udt_dimm_cs = 0 1714 }, { 1715 .udt_desc = "DF 4D2 NPS 2K 6ch (13)", 1716 .udt_umc = &zen_umc_nps_6ch_2k, 1717 .udt_pa = 0x1cff23f2b, 1718 .udt_pass = B_TRUE, 1719 .udt_norm_addr = 0x4d530f2b, 1720 .udt_sock = 0, 1721 .udt_die = 0, 1722 .udt_comp = 1, 1723 .udt_dimm_no = 0, 1724 .udt_dimm_col = 0x1ea, 1725 .udt_dimm_row = 0x1354, 1726 .udt_dimm_bank = 0x0, 1727 .udt_dimm_bank_group = 0x6, 1728 .udt_dimm_subchan = 0, 1729 .udt_dimm_rm = 0, 1730 .udt_dimm_cs = 0 1731 }, { 1732 .udt_desc = "DF 4D2 NPS 2K 6ch (14)", 1733 .udt_umc = &zen_umc_nps_6ch_2k, 1734 .udt_pa = 0x1cff24f2b, 1735 .udt_pass = B_TRUE, 1736 .udt_norm_addr = 0x4d530f2b, 1737 .udt_sock = 0, 1738 .udt_die = 0, 1739 .udt_comp = 2, 1740 .udt_dimm_no = 0, 1741 .udt_dimm_col = 0x1ea, 1742 .udt_dimm_row = 0x1354, 1743 .udt_dimm_bank = 0x0, 1744 .udt_dimm_bank_group = 0x6, 1745 .udt_dimm_subchan = 0, 1746 .udt_dimm_rm = 0, 1747 .udt_dimm_cs = 0 1748 }, { 1749 .udt_desc = "DF 4D2 NPS 2K 6ch (15)", 1750 .udt_umc = &zen_umc_nps_6ch_2k, 1751 .udt_pa = 0x1cff24e2b, 1752 .udt_pass = B_TRUE, 1753 .udt_norm_addr = 0x4d530f2b, 1754 .udt_sock = 0, 1755 .udt_die = 0, 1756 .udt_comp = 3, 1757 .udt_dimm_no = 0, 1758 .udt_dimm_col = 0x1ea, 1759 .udt_dimm_row = 0x1354, 1760 .udt_dimm_bank = 0x0, 1761 .udt_dimm_bank_group = 0x6, 1762 .udt_dimm_subchan = 0, 1763 .udt_dimm_rm = 0, 1764 .udt_dimm_cs = 0 1765 }, { 1766 .udt_desc = "DF 4D2 NPS 2K 6ch (16)", 1767 .udt_umc = &zen_umc_nps_6ch_2k, 1768 .udt_pa = 0x1cff25f2b, 1769 .udt_pass = B_TRUE, 1770 .udt_norm_addr = 0x4d530f2b, 1771 .udt_sock = 0, 1772 .udt_die = 0, 1773 .udt_comp = 4, 1774 .udt_dimm_no = 0, 1775 .udt_dimm_col = 0x1ea, 1776 .udt_dimm_row = 0x1354, 1777 .udt_dimm_bank = 0x0, 1778 .udt_dimm_bank_group = 0x6, 1779 .udt_dimm_subchan = 0, 1780 .udt_dimm_rm = 0, 1781 .udt_dimm_cs = 0 1782 }, { 1783 .udt_desc = "DF 4D2 NPS 2K 6ch (17)", 1784 .udt_umc = &zen_umc_nps_6ch_2k, 1785 .udt_pa = 0x1cff25e2b, 1786 .udt_pass = B_TRUE, 1787 .udt_norm_addr = 0x4d530f2b, 1788 .udt_sock = 0, 1789 .udt_die = 0, 1790 .udt_comp = 5, 1791 .udt_dimm_no = 0, 1792 .udt_dimm_col = 0x1ea, 1793 .udt_dimm_row = 0x1354, 1794 .udt_dimm_bank = 0x0, 1795 .udt_dimm_bank_group = 0x6, 1796 .udt_dimm_subchan = 0, 1797 .udt_dimm_rm = 0, 1798 .udt_dimm_cs = 0 1799 }, { 1800 .udt_desc = "DF 4D2 NPS 2K 6ch (18)", 1801 .udt_umc = &zen_umc_nps_6ch_2k, 1802 .udt_pa = 0x23456789a, 1803 .udt_pass = B_TRUE, 1804 .udt_norm_addr = 0x5e0e6c9a, 1805 .udt_sock = 0, 1806 .udt_die = 0, 1807 .udt_comp = 1, 1808 .udt_dimm_no = 0, 1809 .udt_dimm_col = 0x196, 1810 .udt_dimm_row = 0x1783, 1811 .udt_dimm_bank = 0x3, 1812 .udt_dimm_bank_group = 0x4, 1813 .udt_dimm_subchan = 0, 1814 .udt_dimm_rm = 0, 1815 .udt_dimm_cs = 0 1816 }, { 1817 .udt_desc = "DF 4D2 NPS 2K 6ch (19)", 1818 .udt_umc = &zen_umc_nps_6ch_2k, 1819 .udt_pa = 0xa98765432, 1820 .udt_pass = B_TRUE, 1821 .udt_norm_addr = 0x1c413ba32, 1822 .udt_sock = 0, 1823 .udt_die = 0, 1824 .udt_comp = 0, 1825 .udt_dimm_no = 0, 1826 .udt_dimm_col = 0x34c, 1827 .udt_dimm_row = 0x7104, 1828 .udt_dimm_bank = 0x1, 1829 .udt_dimm_bank_group = 0x7, 1830 .udt_dimm_subchan = 0, 1831 .udt_dimm_rm = 0, 1832 .udt_dimm_cs = 0 1833 }, { 1834 .udt_desc = "DF 4D2 NPS 2K 6ch (20)", 1835 .udt_umc = &zen_umc_nps_6ch_2k, 1836 .udt_pa = 0xbeeffeeb, 1837 .udt_pass = B_TRUE, 1838 .udt_norm_addr = 0x1fd2afeb, 1839 .udt_sock = 0, 1840 .udt_die = 0, 1841 .udt_comp = 1, 1842 .udt_dimm_no = 0, 1843 .udt_dimm_col = 0x1fa, 1844 .udt_dimm_row = 0x7f4, 1845 .udt_dimm_bank = 0x1, 1846 .udt_dimm_bank_group = 0x5, 1847 .udt_dimm_subchan = 1, 1848 .udt_dimm_rm = 0, 1849 .udt_dimm_cs = 0 1850 }, { 1851 .udt_desc = "DF 4D2 NPS 2K 5ch (0)", 1852 .udt_umc = &zen_umc_nps_5ch_2k, 1853 .udt_pa = 0x95, 1854 .udt_pass = B_TRUE, 1855 .udt_norm_addr = 0x95, 1856 .udt_sock = 0, 1857 .udt_die = 0, 1858 .udt_comp = 0, 1859 .udt_dimm_no = 0, 1860 .udt_dimm_col = 0x15, 1861 .udt_dimm_row = 0x0, 1862 .udt_dimm_bank = 0x0, 1863 .udt_dimm_bank_group = 0x0, 1864 .udt_dimm_subchan = 0, 1865 .udt_dimm_rm = 0, 1866 .udt_dimm_cs = 0 1867 }, { 1868 .udt_desc = "DF 4D2 NPS 2K 5ch (1)", 1869 .udt_umc = &zen_umc_nps_5ch_2k, 1870 .udt_pa = 0x1195, 1871 .udt_pass = B_TRUE, 1872 .udt_norm_addr = 0x95, 1873 .udt_sock = 0, 1874 .udt_die = 0, 1875 .udt_comp = 1, 1876 .udt_dimm_no = 0, 1877 .udt_dimm_col = 0x15, 1878 .udt_dimm_row = 0x0, 1879 .udt_dimm_bank = 0x0, 1880 .udt_dimm_bank_group = 0x0, 1881 .udt_dimm_subchan = 0, 1882 .udt_dimm_rm = 0, 1883 .udt_dimm_cs = 0 1884 }, { 1885 .udt_desc = "DF 4D2 NPS 2K 5ch (2)", 1886 .udt_umc = &zen_umc_nps_5ch_2k, 1887 .udt_pa = 0x195, 1888 .udt_pass = B_TRUE, 1889 .udt_norm_addr = 0x95, 1890 .udt_sock = 0, 1891 .udt_die = 0, 1892 .udt_comp = 2, 1893 .udt_dimm_no = 0, 1894 .udt_dimm_col = 0x15, 1895 .udt_dimm_row = 0x0, 1896 .udt_dimm_bank = 0x0, 1897 .udt_dimm_bank_group = 0x0, 1898 .udt_dimm_subchan = 0, 1899 .udt_dimm_rm = 0, 1900 .udt_dimm_cs = 0 1901 }, { 1902 .udt_desc = "DF 4D2 NPS 2K 5ch (3)", 1903 .udt_umc = &zen_umc_nps_5ch_2k, 1904 .udt_pa = 0x2095, 1905 .udt_pass = B_TRUE, 1906 .udt_norm_addr = 0x95, 1907 .udt_sock = 0, 1908 .udt_die = 0, 1909 .udt_comp = 3, 1910 .udt_dimm_no = 0, 1911 .udt_dimm_col = 0x15, 1912 .udt_dimm_row = 0x0, 1913 .udt_dimm_bank = 0x0, 1914 .udt_dimm_bank_group = 0x0, 1915 .udt_dimm_subchan = 0, 1916 .udt_dimm_rm = 0, 1917 .udt_dimm_cs = 0 1918 }, { 1919 .udt_desc = "DF 4D2 NPS 2K 5ch (4)", 1920 .udt_umc = &zen_umc_nps_5ch_2k, 1921 .udt_pa = 0x1095, 1922 .udt_pass = B_TRUE, 1923 .udt_norm_addr = 0x95, 1924 .udt_sock = 0, 1925 .udt_die = 0, 1926 .udt_comp = 4, 1927 .udt_dimm_no = 0, 1928 .udt_dimm_col = 0x15, 1929 .udt_dimm_row = 0x0, 1930 .udt_dimm_bank = 0x0, 1931 .udt_dimm_bank_group = 0x0, 1932 .udt_dimm_subchan = 0, 1933 .udt_dimm_rm = 0, 1934 .udt_dimm_cs = 0 1935 }, { 1936 /* 1937 * The 5 channel variant doesn't use any hash bits. We use addresses 1938 * that would normally impact hashing for this next set. In addition, 1939 * exercise the preserved bits 9-11. 1940 */ 1941 .udt_desc = "DF 4D2 NPS 2K 5ch (5)", 1942 .udt_umc = &zen_umc_nps_5ch_2k, 1943 .udt_pa = 0xffffff95, 1944 .udt_pass = B_TRUE, 1945 .udt_norm_addr = 0x33333795, 1946 .udt_sock = 0, 1947 .udt_die = 0, 1948 .udt_comp = 2, 1949 .udt_dimm_no = 0, 1950 .udt_dimm_col = 0x2f5, 1951 .udt_dimm_row = 0xccc, 1952 .udt_dimm_bank = 0x1, 1953 .udt_dimm_bank_group = 0x6, 1954 .udt_dimm_subchan = 0, 1955 .udt_dimm_rm = 0, 1956 .udt_dimm_cs = 0 1957 }, { 1958 .udt_desc = "DF 4D2 NPS 2K 5ch (6)", 1959 .udt_umc = &zen_umc_nps_5ch_2k, 1960 .udt_pa = 0x100001e95, 1961 .udt_pass = B_TRUE, 1962 .udt_norm_addr = 0x33333795, 1963 .udt_sock = 0, 1964 .udt_die = 0, 1965 .udt_comp = 3, 1966 .udt_dimm_no = 0, 1967 .udt_dimm_col = 0x2f5, 1968 .udt_dimm_row = 0xccc, 1969 .udt_dimm_bank = 0x1, 1970 .udt_dimm_bank_group = 0x6, 1971 .udt_dimm_subchan = 0, 1972 .udt_dimm_rm = 0, 1973 .udt_dimm_cs = 0 1974 }, { 1975 .udt_desc = "DF 4D2 NPS 2K 5ch (7)", 1976 .udt_umc = &zen_umc_nps_5ch_2k, 1977 .udt_pa = 0x100000f95, 1978 .udt_pass = B_TRUE, 1979 .udt_norm_addr = 0x33333795, 1980 .udt_sock = 0, 1981 .udt_die = 0, 1982 .udt_comp = 1, 1983 .udt_dimm_no = 0, 1984 .udt_dimm_col = 0x2f5, 1985 .udt_dimm_row = 0xccc, 1986 .udt_dimm_bank = 0x1, 1987 .udt_dimm_bank_group = 0x6, 1988 .udt_dimm_subchan = 0, 1989 .udt_dimm_rm = 0, 1990 .udt_dimm_cs = 0 1991 }, { 1992 .udt_desc = "DF 4D2 NPS 2K 5ch (8)", 1993 .udt_umc = &zen_umc_nps_5ch_2k, 1994 .udt_pa = 0x100000e95, 1995 .udt_pass = B_TRUE, 1996 .udt_norm_addr = 0x33333795, 1997 .udt_sock = 0, 1998 .udt_die = 0, 1999 .udt_comp = 4, 2000 .udt_dimm_no = 0, 2001 .udt_dimm_col = 0x2f5, 2002 .udt_dimm_row = 0xccc, 2003 .udt_dimm_bank = 0x1, 2004 .udt_dimm_bank_group = 0x6, 2005 .udt_dimm_subchan = 0, 2006 .udt_dimm_rm = 0, 2007 .udt_dimm_cs = 0 2008 }, { 2009 .udt_desc = "DF 4D2 NPS 2K 5ch (9)", 2010 .udt_umc = &zen_umc_nps_5ch_2k, 2011 .udt_pa = 0xfffffe95, 2012 .udt_pass = B_TRUE, 2013 .udt_norm_addr = 0x33333795, 2014 .udt_sock = 0, 2015 .udt_die = 0, 2016 .udt_comp = 0, 2017 .udt_dimm_no = 0, 2018 .udt_dimm_col = 0x2f5, 2019 .udt_dimm_row = 0xccc, 2020 .udt_dimm_bank = 0x1, 2021 .udt_dimm_bank_group = 0x6, 2022 .udt_dimm_subchan = 0, 2023 .udt_dimm_rm = 0, 2024 .udt_dimm_cs = 0 2025 }, { 2026 .udt_desc = "DF 4D2 NPS 1K 10ch (0)", 2027 .udt_umc = &zen_umc_nps_10ch_1k, 2028 .udt_pa = 0xf7, 2029 .udt_pass = B_TRUE, 2030 .udt_norm_addr = 0xf7, 2031 .udt_sock = 0, 2032 .udt_die = 0, 2033 .udt_comp = 0, 2034 .udt_dimm_no = 0, 2035 .udt_dimm_col = 0x1d, 2036 .udt_dimm_row = 0x0, 2037 .udt_dimm_bank = 0x0, 2038 .udt_dimm_bank_group = 0x0, 2039 .udt_dimm_subchan = 1, 2040 .udt_dimm_rm = 0, 2041 .udt_dimm_cs = 0 2042 }, { 2043 .udt_desc = "DF 4D2 NPS 1K 10ch (1)", 2044 .udt_umc = &zen_umc_nps_10ch_1k, 2045 .udt_pa = 0x1f7, 2046 .udt_pass = B_TRUE, 2047 .udt_norm_addr = 0xf7, 2048 .udt_sock = 0, 2049 .udt_die = 0, 2050 .udt_comp = 1, 2051 .udt_dimm_no = 0, 2052 .udt_dimm_col = 0x1d, 2053 .udt_dimm_row = 0x0, 2054 .udt_dimm_bank = 0x0, 2055 .udt_dimm_bank_group = 0x0, 2056 .udt_dimm_subchan = 1, 2057 .udt_dimm_rm = 0, 2058 .udt_dimm_cs = 0 2059 }, { 2060 .udt_desc = "DF 4D2 NPS 1K 10ch (2)", 2061 .udt_umc = &zen_umc_nps_10ch_1k, 2062 .udt_pa = 0x12f7, 2063 .udt_pass = B_TRUE, 2064 .udt_norm_addr = 0xf7, 2065 .udt_sock = 0, 2066 .udt_die = 0, 2067 .udt_comp = 2, 2068 .udt_dimm_no = 0, 2069 .udt_dimm_col = 0x1d, 2070 .udt_dimm_row = 0x0, 2071 .udt_dimm_bank = 0x0, 2072 .udt_dimm_bank_group = 0x0, 2073 .udt_dimm_subchan = 1, 2074 .udt_dimm_rm = 0, 2075 .udt_dimm_cs = 0 2076 }, { 2077 .udt_desc = "DF 4D2 NPS 1K 10ch (3)", 2078 .udt_umc = &zen_umc_nps_10ch_1k, 2079 .udt_pa = 0x13f7, 2080 .udt_pass = B_TRUE, 2081 .udt_norm_addr = 0xf7, 2082 .udt_sock = 0, 2083 .udt_die = 0, 2084 .udt_comp = 3, 2085 .udt_dimm_no = 0, 2086 .udt_dimm_col = 0x1d, 2087 .udt_dimm_row = 0x0, 2088 .udt_dimm_bank = 0x0, 2089 .udt_dimm_bank_group = 0x0, 2090 .udt_dimm_subchan = 1, 2091 .udt_dimm_rm = 0, 2092 .udt_dimm_cs = 0 2093 }, { 2094 .udt_desc = "DF 4D2 NPS 1K 10ch (4)", 2095 .udt_umc = &zen_umc_nps_10ch_1k, 2096 .udt_pa = 0x2f7, 2097 .udt_pass = B_TRUE, 2098 .udt_norm_addr = 0xf7, 2099 .udt_sock = 0, 2100 .udt_die = 0, 2101 .udt_comp = 4, 2102 .udt_dimm_no = 0, 2103 .udt_dimm_col = 0x1d, 2104 .udt_dimm_row = 0x0, 2105 .udt_dimm_bank = 0x0, 2106 .udt_dimm_bank_group = 0x0, 2107 .udt_dimm_subchan = 1, 2108 .udt_dimm_rm = 0, 2109 .udt_dimm_cs = 0 2110 }, { 2111 .udt_desc = "DF 4D2 NPS 1K 10ch (5)", 2112 .udt_umc = &zen_umc_nps_10ch_1k, 2113 .udt_pa = 0x3f7, 2114 .udt_pass = B_TRUE, 2115 .udt_norm_addr = 0xf7, 2116 .udt_sock = 0, 2117 .udt_die = 0, 2118 .udt_comp = 5, 2119 .udt_dimm_no = 0, 2120 .udt_dimm_col = 0x1d, 2121 .udt_dimm_row = 0x0, 2122 .udt_dimm_bank = 0x0, 2123 .udt_dimm_bank_group = 0x0, 2124 .udt_dimm_subchan = 1, 2125 .udt_dimm_rm = 0, 2126 .udt_dimm_cs = 0 2127 }, { 2128 .udt_desc = "DF 4D2 NPS 1K 10ch (6)", 2129 .udt_umc = &zen_umc_nps_10ch_1k, 2130 .udt_pa = 0x20f7, 2131 .udt_pass = B_TRUE, 2132 .udt_norm_addr = 0xf7, 2133 .udt_sock = 0, 2134 .udt_die = 0, 2135 .udt_comp = 6, 2136 .udt_dimm_no = 0, 2137 .udt_dimm_col = 0x1d, 2138 .udt_dimm_row = 0x0, 2139 .udt_dimm_bank = 0x0, 2140 .udt_dimm_bank_group = 0x0, 2141 .udt_dimm_subchan = 1, 2142 .udt_dimm_rm = 0, 2143 .udt_dimm_cs = 0 2144 }, { 2145 .udt_desc = "DF 4D2 NPS 1K 10ch (7)", 2146 .udt_umc = &zen_umc_nps_10ch_1k, 2147 .udt_pa = 0x21f7, 2148 .udt_pass = B_TRUE, 2149 .udt_norm_addr = 0xf7, 2150 .udt_sock = 0, 2151 .udt_die = 0, 2152 .udt_comp = 7, 2153 .udt_dimm_no = 0, 2154 .udt_dimm_col = 0x1d, 2155 .udt_dimm_row = 0x0, 2156 .udt_dimm_bank = 0x0, 2157 .udt_dimm_bank_group = 0x0, 2158 .udt_dimm_subchan = 1, 2159 .udt_dimm_rm = 0, 2160 .udt_dimm_cs = 0 2161 }, { 2162 .udt_desc = "DF 4D2 NPS 1K 10ch (8)", 2163 .udt_umc = &zen_umc_nps_10ch_1k, 2164 .udt_pa = 0x10f7, 2165 .udt_pass = B_TRUE, 2166 .udt_norm_addr = 0xf7, 2167 .udt_sock = 0, 2168 .udt_die = 0, 2169 .udt_comp = 8, 2170 .udt_dimm_no = 0, 2171 .udt_dimm_col = 0x1d, 2172 .udt_dimm_row = 0x0, 2173 .udt_dimm_bank = 0x0, 2174 .udt_dimm_bank_group = 0x0, 2175 .udt_dimm_subchan = 1, 2176 .udt_dimm_rm = 0, 2177 .udt_dimm_cs = 0 2178 }, { 2179 .udt_desc = "DF 4D2 NPS 1K 10ch (9)", 2180 .udt_umc = &zen_umc_nps_10ch_1k, 2181 .udt_pa = 0x11f7, 2182 .udt_pass = B_TRUE, 2183 .udt_norm_addr = 0xf7, 2184 .udt_sock = 0, 2185 .udt_die = 0, 2186 .udt_comp = 9, 2187 .udt_dimm_no = 0, 2188 .udt_dimm_col = 0x1d, 2189 .udt_dimm_row = 0x0, 2190 .udt_dimm_bank = 0x0, 2191 .udt_dimm_bank_group = 0x0, 2192 .udt_dimm_subchan = 1, 2193 .udt_dimm_rm = 0, 2194 .udt_dimm_cs = 0 2195 }, { 2196 /* 2197 * Exercise hashing bit 8, but ensure no hashing of bit 9 comes into 2198 * play. Note, we don't touch bit 14 as part of this. 2199 */ 2200 .udt_desc = "DF 4D2 NPS 1K 10ch (10)", 2201 .udt_umc = &zen_umc_nps_10ch_1k, 2202 .udt_pa = 0xc06300f7, 2203 .udt_pass = B_TRUE, 2204 .udt_norm_addr = 0x133d18f7, 2205 .udt_sock = 0, 2206 .udt_die = 0, 2207 .udt_comp = 9, 2208 .udt_dimm_no = 0, 2209 .udt_dimm_col = 0x31d, 2210 .udt_dimm_row = 0x4cf, 2211 .udt_dimm_bank = 0x0, 2212 .udt_dimm_bank_group = 0x2, 2213 .udt_dimm_subchan = 1, 2214 .udt_dimm_rm = 0, 2215 .udt_dimm_cs = 0 2216 }, { 2217 .udt_desc = "DF 4D2 NPS 1K 10ch (11)", 2218 .udt_umc = &zen_umc_nps_10ch_1k, 2219 .udt_pa = 0xc06301f7, 2220 .udt_pass = B_TRUE, 2221 .udt_norm_addr = 0x133d18f7, 2222 .udt_sock = 0, 2223 .udt_die = 0, 2224 .udt_comp = 8, 2225 .udt_dimm_no = 0, 2226 .udt_dimm_col = 0x31d, 2227 .udt_dimm_row = 0x4cf, 2228 .udt_dimm_bank = 0x0, 2229 .udt_dimm_bank_group = 0x2, 2230 .udt_dimm_subchan = 1, 2231 .udt_dimm_rm = 0, 2232 .udt_dimm_cs = 0 2233 }, { 2234 .udt_desc = "DF 4D2 NPS 1K 10ch (12)", 2235 .udt_umc = &zen_umc_nps_10ch_1k, 2236 .udt_pa = 0xc06310f7, 2237 .udt_pass = B_TRUE, 2238 .udt_norm_addr = 0x133d18f7, 2239 .udt_sock = 0, 2240 .udt_die = 0, 2241 .udt_comp = 7, 2242 .udt_dimm_no = 0, 2243 .udt_dimm_col = 0x31d, 2244 .udt_dimm_row = 0x4cf, 2245 .udt_dimm_bank = 0x0, 2246 .udt_dimm_bank_group = 0x2, 2247 .udt_dimm_subchan = 1, 2248 .udt_dimm_rm = 0, 2249 .udt_dimm_cs = 0 2250 }, { 2251 .udt_desc = "DF 4D2 NPS 1K 10ch (13)", 2252 .udt_umc = &zen_umc_nps_10ch_1k, 2253 .udt_pa = 0xc06311f7, 2254 .udt_pass = B_TRUE, 2255 .udt_norm_addr = 0x133d18f7, 2256 .udt_sock = 0, 2257 .udt_die = 0, 2258 .udt_comp = 6, 2259 .udt_dimm_no = 0, 2260 .udt_dimm_col = 0x31d, 2261 .udt_dimm_row = 0x4cf, 2262 .udt_dimm_bank = 0x0, 2263 .udt_dimm_bank_group = 0x2, 2264 .udt_dimm_subchan = 1, 2265 .udt_dimm_rm = 0, 2266 .udt_dimm_cs = 0 2267 }, { 2268 .udt_desc = "DF 4D2 NPS 1K 10ch (14)", 2269 .udt_umc = &zen_umc_nps_10ch_1k, 2270 .udt_pa = 0xc062f2f7, 2271 .udt_pass = B_TRUE, 2272 .udt_norm_addr = 0x133d18f7, 2273 .udt_sock = 0, 2274 .udt_die = 0, 2275 .udt_comp = 5, 2276 .udt_dimm_no = 0, 2277 .udt_dimm_col = 0x31d, 2278 .udt_dimm_row = 0x4cf, 2279 .udt_dimm_bank = 0x0, 2280 .udt_dimm_bank_group = 0x2, 2281 .udt_dimm_subchan = 1, 2282 .udt_dimm_rm = 0, 2283 .udt_dimm_cs = 0 2284 }, { 2285 .udt_desc = "DF 4D2 NPS 1K 10ch (15)", 2286 .udt_umc = &zen_umc_nps_10ch_1k, 2287 .udt_pa = 0xc062f3f7, 2288 .udt_pass = B_TRUE, 2289 .udt_norm_addr = 0x133d18f7, 2290 .udt_sock = 0, 2291 .udt_die = 0, 2292 .udt_comp = 4, 2293 .udt_dimm_no = 0, 2294 .udt_dimm_col = 0x31d, 2295 .udt_dimm_row = 0x4cf, 2296 .udt_dimm_bank = 0x0, 2297 .udt_dimm_bank_group = 0x2, 2298 .udt_dimm_subchan = 1, 2299 .udt_dimm_rm = 0, 2300 .udt_dimm_cs = 0 2301 }, { 2302 .udt_desc = "DF 4D2 NPS 1K 10ch (16)", 2303 .udt_umc = &zen_umc_nps_10ch_1k, 2304 .udt_pa = 0xc06302f7, 2305 .udt_pass = B_TRUE, 2306 .udt_norm_addr = 0x133d18f7, 2307 .udt_sock = 0, 2308 .udt_die = 0, 2309 .udt_comp = 3, 2310 .udt_dimm_no = 0, 2311 .udt_dimm_col = 0x31d, 2312 .udt_dimm_row = 0x4cf, 2313 .udt_dimm_bank = 0x0, 2314 .udt_dimm_bank_group = 0x2, 2315 .udt_dimm_subchan = 1, 2316 .udt_dimm_rm = 0, 2317 .udt_dimm_cs = 0 2318 }, { 2319 .udt_desc = "DF 4D2 NPS 1K 10ch (17)", 2320 .udt_umc = &zen_umc_nps_10ch_1k, 2321 .udt_pa = 0xc06303f7, 2322 .udt_pass = B_TRUE, 2323 .udt_norm_addr = 0x133d18f7, 2324 .udt_sock = 0, 2325 .udt_die = 0, 2326 .udt_comp = 2, 2327 .udt_dimm_no = 0, 2328 .udt_dimm_col = 0x31d, 2329 .udt_dimm_row = 0x4cf, 2330 .udt_dimm_bank = 0x0, 2331 .udt_dimm_bank_group = 0x2, 2332 .udt_dimm_subchan = 1, 2333 .udt_dimm_rm = 0, 2334 .udt_dimm_cs = 0 2335 }, { 2336 .udt_desc = "DF 4D2 NPS 1K 10ch (18)", 2337 .udt_umc = &zen_umc_nps_10ch_1k, 2338 .udt_pa = 0xc062f0f7, 2339 .udt_pass = B_TRUE, 2340 .udt_norm_addr = 0x133d18f7, 2341 .udt_sock = 0, 2342 .udt_die = 0, 2343 .udt_comp = 1, 2344 .udt_dimm_no = 0, 2345 .udt_dimm_col = 0x31d, 2346 .udt_dimm_row = 0x4cf, 2347 .udt_dimm_bank = 0x0, 2348 .udt_dimm_bank_group = 0x2, 2349 .udt_dimm_subchan = 1, 2350 .udt_dimm_rm = 0, 2351 .udt_dimm_cs = 0 2352 }, { 2353 .udt_desc = "DF 4D2 NPS 1K 10ch (19)", 2354 .udt_umc = &zen_umc_nps_10ch_1k, 2355 .udt_pa = 0xc062f1f7, 2356 .udt_pass = B_TRUE, 2357 .udt_norm_addr = 0x133d18f7, 2358 .udt_sock = 0, 2359 .udt_die = 0, 2360 .udt_comp = 0, 2361 .udt_dimm_no = 0, 2362 .udt_dimm_col = 0x31d, 2363 .udt_dimm_row = 0x4cf, 2364 .udt_dimm_bank = 0x0, 2365 .udt_dimm_bank_group = 0x2, 2366 .udt_dimm_subchan = 1, 2367 .udt_dimm_rm = 0, 2368 .udt_dimm_cs = 0 2369 }, { 2370 /* 2371 * One last set of 10 channel tests with bit 14 on the scene and 2372 * ensuring that bits 10-11 are preserved. 2373 */ 2374 .udt_desc = "DF 4D2 NPS 1K 10ch (20)", 2375 .udt_umc = &zen_umc_nps_10ch_1k, 2376 .udt_pa = 0xfdcbbcdf7, 2377 .udt_pass = B_TRUE, 2378 .udt_norm_addr = 0x19612c7f7, 2379 .udt_sock = 0, 2380 .udt_die = 0, 2381 .udt_comp = 3, 2382 .udt_dimm_no = 0, 2383 .udt_dimm_col = 0xfd, 2384 .udt_dimm_row = 0x6584, 2385 .udt_dimm_bank = 0x2, 2386 .udt_dimm_bank_group = 0x5, 2387 .udt_dimm_subchan = 1, 2388 .udt_dimm_rm = 0, 2389 .udt_dimm_cs = 0 2390 }, { 2391 .udt_desc = "DF 4D2 NPS 1K 10ch (21)", 2392 .udt_umc = &zen_umc_nps_10ch_1k, 2393 .udt_pa = 0xfdcbbccf7, 2394 .udt_pass = B_TRUE, 2395 .udt_norm_addr = 0x19612c7f7, 2396 .udt_sock = 0, 2397 .udt_die = 0, 2398 .udt_comp = 2, 2399 .udt_dimm_no = 0, 2400 .udt_dimm_col = 0xfd, 2401 .udt_dimm_row = 0x6584, 2402 .udt_dimm_bank = 0x2, 2403 .udt_dimm_bank_group = 0x5, 2404 .udt_dimm_subchan = 1, 2405 .udt_dimm_rm = 0, 2406 .udt_dimm_cs = 0 2407 }, { 2408 .udt_desc = "DF 4D2 NPS 1K 10ch (22)", 2409 .udt_umc = &zen_umc_nps_10ch_1k, 2410 .udt_pa = 0xfdcbbaef7, 2411 .udt_pass = B_TRUE, 2412 .udt_norm_addr = 0x19612c7f7, 2413 .udt_sock = 0, 2414 .udt_die = 0, 2415 .udt_comp = 1, 2416 .udt_dimm_no = 0, 2417 .udt_dimm_col = 0xfd, 2418 .udt_dimm_row = 0x6584, 2419 .udt_dimm_bank = 0x2, 2420 .udt_dimm_bank_group = 0x5, 2421 .udt_dimm_subchan = 1, 2422 .udt_dimm_rm = 0, 2423 .udt_dimm_cs = 0 2424 }, { 2425 .udt_desc = "DF 4D2 NPS 1K 10ch (23)", 2426 .udt_umc = &zen_umc_nps_10ch_1k, 2427 .udt_pa = 0xfdcbbaff7, 2428 .udt_pass = B_TRUE, 2429 .udt_norm_addr = 0x19612c7f7, 2430 .udt_sock = 0, 2431 .udt_die = 0, 2432 .udt_comp = 0, 2433 .udt_dimm_no = 0, 2434 .udt_dimm_col = 0xfd, 2435 .udt_dimm_row = 0x6584, 2436 .udt_dimm_bank = 0x2, 2437 .udt_dimm_bank_group = 0x5, 2438 .udt_dimm_subchan = 1, 2439 .udt_dimm_rm = 0, 2440 .udt_dimm_cs = 0 2441 }, { 2442 .udt_desc = "DF 4D2 NPS 1K 10ch (24)", 2443 .udt_umc = &zen_umc_nps_10ch_1k, 2444 .udt_pa = 0xfdcbbbef7, 2445 .udt_pass = B_TRUE, 2446 .udt_norm_addr = 0x19612c7f7, 2447 .udt_sock = 0, 2448 .udt_die = 0, 2449 .udt_comp = 9, 2450 .udt_dimm_no = 0, 2451 .udt_dimm_col = 0xfd, 2452 .udt_dimm_row = 0x6584, 2453 .udt_dimm_bank = 0x2, 2454 .udt_dimm_bank_group = 0x5, 2455 .udt_dimm_subchan = 1, 2456 .udt_dimm_rm = 0, 2457 .udt_dimm_cs = 0 2458 }, { 2459 .udt_desc = "DF 4D2 NPS 1K 10ch (25)", 2460 .udt_umc = &zen_umc_nps_10ch_1k, 2461 .udt_pa = 0xfdcbbbff7, 2462 .udt_pass = B_TRUE, 2463 .udt_norm_addr = 0x19612c7f7, 2464 .udt_sock = 0, 2465 .udt_die = 0, 2466 .udt_comp = 8, 2467 .udt_dimm_no = 0, 2468 .udt_dimm_col = 0xfd, 2469 .udt_dimm_row = 0x6584, 2470 .udt_dimm_bank = 0x2, 2471 .udt_dimm_bank_group = 0x5, 2472 .udt_dimm_subchan = 1, 2473 .udt_dimm_rm = 0, 2474 .udt_dimm_cs = 0 2475 }, { 2476 .udt_desc = "DF 4D2 NPS 1K 10ch (26)", 2477 .udt_umc = &zen_umc_nps_10ch_1k, 2478 .udt_pa = 0xfdcbbcff7, 2479 .udt_pass = B_TRUE, 2480 .udt_norm_addr = 0x19612c7f7, 2481 .udt_sock = 0, 2482 .udt_die = 0, 2483 .udt_comp = 7, 2484 .udt_dimm_no = 0, 2485 .udt_dimm_col = 0xfd, 2486 .udt_dimm_row = 0x6584, 2487 .udt_dimm_bank = 0x2, 2488 .udt_dimm_bank_group = 0x5, 2489 .udt_dimm_subchan = 1, 2490 .udt_dimm_rm = 0, 2491 .udt_dimm_cs = 0 2492 }, { 2493 .udt_desc = "DF 4D2 NPS 1K 10ch (27)", 2494 .udt_umc = &zen_umc_nps_10ch_1k, 2495 .udt_pa = 0xfdcbbcef7, 2496 .udt_pass = B_TRUE, 2497 .udt_norm_addr = 0x19612c7f7, 2498 .udt_sock = 0, 2499 .udt_die = 0, 2500 .udt_comp = 6, 2501 .udt_dimm_no = 0, 2502 .udt_dimm_col = 0xfd, 2503 .udt_dimm_row = 0x6584, 2504 .udt_dimm_bank = 0x2, 2505 .udt_dimm_bank_group = 0x5, 2506 .udt_dimm_subchan = 1, 2507 .udt_dimm_rm = 0, 2508 .udt_dimm_cs = 0 2509 }, { 2510 .udt_desc = "DF 4D2 NPS 1K 10ch (28)", 2511 .udt_umc = &zen_umc_nps_10ch_1k, 2512 .udt_pa = 0xfdcbbbcf7, 2513 .udt_pass = B_TRUE, 2514 .udt_norm_addr = 0x19612c7f7, 2515 .udt_sock = 0, 2516 .udt_die = 0, 2517 .udt_comp = 5, 2518 .udt_dimm_no = 0, 2519 .udt_dimm_col = 0xfd, 2520 .udt_dimm_row = 0x6584, 2521 .udt_dimm_bank = 0x2, 2522 .udt_dimm_bank_group = 0x5, 2523 .udt_dimm_subchan = 1, 2524 .udt_dimm_rm = 0, 2525 .udt_dimm_cs = 0 2526 }, { 2527 .udt_desc = "DF 4D2 NPS 1K 10ch (29)", 2528 .udt_umc = &zen_umc_nps_10ch_1k, 2529 .udt_pa = 0xfdcbbbdf7, 2530 .udt_pass = B_TRUE, 2531 .udt_norm_addr = 0x19612c7f7, 2532 .udt_sock = 0, 2533 .udt_die = 0, 2534 .udt_comp = 4, 2535 .udt_dimm_no = 0, 2536 .udt_dimm_col = 0xfd, 2537 .udt_dimm_row = 0x6584, 2538 .udt_dimm_bank = 0x2, 2539 .udt_dimm_bank_group = 0x5, 2540 .udt_dimm_subchan = 1, 2541 .udt_dimm_rm = 0, 2542 .udt_dimm_cs = 0 2543 }, { 2544 .udt_desc = NULL 2545 } }; 2546