1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 /* 17 * This tries to make sure that if we had invalid state somehow, we'd properly 18 * end up detecting an error. Note, for these we try to do include the most bare 19 * minimum style zen_umc_t to minimize the size (at least in this one file for a 20 * change). Note, testing hole decoding errors has been performed in 21 * zen_umc_test_hole.c. 22 */ 23 24 #include "zen_umc_test.h" 25 26 /* 27 * This first structure is used to test: 28 * o Being outside TOM2 29 * o Being in the 1 TiB reserved region 30 * o Not being covered by a valid DF rule 31 * o Several invalid interleave combinations 32 * o Unsupported interleave rule 33 * o Bad Remap set counts 34 */ 35 static const zen_umc_t zen_umc_bad_df = { 36 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 37 .umc_tom2 = 2ULL * 1024ULL * 1024ULL * 1024ULL * 1024ULL, 38 .umc_df_rev = DF_REV_3, 39 .umc_decomp = { 40 .dfd_sock_mask = 0x01, 41 .dfd_die_mask = 0x00, 42 .dfd_node_mask = 0x20, 43 .dfd_comp_mask = 0x1f, 44 .dfd_sock_shift = 0, 45 .dfd_die_shift = 0, 46 .dfd_node_shift = 5, 47 .dfd_comp_shift = 0 48 }, 49 .umc_ndfs = 1, 50 .umc_dfs = { { 51 .zud_dfno = 0, 52 .zud_dram_nrules = 10, 53 .zud_rules = { { 54 .ddr_flags = DF_DRAM_F_VALID, 55 .ddr_base = 0, 56 .ddr_limit = 1ULL * 1024ULL * 1024ULL, 57 .ddr_dest_fabid = 0, 58 .ddr_sock_ileave_bits = 1, 59 .ddr_die_ileave_bits = 0, 60 .ddr_addr_start = 9, 61 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD4_2CH 62 }, { 63 .ddr_flags = DF_DRAM_F_VALID, 64 .ddr_base = 2ULL * 1024ULL * 1024ULL, 65 .ddr_limit = 3ULL * 1024ULL * 1024ULL, 66 .ddr_dest_fabid = 0, 67 .ddr_sock_ileave_bits = 0, 68 .ddr_die_ileave_bits = 2, 69 .ddr_addr_start = 9, 70 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD1_8CH 71 }, { 72 .ddr_flags = DF_DRAM_F_VALID, 73 .ddr_base = 4ULL * 1024ULL * 1024ULL, 74 .ddr_limit = 5ULL * 1024ULL * 1024ULL, 75 .ddr_dest_fabid = 0, 76 .ddr_sock_ileave_bits = 0, 77 .ddr_die_ileave_bits = 2, 78 .ddr_addr_start = 9, 79 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 80 }, { 81 .ddr_flags = DF_DRAM_F_VALID, 82 .ddr_base = 6ULL * 1024ULL * 1024ULL, 83 .ddr_limit = 7ULL * 1024ULL * 1024ULL, 84 .ddr_dest_fabid = 0, 85 .ddr_sock_ileave_bits = 2, 86 .ddr_die_ileave_bits = 0, 87 .ddr_addr_start = 9, 88 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 89 }, { 90 .ddr_flags = DF_DRAM_F_VALID, 91 .ddr_base = 8ULL * 1024ULL * 1024ULL, 92 .ddr_limit = 9ULL * 1024ULL * 1024ULL, 93 .ddr_dest_fabid = 0, 94 .ddr_sock_ileave_bits = 2, 95 .ddr_die_ileave_bits = 0, 96 .ddr_addr_start = 9, 97 .ddr_chan_ileave = INT32_MAX 98 }, { 99 .ddr_flags = DF_DRAM_F_VALID, 100 .ddr_base = 10ULL * 1024ULL * 1024ULL, 101 .ddr_limit = 11ULL * 1024ULL * 1024ULL, 102 .ddr_dest_fabid = 0, 103 .ddr_sock_ileave_bits = 1, 104 .ddr_die_ileave_bits = 1, 105 .ddr_addr_start = 9, 106 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 107 }, { 108 .ddr_flags = DF_DRAM_F_VALID, 109 .ddr_base = 12ULL * 1024ULL * 1024ULL, 110 .ddr_limit = 13ULL * 1024ULL * 1024ULL, 111 .ddr_dest_fabid = 0, 112 .ddr_sock_ileave_bits = 0, 113 .ddr_die_ileave_bits = 2, 114 .ddr_addr_start = 9, 115 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 116 }, { 117 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN | 118 DF_DRAM_F_REMAP_SOCK, 119 .ddr_base = 14ULL * 1024ULL * 1024ULL, 120 .ddr_limit = 15ULL * 1024ULL * 1024ULL, 121 .ddr_dest_fabid = 0, 122 .ddr_sock_ileave_bits = 0, 123 .ddr_die_ileave_bits = 0, 124 .ddr_addr_start = 9, 125 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 126 }, { 127 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 128 .ddr_base = 16ULL * 1024ULL * 1024ULL, 129 .ddr_limit = 17ULL * 1024ULL * 1024ULL, 130 .ddr_dest_fabid = 0, 131 .ddr_sock_ileave_bits = 0, 132 .ddr_die_ileave_bits = 0, 133 .ddr_addr_start = 9, 134 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 135 }, { 136 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 137 .ddr_base = 18ULL * 1024ULL * 1024ULL, 138 .ddr_limit = 19ULL * 1024ULL * 1024ULL, 139 .ddr_dest_fabid = 0, 140 .ddr_sock_ileave_bits = 0, 141 .ddr_die_ileave_bits = 0, 142 .ddr_addr_start = 9, 143 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 144 .ddr_remap_ent = 3 145 } }, 146 } } 147 }; 148 149 /* 150 * This UMC contains a weird relationship between its rule, TOM and the actual 151 * DRAM hole base. This creates an inconsistency that should underflow. This is 152 * honestly a bit odd to actually try to find in the wild. The fact that TOM is 153 * much greater than the hole base is key. This requires DFv4 for subtracting 154 * the base. 155 */ 156 static const zen_umc_t zen_umc_hole_underflow = { 157 .umc_tom = 3ULL * 1024ULL * 1024ULL * 1024ULL, 158 .umc_tom2 = 2ULL * 1024ULL * 1024ULL * 1024ULL * 1024ULL, 159 .umc_df_rev = DF_REV_4, 160 .umc_decomp = { 161 .dfd_sock_mask = 0x01, 162 .dfd_die_mask = 0x00, 163 .dfd_node_mask = 0x20, 164 .dfd_comp_mask = 0x1f, 165 .dfd_sock_shift = 0, 166 .dfd_die_shift = 0, 167 .dfd_node_shift = 5, 168 .dfd_comp_shift = 0 169 }, 170 .umc_ndfs = 1, 171 .umc_dfs = { { 172 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 173 .zud_dfno = 0, 174 .zud_dram_nrules = 2, 175 .zud_hole_base = 0x0, 176 .zud_rules = { { 177 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 178 .ddr_base = 1ULL * 1024ULL * 1024ULL, 179 .ddr_limit = 8ULL * 1024ULL * 1024ULL * 1024ULL, 180 .ddr_dest_fabid = 0, 181 .ddr_sock_ileave_bits = 0, 182 .ddr_die_ileave_bits = 0, 183 .ddr_addr_start = 9, 184 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 185 } } 186 } }, 187 }; 188 189 /* 190 * This is a variant of the previous one, but it takes place when normalization 191 * occurs. The biggest gotcha there is that for DFv3 the base isn't subtracted 192 * initially for interleaving, only when normalizing. 193 */ 194 static const zen_umc_t zen_umc_norm_underflow = { 195 .umc_tom = 3ULL * 1024ULL * 1024ULL * 1024ULL, 196 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 197 .umc_df_rev = DF_REV_3, 198 .umc_decomp = { 199 .dfd_sock_mask = 0x01, 200 .dfd_die_mask = 0x00, 201 .dfd_node_mask = 0x20, 202 .dfd_comp_mask = 0x1f, 203 .dfd_sock_shift = 0, 204 .dfd_die_shift = 0, 205 .dfd_node_shift = 5, 206 .dfd_comp_shift = 0 207 }, 208 .umc_ndfs = 1, 209 .umc_dfs = { { 210 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 211 .zud_dfno = 0, 212 .zud_dram_nrules = 2, 213 .zud_nchan = 1, 214 .zud_hole_base = 0xc0000000, 215 .zud_rules = { { 216 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 217 .ddr_base = 4ULL * 1024ULL * 1024ULL * 1024ULL, 218 .ddr_limit = 8ULL * 1024ULL * 1024ULL * 1024ULL, 219 .ddr_dest_fabid = 0, 220 .ddr_sock_ileave_bits = 0, 221 .ddr_die_ileave_bits = 0, 222 .ddr_addr_start = 9, 223 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 224 } }, 225 .zud_chan = { { 226 .chan_flags = UMC_CHAN_F_ECC_EN, 227 .chan_fabid = 0, 228 .chan_instid = 0, 229 .chan_logid = 0, 230 .chan_nrules = 1, 231 .chan_type = UMC_DIMM_T_DDR4, 232 .chan_rules = { { 233 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 234 .ddr_base = 4ULL * 1024ULL * 1024ULL * 1024ULL, 235 .ddr_limit = 8ULL * 1024ULL * 1024ULL * 1024ULL, 236 .ddr_dest_fabid = 0, 237 .ddr_sock_ileave_bits = 0, 238 .ddr_die_ileave_bits = 0, 239 .ddr_addr_start = 9, 240 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 241 } }, 242 .chan_dimms = { { 243 .ud_flags = UMC_DIMM_F_VALID, 244 .ud_width = UMC_DIMM_W_X4, 245 .ud_kind = UMC_DIMM_K_RDIMM, 246 .ud_dimmno = 0, 247 .ud_cs = { { 248 .ucs_flags = UMC_CS_F_DECODE_EN, 249 .ucs_base = { 250 .udb_base = 0, 251 .udb_valid = B_TRUE 252 }, 253 .ucs_base_mask = 0x3ffffffff, 254 .ucs_nbanks = 0x4, 255 .ucs_ncol = 0xa, 256 .ucs_nrow_lo = 0x11, 257 .ucs_nbank_groups = 0x2, 258 .ucs_row_hi_bit = 0x18, 259 .ucs_row_low_bit = 0x11, 260 .ucs_bank_bits = { 0xf, 0x10, 0xd, 261 0xe }, 262 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 263 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 264 } } 265 } }, 266 } } 267 } } 268 }; 269 270 /* 271 * This DF is designed to capture bad remap entry pointers and remap entries 272 * with bad components. 273 */ 274 static const zen_umc_t zen_umc_remap_errs = { 275 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 276 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 277 .umc_df_rev = DF_REV_3, 278 .umc_decomp = { 279 .dfd_sock_mask = 0x01, 280 .dfd_die_mask = 0x00, 281 .dfd_node_mask = 0x20, 282 .dfd_comp_mask = 0x1f, 283 .dfd_sock_shift = 0, 284 .dfd_die_shift = 0, 285 .dfd_node_shift = 5, 286 .dfd_comp_shift = 0 287 }, 288 .umc_ndfs = 1, 289 .umc_dfs = { { 290 .zud_dfno = 0, 291 .zud_dram_nrules = 2, 292 .zud_nchan = 4, 293 .zud_cs_nremap = 2, 294 .zud_hole_base = 0, 295 .zud_rules = { { 296 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN | 297 DF_DRAM_F_REMAP_SOCK, 298 .ddr_base = 0, 299 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 1024ULL, 300 .ddr_dest_fabid = 0x1f, 301 .ddr_sock_ileave_bits = 0, 302 .ddr_die_ileave_bits = 0, 303 .ddr_addr_start = 12, 304 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH, 305 }, { 306 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 307 .ddr_base = 32ULL * 1024ULL * 1024ULL * 1024ULL, 308 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 309 .ddr_dest_fabid = 0, 310 .ddr_sock_ileave_bits = 0, 311 .ddr_die_ileave_bits = 0, 312 .ddr_addr_start = 12, 313 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH, 314 .ddr_remap_ent = 1 315 } }, 316 .zud_remap = { { 317 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 318 .csr_remaps = { 0x0 } 319 }, { 320 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 321 .csr_remaps = { 0x21 } 322 } } 323 } } 324 }; 325 326 /* 327 * This umc is used to cover the cases where: 328 * o There is no match to the fabric ID 329 * o The UMC in question doesn't have rules for our PA 330 * o Normalization underflow 331 * o Failure to match a chip-select 332 */ 333 static const zen_umc_t zen_umc_fab_errs = { 334 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 335 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 336 .umc_df_rev = DF_REV_3, 337 .umc_decomp = { 338 .dfd_sock_mask = 0x01, 339 .dfd_die_mask = 0x00, 340 .dfd_node_mask = 0x20, 341 .dfd_comp_mask = 0x1f, 342 .dfd_sock_shift = 0, 343 .dfd_die_shift = 0, 344 .dfd_node_shift = 5, 345 .dfd_comp_shift = 0 346 }, 347 .umc_ndfs = 1, 348 .umc_dfs = { { 349 .zud_dfno = 0, 350 .zud_dram_nrules = 4, 351 .zud_nchan = 2, 352 .zud_cs_nremap = 0, 353 .zud_hole_base = 0, 354 .zud_rules = { { 355 .ddr_flags = DF_DRAM_F_VALID, 356 .ddr_base = 0, 357 .ddr_limit = 1ULL * 1024ULL * 1024ULL * 1024ULL, 358 .ddr_dest_fabid = 0x22, 359 .ddr_sock_ileave_bits = 0, 360 .ddr_die_ileave_bits = 0, 361 .ddr_addr_start = 9, 362 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 363 }, { 364 .ddr_flags = DF_DRAM_F_VALID, 365 .ddr_base = 2ULL * 1024ULL * 1024ULL * 1024ULL, 366 .ddr_limit = 3ULL * 1024ULL * 1024ULL * 1024ULL, 367 .ddr_dest_fabid = 0, 368 .ddr_sock_ileave_bits = 0, 369 .ddr_die_ileave_bits = 0, 370 .ddr_addr_start = 9, 371 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 372 }, { 373 .ddr_flags = DF_DRAM_F_VALID, 374 .ddr_base = 4ULL * 1024ULL * 1024ULL * 1024ULL, 375 .ddr_limit = 5ULL * 1024ULL * 1024ULL * 1024ULL, 376 .ddr_dest_fabid = 0x1, 377 .ddr_sock_ileave_bits = 0, 378 .ddr_die_ileave_bits = 0, 379 .ddr_addr_start = 9, 380 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 381 } }, 382 .zud_chan = { { 383 .chan_flags = UMC_CHAN_F_ECC_EN, 384 .chan_fabid = 0, 385 .chan_instid = 0, 386 .chan_logid = 0, 387 .chan_nrules = 1, 388 .chan_type = UMC_DIMM_T_DDR4, 389 .chan_rules = { { 390 .ddr_flags = DF_DRAM_F_VALID, 391 .ddr_base = 32ULL * 1024ULL * 1024ULL * 392 1024ULL, 393 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 394 1024ULL, 395 .ddr_dest_fabid = 0, 396 .ddr_sock_ileave_bits = 0, 397 .ddr_die_ileave_bits = 0, 398 .ddr_addr_start = 9, 399 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 400 } } 401 }, { 402 .chan_flags = UMC_CHAN_F_ECC_EN, 403 .chan_fabid = 1, 404 .chan_instid = 1, 405 .chan_logid = 1, 406 .chan_nrules = 1, 407 .chan_type = UMC_DIMM_T_DDR4, 408 .chan_rules = { { 409 .ddr_flags = DF_DRAM_F_VALID, 410 .ddr_base = 0, 411 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 412 1024ULL, 413 .ddr_dest_fabid = 0, 414 .ddr_sock_ileave_bits = 0, 415 .ddr_die_ileave_bits = 0, 416 .ddr_addr_start = 9, 417 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 418 } }, 419 .chan_dimms = { { 420 .ud_flags = UMC_DIMM_F_VALID, 421 .ud_width = UMC_DIMM_W_X4, 422 .ud_kind = UMC_DIMM_K_RDIMM, 423 .ud_dimmno = 0, 424 .ud_cs = { { 425 .ucs_flags = UMC_CS_F_DECODE_EN, 426 .ucs_base = { 427 .udb_base = 0x400000000, 428 .udb_valid = B_TRUE 429 }, 430 .ucs_base_mask = 0x3ffffffff, 431 .ucs_nbanks = 0x4, 432 .ucs_ncol = 0xa, 433 .ucs_nrow_lo = 0x11, 434 .ucs_nbank_groups = 0x2, 435 .ucs_row_hi_bit = 0x18, 436 .ucs_row_low_bit = 0x11, 437 .ucs_bank_bits = { 0xf, 0x10, 0xd, 438 0xe }, 439 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 440 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 441 } } 442 } }, 443 } } 444 } } 445 }; 446 447 const umc_decode_test_t zen_umc_test_errors[] = { { 448 .udt_desc = "Memory beyond TOM2 doesn't decode (0)", 449 .udt_umc = &zen_umc_bad_df, 450 .udt_pa = 0x20000000000, 451 .udt_pass = B_FALSE, 452 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 453 }, { 454 .udt_desc = "Memory beyond TOM2 doesn't decode (1)", 455 .udt_umc = &zen_umc_bad_df, 456 .udt_pa = 0x2123456789a, 457 .udt_pass = B_FALSE, 458 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 459 }, { 460 .udt_desc = "Memory in 1 TiB-12 GiB hole doesn't decode (0)", 461 .udt_umc = &zen_umc_bad_df, 462 .udt_pa = 0xfd00000000, 463 .udt_pass = B_FALSE, 464 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 465 }, { 466 .udt_desc = "Memory in 1 TiB-12 GiB hole doesn't decode (1)", 467 .udt_umc = &zen_umc_bad_df, 468 .udt_pa = 0xfd00000001, 469 .udt_pass = B_FALSE, 470 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 471 }, { 472 .udt_desc = "Memory in 1 TiB-12 GiB hole doesn't decode (2)", 473 .udt_umc = &zen_umc_bad_df, 474 .udt_pa = 0xffffffffff, 475 .udt_pass = B_FALSE, 476 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 477 }, { 478 .udt_desc = "No valid DF rule (0)", 479 .udt_umc = &zen_umc_bad_df, 480 .udt_pa = 0x1ffffffffff, 481 .udt_pass = B_FALSE, 482 .udt_fail = ZEN_UMC_DECODE_F_NO_DF_RULE 483 }, { 484 .udt_desc = "No valid DF rule (1)", 485 .udt_umc = &zen_umc_bad_df, 486 .udt_pa = 0xfcffffffff, 487 .udt_pass = B_FALSE, 488 .udt_fail = ZEN_UMC_DECODE_F_NO_DF_RULE 489 }, { 490 .udt_desc = "No valid DF rule (2)", 491 .udt_umc = &zen_umc_bad_df, 492 .udt_pa = 0x123456, 493 .udt_pass = B_FALSE, 494 .udt_fail = ZEN_UMC_DECODE_F_NO_DF_RULE 495 }, { 496 .udt_desc = "Bad COD hash interleave - socket", 497 .udt_umc = &zen_umc_bad_df, 498 .udt_pa = 0x0, 499 .udt_pass = B_FALSE, 500 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 501 }, { 502 .udt_desc = "Bad COD hash interleave - die", 503 .udt_umc = &zen_umc_bad_df, 504 .udt_pa = 0x200000, 505 .udt_pass = B_FALSE, 506 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 507 }, { 508 .udt_desc = "Bad COD 6ch hash interleave - socket", 509 .udt_umc = &zen_umc_bad_df, 510 .udt_pa = 0x400000, 511 .udt_pass = B_FALSE, 512 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 513 }, { 514 .udt_desc = "Bad COD 6ch hash interleave - die", 515 .udt_umc = &zen_umc_bad_df, 516 .udt_pa = 0x600000, 517 .udt_pass = B_FALSE, 518 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 519 }, { 520 .udt_desc = "Unknown interleave", 521 .udt_umc = &zen_umc_bad_df, 522 .udt_pa = 0x800000, 523 .udt_pass = B_FALSE, 524 .udt_fail = ZEN_UMC_DECODE_F_CHAN_ILEAVE_NOTSUP, 525 }, { 526 .udt_desc = "Bad NPS hash interleave - die", 527 .udt_umc = &zen_umc_bad_df, 528 .udt_pa = 0xc00000, 529 .udt_pass = B_FALSE, 530 .udt_fail = ZEN_UMC_DECODE_F_NPS_BAD_ILEAVE 531 }, { 532 .udt_desc = "Bad NPS NP2 hash interleave - die", 533 .udt_umc = &zen_umc_bad_df, 534 .udt_pa = 0xa00000, 535 .udt_pass = B_FALSE, 536 .udt_fail = ZEN_UMC_DECODE_F_NPS_BAD_ILEAVE 537 }, { 538 .udt_desc = "Bad Remap Set - DFv3", 539 .udt_umc = &zen_umc_bad_df, 540 .udt_pa = 0xe00000, 541 .udt_pass = B_FALSE, 542 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_SET 543 }, { 544 .udt_desc = "Bad Remap Set - DFv4 (0)", 545 .udt_umc = &zen_umc_bad_df, 546 .udt_pa = 0x1000000, 547 .udt_pass = B_FALSE, 548 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_SET 549 }, { 550 .udt_desc = "Bad Remap Set - DFv4 (1)", 551 .udt_umc = &zen_umc_bad_df, 552 .udt_pa = 0x1200000, 553 .udt_pass = B_FALSE, 554 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_SET 555 }, { 556 .udt_desc = "Interleave address underflow", 557 .udt_umc = &zen_umc_hole_underflow, 558 .udt_pa = 0x100000000, 559 .udt_pass = B_FALSE, 560 .udt_fail = ZEN_UMC_DECODE_F_ILEAVE_UNDERFLOW 561 }, { 562 .udt_desc = "Normal address underflow", 563 .udt_umc = &zen_umc_norm_underflow, 564 .udt_pa = 0x100000000, 565 .udt_pass = B_FALSE, 566 .udt_fail = ZEN_UMC_DECODE_F_CALC_NORM_UNDERFLOW 567 }, { 568 .udt_desc = "Non-existent remap entry", 569 .udt_umc = &zen_umc_remap_errs, 570 .udt_pa = 0x0, 571 .udt_pass = B_FALSE, 572 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_ENTRY 573 }, { 574 .udt_desc = "Remap entry has bogus ID", 575 .udt_umc = &zen_umc_remap_errs, 576 .udt_pa = 0x8f0000000, 577 .udt_pass = B_FALSE, 578 .udt_fail = ZEN_UMC_DECODE_F_REMAP_HAS_BAD_COMP 579 }, { 580 .udt_desc = "Target fabric ID doesn't exist", 581 .udt_umc = &zen_umc_fab_errs, 582 .udt_pa = 0x12345, 583 .udt_pass = B_FALSE, 584 .udt_fail = ZEN_UMC_DECODE_F_CANNOT_MAP_FABID 585 }, { 586 .udt_desc = "UMC doesn't have DRAM rule", 587 .udt_umc = &zen_umc_fab_errs, 588 .udt_pa = 0x87654321, 589 .udt_pass = B_FALSE, 590 .udt_fail = ZEN_UMC_DECODE_F_UMC_DOESNT_HAVE_PA 591 }, { 592 .udt_desc = "No matching chip-select", 593 .udt_umc = &zen_umc_fab_errs, 594 .udt_pa = 0x101234567, 595 .udt_pass = B_FALSE, 596 .udt_fail = ZEN_UMC_DECODE_F_NO_CS_BASE_MATCH 597 }, { 598 .udt_desc = NULL 599 } }; 600