1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 /* 17 * Here we try to test a few variants of the Zen 3 COD based hashing, including 18 * our favorite 6 channel. These all use DFv3 and 1 DPC 16 GiB channels without 19 * any internal hashing (that is tested elsewhere). 20 */ 21 22 #include "zen_umc_test.h" 23 24 /* 25 * This is a basic 4-channel hash, sending us out to one of four locations. This 26 * enables hashing in all three regions because 6 channel variant does not seem 27 * to use them. 28 */ 29 static const zen_umc_t zen_umc_cod_4ch = { 30 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 31 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 32 .umc_df_rev = DF_REV_3, 33 .umc_decomp = { 34 .dfd_sock_mask = 0x01, 35 .dfd_die_mask = 0x00, 36 .dfd_node_mask = 0x20, 37 .dfd_comp_mask = 0x1f, 38 .dfd_sock_shift = 0, 39 .dfd_die_shift = 0, 40 .dfd_node_shift = 5, 41 .dfd_comp_shift = 0 42 }, 43 .umc_ndfs = 1, 44 .umc_dfs = { { 45 .zud_dfno = 0, 46 .zud_dram_nrules = 1, 47 .zud_nchan = 4, 48 .zud_cs_nremap = 0, 49 .zud_hole_base = 0, 50 .zud_rules = { { 51 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 | 52 DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32, 53 .ddr_base = 0, 54 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 55 .ddr_dest_fabid = 0, 56 .ddr_sock_ileave_bits = 0, 57 .ddr_die_ileave_bits = 0, 58 .ddr_addr_start = 9, 59 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 60 } }, 61 .zud_chan = { { 62 .chan_flags = UMC_CHAN_F_ECC_EN, 63 .chan_fabid = 0, 64 .chan_instid = 0, 65 .chan_logid = 0, 66 .chan_nrules = 1, 67 .chan_type = UMC_DIMM_T_DDR4, 68 .chan_rules = { { 69 .ddr_flags = DF_DRAM_F_VALID | 70 DF_DRAM_F_HASH_16_18 | 71 DF_DRAM_F_HASH_21_23 | 72 DF_DRAM_F_HASH_30_32, 73 .ddr_base = 0, 74 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 75 1024ULL, 76 .ddr_dest_fabid = 0, 77 .ddr_sock_ileave_bits = 0, 78 .ddr_die_ileave_bits = 0, 79 .ddr_addr_start = 9, 80 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 81 } }, 82 .chan_dimms = { { 83 .ud_flags = UMC_DIMM_F_VALID, 84 .ud_width = UMC_DIMM_W_X4, 85 .ud_kind = UMC_DIMM_K_RDIMM, 86 .ud_dimmno = 0, 87 .ud_cs = { { 88 .ucs_flags = UMC_CS_F_DECODE_EN, 89 .ucs_base = { 90 .udb_base = 0, 91 .udb_valid = B_TRUE 92 }, 93 .ucs_base_mask = 0x3ffffffff, 94 .ucs_nbanks = 0x4, 95 .ucs_ncol = 0xa, 96 .ucs_nrow_lo = 0x11, 97 .ucs_nbank_groups = 0x2, 98 .ucs_row_hi_bit = 0x18, 99 .ucs_row_low_bit = 0x11, 100 .ucs_bank_bits = { 0xf, 0x10, 0xd, 101 0xe }, 102 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 103 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 104 } } 105 } }, 106 }, { 107 .chan_flags = UMC_CHAN_F_ECC_EN, 108 .chan_fabid = 1, 109 .chan_instid = 1, 110 .chan_logid = 1, 111 .chan_nrules = 1, 112 .chan_rules = { { 113 .ddr_flags = DF_DRAM_F_VALID | 114 DF_DRAM_F_HASH_16_18 | 115 DF_DRAM_F_HASH_21_23 | 116 DF_DRAM_F_HASH_30_32, 117 .ddr_base = 0, 118 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 119 1024ULL, 120 .ddr_dest_fabid = 0, 121 .ddr_sock_ileave_bits = 0, 122 .ddr_die_ileave_bits = 0, 123 .ddr_addr_start = 9, 124 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 125 } }, 126 .chan_dimms = { { 127 .ud_flags = UMC_DIMM_F_VALID, 128 .ud_width = UMC_DIMM_W_X4, 129 .ud_kind = UMC_DIMM_K_RDIMM, 130 .ud_dimmno = 0, 131 .ud_cs = { { 132 .ucs_flags = UMC_CS_F_DECODE_EN, 133 .ucs_base = { 134 .udb_base = 0, 135 .udb_valid = B_TRUE 136 }, 137 .ucs_base_mask = 0x3ffffffff, 138 .ucs_nbanks = 0x4, 139 .ucs_ncol = 0xa, 140 .ucs_nrow_lo = 0x11, 141 .ucs_nbank_groups = 0x2, 142 .ucs_row_hi_bit = 0x18, 143 .ucs_row_low_bit = 0x11, 144 .ucs_bank_bits = { 0xf, 0x10, 0xd, 145 0xe }, 146 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 147 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 148 } } 149 } }, 150 }, { 151 .chan_flags = UMC_CHAN_F_ECC_EN, 152 .chan_fabid = 2, 153 .chan_instid = 2, 154 .chan_logid = 2, 155 .chan_nrules = 1, 156 .chan_type = UMC_DIMM_T_DDR4, 157 .chan_rules = { { 158 .ddr_flags = DF_DRAM_F_VALID | 159 DF_DRAM_F_HASH_16_18 | 160 DF_DRAM_F_HASH_21_23 | 161 DF_DRAM_F_HASH_30_32, 162 .ddr_base = 0, 163 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 164 1024ULL, 165 .ddr_dest_fabid = 0, 166 .ddr_sock_ileave_bits = 0, 167 .ddr_die_ileave_bits = 0, 168 .ddr_addr_start = 9, 169 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 170 } }, 171 .chan_dimms = { { 172 .ud_flags = UMC_DIMM_F_VALID, 173 .ud_width = UMC_DIMM_W_X4, 174 .ud_kind = UMC_DIMM_K_RDIMM, 175 .ud_dimmno = 0, 176 .ud_cs = { { 177 .ucs_flags = UMC_CS_F_DECODE_EN, 178 .ucs_base = { 179 .udb_base = 0, 180 .udb_valid = B_TRUE 181 }, 182 .ucs_base_mask = 0x3ffffffff, 183 .ucs_nbanks = 0x4, 184 .ucs_ncol = 0xa, 185 .ucs_nrow_lo = 0x11, 186 .ucs_nbank_groups = 0x2, 187 .ucs_row_hi_bit = 0x18, 188 .ucs_row_low_bit = 0x11, 189 .ucs_bank_bits = { 0xf, 0x10, 0xd, 190 0xe }, 191 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 192 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 193 } } 194 } }, 195 }, { 196 .chan_flags = UMC_CHAN_F_ECC_EN, 197 .chan_fabid = 3, 198 .chan_instid = 3, 199 .chan_logid = 3, 200 .chan_nrules = 1, 201 .chan_type = UMC_DIMM_T_DDR4, 202 .chan_rules = { { 203 .ddr_flags = DF_DRAM_F_VALID | 204 DF_DRAM_F_HASH_16_18 | 205 DF_DRAM_F_HASH_21_23 | 206 DF_DRAM_F_HASH_30_32, 207 .ddr_base = 0, 208 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 209 1024ULL, 210 .ddr_dest_fabid = 0, 211 .ddr_sock_ileave_bits = 0, 212 .ddr_die_ileave_bits = 0, 213 .ddr_addr_start = 9, 214 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH 215 } }, 216 .chan_dimms = { { 217 .ud_flags = UMC_DIMM_F_VALID, 218 .ud_width = UMC_DIMM_W_X4, 219 .ud_kind = UMC_DIMM_K_RDIMM, 220 .ud_dimmno = 0, 221 .ud_cs = { { 222 .ucs_flags = UMC_CS_F_DECODE_EN, 223 .ucs_base = { 224 .udb_base = 0, 225 .udb_valid = B_TRUE 226 }, 227 .ucs_base_mask = 0x3ffffffff, 228 .ucs_nbanks = 0x4, 229 .ucs_ncol = 0xa, 230 .ucs_nrow_lo = 0x11, 231 .ucs_nbank_groups = 0x2, 232 .ucs_row_hi_bit = 0x18, 233 .ucs_row_low_bit = 0x11, 234 .ucs_bank_bits = { 0xf, 0x10, 0xd, 235 0xe }, 236 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 237 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 238 } } 239 } }, 240 } } 241 } } 242 }; 243 244 static const zen_umc_t zen_umc_cod_6ch = { 245 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 246 .umc_tom2 = 96ULL * 1024ULL * 1024ULL * 1024ULL, 247 .umc_df_rev = DF_REV_3, 248 .umc_decomp = { 249 .dfd_sock_mask = 0x01, 250 .dfd_die_mask = 0x00, 251 .dfd_node_mask = 0x20, 252 .dfd_comp_mask = 0x1f, 253 .dfd_sock_shift = 0, 254 .dfd_die_shift = 0, 255 .dfd_node_shift = 5, 256 .dfd_comp_shift = 0 257 }, 258 .umc_ndfs = 1, 259 .umc_dfs = { { 260 .zud_dfno = 0, 261 .zud_dram_nrules = 1, 262 .zud_nchan = 6, 263 .zud_cs_nremap = 0, 264 .zud_hole_base = 0, 265 .zud_rules = { { 266 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_21_23 | 267 DF_DRAM_F_HASH_30_32, 268 .ddr_base = 0, 269 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL, 270 .ddr_dest_fabid = 0, 271 .ddr_sock_ileave_bits = 0, 272 .ddr_die_ileave_bits = 0, 273 .ddr_addr_start = 12, 274 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 275 } }, 276 .zud_chan = { { 277 .chan_flags = UMC_CHAN_F_ECC_EN, 278 .chan_fabid = 0, 279 .chan_instid = 0, 280 .chan_logid = 0, 281 .chan_nrules = 1, 282 .chan_type = UMC_DIMM_T_DDR4, 283 .chan_np2_space0 = 21, 284 .chan_rules = { { 285 .ddr_flags = DF_DRAM_F_VALID | 286 DF_DRAM_F_HASH_21_23 | 287 DF_DRAM_F_HASH_30_32, 288 .ddr_base = 0, 289 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 290 1024ULL, 291 .ddr_dest_fabid = 0, 292 .ddr_sock_ileave_bits = 0, 293 .ddr_die_ileave_bits = 0, 294 .ddr_addr_start = 12, 295 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 296 } }, 297 .chan_dimms = { { 298 .ud_flags = UMC_DIMM_F_VALID, 299 .ud_width = UMC_DIMM_W_X4, 300 .ud_kind = UMC_DIMM_K_RDIMM, 301 .ud_dimmno = 0, 302 .ud_cs = { { 303 .ucs_flags = UMC_CS_F_DECODE_EN, 304 .ucs_base = { 305 .udb_base = 0, 306 .udb_valid = B_TRUE 307 }, 308 .ucs_base_mask = 0x3ffffffff, 309 .ucs_nbanks = 0x4, 310 .ucs_ncol = 0xa, 311 .ucs_nrow_lo = 0x11, 312 .ucs_nbank_groups = 0x2, 313 .ucs_row_hi_bit = 0x18, 314 .ucs_row_low_bit = 0x11, 315 .ucs_bank_bits = { 0xf, 0x10, 0xd, 316 0xe }, 317 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 318 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 319 } } 320 } }, 321 }, { 322 .chan_flags = UMC_CHAN_F_ECC_EN, 323 .chan_fabid = 1, 324 .chan_instid = 1, 325 .chan_logid = 1, 326 .chan_nrules = 1, 327 .chan_np2_space0 = 21, 328 .chan_type = UMC_DIMM_T_DDR4, 329 .chan_rules = { { 330 .ddr_flags = DF_DRAM_F_VALID | 331 DF_DRAM_F_HASH_21_23 | 332 DF_DRAM_F_HASH_30_32, 333 .ddr_base = 0, 334 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 335 1024ULL, 336 .ddr_dest_fabid = 0, 337 .ddr_sock_ileave_bits = 0, 338 .ddr_die_ileave_bits = 0, 339 .ddr_addr_start = 12, 340 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 341 } }, 342 .chan_dimms = { { 343 .ud_flags = UMC_DIMM_F_VALID, 344 .ud_width = UMC_DIMM_W_X4, 345 .ud_kind = UMC_DIMM_K_RDIMM, 346 .ud_dimmno = 0, 347 .ud_cs = { { 348 .ucs_flags = UMC_CS_F_DECODE_EN, 349 .ucs_base = { 350 .udb_base = 0, 351 .udb_valid = B_TRUE 352 }, 353 .ucs_base_mask = 0x3ffffffff, 354 .ucs_nbanks = 0x4, 355 .ucs_ncol = 0xa, 356 .ucs_nrow_lo = 0x11, 357 .ucs_nbank_groups = 0x2, 358 .ucs_row_hi_bit = 0x18, 359 .ucs_row_low_bit = 0x11, 360 .ucs_bank_bits = { 0xf, 0x10, 0xd, 361 0xe }, 362 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 363 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 364 } } 365 } }, 366 }, { 367 .chan_flags = UMC_CHAN_F_ECC_EN, 368 .chan_fabid = 2, 369 .chan_instid = 2, 370 .chan_logid = 2, 371 .chan_nrules = 1, 372 .chan_np2_space0 = 21, 373 .chan_type = UMC_DIMM_T_DDR4, 374 .chan_rules = { { 375 .ddr_flags = DF_DRAM_F_VALID | 376 DF_DRAM_F_HASH_21_23 | 377 DF_DRAM_F_HASH_30_32, 378 .ddr_base = 0, 379 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 380 1024ULL, 381 .ddr_dest_fabid = 0, 382 .ddr_sock_ileave_bits = 0, 383 .ddr_die_ileave_bits = 0, 384 .ddr_addr_start = 12, 385 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 386 } }, 387 .chan_dimms = { { 388 .ud_flags = UMC_DIMM_F_VALID, 389 .ud_width = UMC_DIMM_W_X4, 390 .ud_kind = UMC_DIMM_K_RDIMM, 391 .ud_dimmno = 0, 392 .ud_cs = { { 393 .ucs_flags = UMC_CS_F_DECODE_EN, 394 .ucs_base = { 395 .udb_base = 0, 396 .udb_valid = B_TRUE 397 }, 398 .ucs_base_mask = 0x3ffffffff, 399 .ucs_nbanks = 0x4, 400 .ucs_ncol = 0xa, 401 .ucs_nrow_lo = 0x11, 402 .ucs_nbank_groups = 0x2, 403 .ucs_row_hi_bit = 0x18, 404 .ucs_row_low_bit = 0x11, 405 .ucs_bank_bits = { 0xf, 0x10, 0xd, 406 0xe }, 407 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 408 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 409 } } 410 } }, 411 }, { 412 .chan_flags = UMC_CHAN_F_ECC_EN, 413 .chan_fabid = 3, 414 .chan_instid = 3, 415 .chan_logid = 3, 416 .chan_nrules = 1, 417 .chan_np2_space0 = 21, 418 .chan_type = UMC_DIMM_T_DDR4, 419 .chan_rules = { { 420 .ddr_flags = DF_DRAM_F_VALID | 421 DF_DRAM_F_HASH_21_23 | 422 DF_DRAM_F_HASH_30_32, 423 .ddr_base = 0, 424 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 425 1024ULL, 426 .ddr_dest_fabid = 0, 427 .ddr_sock_ileave_bits = 0, 428 .ddr_die_ileave_bits = 0, 429 .ddr_addr_start = 12, 430 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 431 } }, 432 .chan_dimms = { { 433 .ud_flags = UMC_DIMM_F_VALID, 434 .ud_width = UMC_DIMM_W_X4, 435 .ud_kind = UMC_DIMM_K_RDIMM, 436 .ud_dimmno = 0, 437 .ud_cs = { { 438 .ucs_flags = UMC_CS_F_DECODE_EN, 439 .ucs_base = { 440 .udb_base = 0, 441 .udb_valid = B_TRUE 442 }, 443 .ucs_base_mask = 0x3ffffffff, 444 .ucs_nbanks = 0x4, 445 .ucs_ncol = 0xa, 446 .ucs_nrow_lo = 0x11, 447 .ucs_nbank_groups = 0x2, 448 .ucs_row_hi_bit = 0x18, 449 .ucs_row_low_bit = 0x11, 450 .ucs_bank_bits = { 0xf, 0x10, 0xd, 451 0xe }, 452 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 453 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 454 } } 455 } }, 456 }, { 457 .chan_flags = UMC_CHAN_F_ECC_EN, 458 .chan_fabid = 4, 459 .chan_instid = 4, 460 .chan_logid = 4, 461 .chan_nrules = 1, 462 .chan_np2_space0 = 21, 463 .chan_type = UMC_DIMM_T_DDR4, 464 .chan_rules = { { 465 .ddr_flags = DF_DRAM_F_VALID | 466 DF_DRAM_F_HASH_21_23 | 467 DF_DRAM_F_HASH_30_32, 468 .ddr_base = 0, 469 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 470 1024ULL, 471 .ddr_dest_fabid = 0, 472 .ddr_sock_ileave_bits = 0, 473 .ddr_die_ileave_bits = 0, 474 .ddr_addr_start = 12, 475 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 476 } }, 477 .chan_dimms = { { 478 .ud_flags = UMC_DIMM_F_VALID, 479 .ud_width = UMC_DIMM_W_X4, 480 .ud_kind = UMC_DIMM_K_RDIMM, 481 .ud_dimmno = 0, 482 .ud_cs = { { 483 .ucs_flags = UMC_CS_F_DECODE_EN, 484 .ucs_base = { 485 .udb_base = 0, 486 .udb_valid = B_TRUE 487 }, 488 .ucs_base_mask = 0x3ffffffff, 489 .ucs_nbanks = 0x4, 490 .ucs_ncol = 0xa, 491 .ucs_nrow_lo = 0x11, 492 .ucs_nbank_groups = 0x2, 493 .ucs_row_hi_bit = 0x18, 494 .ucs_row_low_bit = 0x11, 495 .ucs_bank_bits = { 0xf, 0x10, 0xd, 496 0xe }, 497 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 498 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 499 } } 500 } }, 501 }, { 502 .chan_flags = UMC_CHAN_F_ECC_EN, 503 .chan_fabid = 5, 504 .chan_instid = 5, 505 .chan_logid = 5, 506 .chan_nrules = 1, 507 .chan_np2_space0 = 21, 508 .chan_type = UMC_DIMM_T_DDR4, 509 .chan_rules = { { 510 .ddr_flags = DF_DRAM_F_VALID | 511 DF_DRAM_F_HASH_21_23 | 512 DF_DRAM_F_HASH_30_32, 513 .ddr_base = 0, 514 .ddr_limit = 96ULL * 1024ULL * 1024ULL * 515 1024ULL, 516 .ddr_dest_fabid = 0, 517 .ddr_sock_ileave_bits = 0, 518 .ddr_die_ileave_bits = 0, 519 .ddr_addr_start = 12, 520 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 521 } }, 522 .chan_dimms = { { 523 .ud_flags = UMC_DIMM_F_VALID, 524 .ud_width = UMC_DIMM_W_X4, 525 .ud_kind = UMC_DIMM_K_RDIMM, 526 .ud_dimmno = 0, 527 .ud_cs = { { 528 .ucs_flags = UMC_CS_F_DECODE_EN, 529 .ucs_base = { 530 .udb_base = 0, 531 .udb_valid = B_TRUE 532 }, 533 .ucs_base_mask = 0x3ffffffff, 534 .ucs_nbanks = 0x4, 535 .ucs_ncol = 0xa, 536 .ucs_nrow_lo = 0x11, 537 .ucs_nbank_groups = 0x2, 538 .ucs_row_hi_bit = 0x18, 539 .ucs_row_low_bit = 0x11, 540 .ucs_bank_bits = { 0xf, 0x10, 0xd, 541 0xe }, 542 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 543 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 544 } } 545 } }, 546 } } 547 } } 548 }; 549 550 const umc_decode_test_t zen_umc_test_cod[] = { { 551 .udt_desc = "COD 4ch (0)", 552 .udt_umc = &zen_umc_cod_4ch, 553 .udt_pa = 0x1ff, 554 .udt_pass = B_TRUE, 555 .udt_norm_addr = 0x1ff, 556 .udt_sock = 0, 557 .udt_die = 0, 558 .udt_comp = 0, 559 .udt_dimm_no = 0, 560 .udt_dimm_col = 0x3f, 561 .udt_dimm_row = 0, 562 .udt_dimm_bank = 0, 563 .udt_dimm_bank_group = 0, 564 .udt_dimm_subchan = UINT8_MAX, 565 .udt_dimm_rm = 0, 566 .udt_dimm_cs = 0 567 }, { 568 .udt_desc = "COD 4ch (1)", 569 .udt_umc = &zen_umc_cod_4ch, 570 .udt_pa = 0x3ff, 571 .udt_pass = B_TRUE, 572 .udt_norm_addr = 0x1ff, 573 .udt_sock = 0, 574 .udt_die = 0, 575 .udt_comp = 1, 576 .udt_dimm_no = 0, 577 .udt_dimm_col = 0x3f, 578 .udt_dimm_row = 0, 579 .udt_dimm_bank = 0, 580 .udt_dimm_bank_group = 0, 581 .udt_dimm_subchan = UINT8_MAX, 582 .udt_dimm_rm = 0, 583 .udt_dimm_cs = 0 584 }, { 585 .udt_desc = "COD 4ch (2)", 586 .udt_umc = &zen_umc_cod_4ch, 587 .udt_pa = 0x11ff, 588 .udt_pass = B_TRUE, 589 .udt_norm_addr = 0x1ff, 590 .udt_sock = 0, 591 .udt_die = 0, 592 .udt_comp = 2, 593 .udt_dimm_no = 0, 594 .udt_dimm_col = 0x3f, 595 .udt_dimm_row = 0, 596 .udt_dimm_bank = 0, 597 .udt_dimm_bank_group = 0, 598 .udt_dimm_subchan = UINT8_MAX, 599 .udt_dimm_rm = 0, 600 .udt_dimm_cs = 0 601 }, { 602 .udt_desc = "COD 4ch (3)", 603 .udt_umc = &zen_umc_cod_4ch, 604 .udt_pa = 0x13ff, 605 .udt_pass = B_TRUE, 606 .udt_norm_addr = 0x1ff, 607 .udt_sock = 0, 608 .udt_die = 0, 609 .udt_comp = 3, 610 .udt_dimm_no = 0, 611 .udt_dimm_col = 0x3f, 612 .udt_dimm_row = 0, 613 .udt_dimm_bank = 0, 614 .udt_dimm_bank_group = 0, 615 .udt_dimm_subchan = UINT8_MAX, 616 .udt_dimm_rm = 0, 617 .udt_dimm_cs = 0 618 }, { 619 .udt_desc = "COD 4ch (4)", 620 .udt_umc = &zen_umc_cod_4ch, 621 .udt_pa = 0x101ff, 622 .udt_pass = B_TRUE, 623 .udt_norm_addr = 0x41ff, 624 .udt_sock = 0, 625 .udt_die = 0, 626 .udt_comp = 1, 627 .udt_dimm_no = 0, 628 .udt_dimm_col = 0x3f, 629 .udt_dimm_row = 0, 630 .udt_dimm_bank = 2, 631 .udt_dimm_bank_group = 0, 632 .udt_dimm_subchan = UINT8_MAX, 633 .udt_dimm_rm = 0, 634 .udt_dimm_cs = 0 635 }, { 636 .udt_desc = "COD 4ch (5)", 637 .udt_umc = &zen_umc_cod_4ch, 638 .udt_pa = 0x103ff, 639 .udt_pass = B_TRUE, 640 .udt_norm_addr = 0x41ff, 641 .udt_sock = 0, 642 .udt_die = 0, 643 .udt_comp = 0, 644 .udt_dimm_no = 0, 645 .udt_dimm_col = 0x3f, 646 .udt_dimm_row = 0, 647 .udt_dimm_bank = 2, 648 .udt_dimm_bank_group = 0, 649 .udt_dimm_subchan = UINT8_MAX, 650 .udt_dimm_rm = 0, 651 .udt_dimm_cs = 0 652 }, { 653 .udt_desc = "COD 4ch (6)", 654 .udt_umc = &zen_umc_cod_4ch, 655 .udt_pa = 0x303ff, 656 .udt_pass = B_TRUE, 657 .udt_norm_addr = 0xc1ff, 658 .udt_sock = 0, 659 .udt_die = 0, 660 .udt_comp = 2, 661 .udt_dimm_no = 0, 662 .udt_dimm_col = 0x3f, 663 .udt_dimm_row = 0, 664 .udt_dimm_bank = 2, 665 .udt_dimm_bank_group = 1, 666 .udt_dimm_subchan = UINT8_MAX, 667 .udt_dimm_rm = 0, 668 .udt_dimm_cs = 0 669 }, { 670 .udt_desc = "COD 4ch (7)", 671 .udt_umc = &zen_umc_cod_4ch, 672 .udt_pa = 0x313ff, 673 .udt_pass = B_TRUE, 674 .udt_norm_addr = 0xc1ff, 675 .udt_sock = 0, 676 .udt_die = 0, 677 .udt_comp = 0, 678 .udt_dimm_no = 0, 679 .udt_dimm_col = 0x3f, 680 .udt_dimm_row = 0, 681 .udt_dimm_bank = 2, 682 .udt_dimm_bank_group = 1, 683 .udt_dimm_subchan = UINT8_MAX, 684 .udt_dimm_rm = 0, 685 .udt_dimm_cs = 0 686 }, { 687 .udt_desc = "COD 4ch (8)", 688 .udt_umc = &zen_umc_cod_4ch, 689 .udt_pa = 0x311ff, 690 .udt_pass = B_TRUE, 691 .udt_norm_addr = 0xc1ff, 692 .udt_sock = 0, 693 .udt_die = 0, 694 .udt_comp = 1, 695 .udt_dimm_no = 0, 696 .udt_dimm_col = 0x3f, 697 .udt_dimm_row = 0, 698 .udt_dimm_bank = 2, 699 .udt_dimm_bank_group = 1, 700 .udt_dimm_subchan = UINT8_MAX, 701 .udt_dimm_rm = 0, 702 .udt_dimm_cs = 0 703 }, { 704 .udt_desc = "COD 4ch (9)", 705 .udt_umc = &zen_umc_cod_4ch, 706 .udt_pa = 0x2311ff, 707 .udt_pass = B_TRUE, 708 .udt_norm_addr = 0x8c1ff, 709 .udt_sock = 0, 710 .udt_die = 0, 711 .udt_comp = 0, 712 .udt_dimm_no = 0, 713 .udt_dimm_col = 0x3f, 714 .udt_dimm_row = 0x4, 715 .udt_dimm_bank = 2, 716 .udt_dimm_bank_group = 1, 717 .udt_dimm_subchan = UINT8_MAX, 718 .udt_dimm_rm = 0, 719 .udt_dimm_cs = 0 720 }, { 721 .udt_desc = "COD 4ch (10)", 722 .udt_umc = &zen_umc_cod_4ch, 723 .udt_pa = 0x6311ff, 724 .udt_pass = B_TRUE, 725 .udt_norm_addr = 0x18c1ff, 726 .udt_sock = 0, 727 .udt_die = 0, 728 .udt_comp = 2, 729 .udt_dimm_no = 0, 730 .udt_dimm_col = 0x3f, 731 .udt_dimm_row = 0xc, 732 .udt_dimm_bank = 2, 733 .udt_dimm_bank_group = 1, 734 .udt_dimm_subchan = UINT8_MAX, 735 .udt_dimm_rm = 0, 736 .udt_dimm_cs = 0 737 }, { 738 .udt_desc = "COD 4ch (11)", 739 .udt_umc = &zen_umc_cod_4ch, 740 .udt_pa = 0x6313ff, 741 .udt_pass = B_TRUE, 742 .udt_norm_addr = 0x18c1ff, 743 .udt_sock = 0, 744 .udt_die = 0, 745 .udt_comp = 3, 746 .udt_dimm_no = 0, 747 .udt_dimm_col = 0x3f, 748 .udt_dimm_row = 0xc, 749 .udt_dimm_bank = 2, 750 .udt_dimm_bank_group = 1, 751 .udt_dimm_subchan = UINT8_MAX, 752 .udt_dimm_rm = 0, 753 .udt_dimm_cs = 0 754 }, { 755 .udt_desc = "COD 4ch (12)", 756 .udt_umc = &zen_umc_cod_4ch, 757 .udt_pa = 0x6303ff, 758 .udt_pass = B_TRUE, 759 .udt_norm_addr = 0x18c1ff, 760 .udt_sock = 0, 761 .udt_die = 0, 762 .udt_comp = 1, 763 .udt_dimm_no = 0, 764 .udt_dimm_col = 0x3f, 765 .udt_dimm_row = 0xc, 766 .udt_dimm_bank = 2, 767 .udt_dimm_bank_group = 1, 768 .udt_dimm_subchan = UINT8_MAX, 769 .udt_dimm_rm = 0, 770 .udt_dimm_cs = 0 771 }, { 772 .udt_desc = "COD 4ch (13)", 773 .udt_umc = &zen_umc_cod_4ch, 774 .udt_pa = 0x6301ff, 775 .udt_pass = B_TRUE, 776 .udt_norm_addr = 0x18c1ff, 777 .udt_sock = 0, 778 .udt_die = 0, 779 .udt_comp = 0, 780 .udt_dimm_no = 0, 781 .udt_dimm_col = 0x3f, 782 .udt_dimm_row = 0xc, 783 .udt_dimm_bank = 2, 784 .udt_dimm_bank_group = 1, 785 .udt_dimm_subchan = UINT8_MAX, 786 .udt_dimm_rm = 0, 787 .udt_dimm_cs = 0 788 }, { 789 .udt_desc = "COD 4ch (14)", 790 .udt_umc = &zen_umc_cod_4ch, 791 .udt_pa = 0x406301ff, 792 .udt_pass = B_TRUE, 793 .udt_norm_addr = 0x1018c1ff, 794 .udt_sock = 0, 795 .udt_die = 0, 796 .udt_comp = 1, 797 .udt_dimm_no = 0, 798 .udt_dimm_col = 0x3f, 799 .udt_dimm_row = 0x80c, 800 .udt_dimm_bank = 2, 801 .udt_dimm_bank_group = 1, 802 .udt_dimm_subchan = UINT8_MAX, 803 .udt_dimm_rm = 0, 804 .udt_dimm_cs = 0 805 }, { 806 .udt_desc = "COD 4ch (15)", 807 .udt_umc = &zen_umc_cod_4ch, 808 .udt_pa = 0x406303ff, 809 .udt_pass = B_TRUE, 810 .udt_norm_addr = 0x1018c1ff, 811 .udt_sock = 0, 812 .udt_die = 0, 813 .udt_comp = 0, 814 .udt_dimm_no = 0, 815 .udt_dimm_col = 0x3f, 816 .udt_dimm_row = 0x80c, 817 .udt_dimm_bank = 2, 818 .udt_dimm_bank_group = 1, 819 .udt_dimm_subchan = UINT8_MAX, 820 .udt_dimm_rm = 0, 821 .udt_dimm_cs = 0 822 }, { 823 .udt_desc = "COD 4ch (16)", 824 .udt_umc = &zen_umc_cod_4ch, 825 .udt_pa = 0x406311ff, 826 .udt_pass = B_TRUE, 827 .udt_norm_addr = 0x1018c1ff, 828 .udt_sock = 0, 829 .udt_die = 0, 830 .udt_comp = 3, 831 .udt_dimm_no = 0, 832 .udt_dimm_col = 0x3f, 833 .udt_dimm_row = 0x80c, 834 .udt_dimm_bank = 2, 835 .udt_dimm_bank_group = 1, 836 .udt_dimm_subchan = UINT8_MAX, 837 .udt_dimm_rm = 0, 838 .udt_dimm_cs = 0 839 }, { 840 .udt_desc = "COD 4ch (17)", 841 .udt_umc = &zen_umc_cod_4ch, 842 .udt_pa = 0x406313ff, 843 .udt_pass = B_TRUE, 844 .udt_norm_addr = 0x1018c1ff, 845 .udt_sock = 0, 846 .udt_die = 0, 847 .udt_comp = 2, 848 .udt_dimm_no = 0, 849 .udt_dimm_col = 0x3f, 850 .udt_dimm_row = 0x80c, 851 .udt_dimm_bank = 2, 852 .udt_dimm_bank_group = 1, 853 .udt_dimm_subchan = UINT8_MAX, 854 .udt_dimm_rm = 0, 855 .udt_dimm_cs = 0 856 }, { 857 .udt_desc = "COD 4ch (18)", 858 .udt_umc = &zen_umc_cod_4ch, 859 .udt_pa = 0xc06313ff, 860 .udt_pass = B_TRUE, 861 .udt_norm_addr = 0x3018c1ff, 862 .udt_sock = 0, 863 .udt_die = 0, 864 .udt_comp = 0, 865 .udt_dimm_no = 0, 866 .udt_dimm_col = 0x3f, 867 .udt_dimm_row = 0x180c, 868 .udt_dimm_bank = 2, 869 .udt_dimm_bank_group = 1, 870 .udt_dimm_subchan = UINT8_MAX, 871 .udt_dimm_rm = 0, 872 .udt_dimm_cs = 0 873 }, { 874 .udt_desc = "COD 4ch (19)", 875 .udt_umc = &zen_umc_cod_4ch, 876 .udt_pa = 0xc06311ff, 877 .udt_pass = B_TRUE, 878 .udt_norm_addr = 0x3018c1ff, 879 .udt_sock = 0, 880 .udt_die = 0, 881 .udt_comp = 1, 882 .udt_dimm_no = 0, 883 .udt_dimm_col = 0x3f, 884 .udt_dimm_row = 0x180c, 885 .udt_dimm_bank = 2, 886 .udt_dimm_bank_group = 1, 887 .udt_dimm_subchan = UINT8_MAX, 888 .udt_dimm_rm = 0, 889 .udt_dimm_cs = 0 890 }, { 891 .udt_desc = "COD 4ch (20)", 892 .udt_umc = &zen_umc_cod_4ch, 893 .udt_pa = 0xc06301ff, 894 .udt_pass = B_TRUE, 895 .udt_norm_addr = 0x3018c1ff, 896 .udt_sock = 0, 897 .udt_die = 0, 898 .udt_comp = 3, 899 .udt_dimm_no = 0, 900 .udt_dimm_col = 0x3f, 901 .udt_dimm_row = 0x180c, 902 .udt_dimm_bank = 2, 903 .udt_dimm_bank_group = 1, 904 .udt_dimm_subchan = UINT8_MAX, 905 .udt_dimm_rm = 0, 906 .udt_dimm_cs = 0 907 }, { 908 .udt_desc = "COD 4ch (21)", 909 .udt_umc = &zen_umc_cod_4ch, 910 .udt_pa = 0xc06303ff, 911 .udt_pass = B_TRUE, 912 .udt_norm_addr = 0x3018c1ff, 913 .udt_sock = 0, 914 .udt_die = 0, 915 .udt_comp = 2, 916 .udt_dimm_no = 0, 917 .udt_dimm_col = 0x3f, 918 .udt_dimm_row = 0x180c, 919 .udt_dimm_bank = 2, 920 .udt_dimm_bank_group = 1, 921 .udt_dimm_subchan = UINT8_MAX, 922 .udt_dimm_rm = 0, 923 .udt_dimm_cs = 0 924 }, { 925 .udt_desc = "COD 6ch (0)", 926 .udt_umc = &zen_umc_cod_6ch, 927 .udt_pa = 0x1ff, 928 .udt_pass = B_TRUE, 929 .udt_norm_addr = 0x1ff, 930 .udt_sock = 0, 931 .udt_die = 0, 932 .udt_comp = 0, 933 .udt_dimm_no = 0, 934 .udt_dimm_col = 0x3f, 935 .udt_dimm_row = 0, 936 .udt_dimm_bank = 0, 937 .udt_dimm_bank_group = 0, 938 .udt_dimm_subchan = UINT8_MAX, 939 .udt_dimm_rm = 0, 940 .udt_dimm_cs = 0 941 }, { 942 .udt_desc = "COD 6ch (1)", 943 .udt_umc = &zen_umc_cod_6ch, 944 .udt_pa = 0x11ff, 945 .udt_pass = B_TRUE, 946 .udt_norm_addr = 0x1ff, 947 .udt_sock = 0, 948 .udt_die = 0, 949 .udt_comp = 1, 950 .udt_dimm_no = 0, 951 .udt_dimm_col = 0x3f, 952 .udt_dimm_row = 0, 953 .udt_dimm_bank = 0, 954 .udt_dimm_bank_group = 0, 955 .udt_dimm_subchan = UINT8_MAX, 956 .udt_dimm_rm = 0, 957 .udt_dimm_cs = 0 958 }, { 959 .udt_desc = "COD 6ch (2)", 960 .udt_umc = &zen_umc_cod_6ch, 961 .udt_pa = 0x21ff, 962 .udt_pass = B_TRUE, 963 .udt_norm_addr = 0x1ff, 964 .udt_sock = 0, 965 .udt_die = 0, 966 .udt_comp = 2, 967 .udt_dimm_no = 0, 968 .udt_dimm_col = 0x3f, 969 .udt_dimm_row = 0, 970 .udt_dimm_bank = 0, 971 .udt_dimm_bank_group = 0, 972 .udt_dimm_subchan = UINT8_MAX, 973 .udt_dimm_rm = 0, 974 .udt_dimm_cs = 0 975 }, { 976 .udt_desc = "COD 6ch (3)", 977 .udt_umc = &zen_umc_cod_6ch, 978 .udt_pa = 0x31ff, 979 .udt_pass = B_TRUE, 980 .udt_norm_addr = 0x1ff, 981 .udt_sock = 0, 982 .udt_die = 0, 983 .udt_comp = 3, 984 .udt_dimm_no = 0, 985 .udt_dimm_col = 0x3f, 986 .udt_dimm_row = 0, 987 .udt_dimm_bank = 0, 988 .udt_dimm_bank_group = 0, 989 .udt_dimm_subchan = UINT8_MAX, 990 .udt_dimm_rm = 0, 991 .udt_dimm_cs = 0 992 }, { 993 .udt_desc = "COD 6ch (4)", 994 .udt_umc = &zen_umc_cod_6ch, 995 .udt_pa = 0x41ff, 996 .udt_pass = B_TRUE, 997 .udt_norm_addr = 0x1ff, 998 .udt_sock = 0, 999 .udt_die = 0, 1000 .udt_comp = 4, 1001 .udt_dimm_no = 0, 1002 .udt_dimm_col = 0x3f, 1003 .udt_dimm_row = 0, 1004 .udt_dimm_bank = 0, 1005 .udt_dimm_bank_group = 0, 1006 .udt_dimm_subchan = UINT8_MAX, 1007 .udt_dimm_rm = 0, 1008 .udt_dimm_cs = 0 1009 }, { 1010 .udt_desc = "COD 6ch (5)", 1011 .udt_umc = &zen_umc_cod_6ch, 1012 .udt_pa = 0x51ff, 1013 .udt_pass = B_TRUE, 1014 .udt_norm_addr = 0x1ff, 1015 .udt_sock = 0, 1016 .udt_die = 0, 1017 .udt_comp = 5, 1018 .udt_dimm_no = 0, 1019 .udt_dimm_col = 0x3f, 1020 .udt_dimm_row = 0, 1021 .udt_dimm_bank = 0, 1022 .udt_dimm_bank_group = 0, 1023 .udt_dimm_subchan = UINT8_MAX, 1024 .udt_dimm_rm = 0, 1025 .udt_dimm_cs = 0 1026 }, { 1027 .udt_desc = "COD 6ch (6)", 1028 .udt_umc = &zen_umc_cod_6ch, 1029 .udt_pa = 0x61ff, 1030 .udt_pass = B_TRUE, 1031 .udt_norm_addr = 0x3000001ff, 1032 .udt_sock = 0, 1033 .udt_die = 0, 1034 .udt_comp = 0, 1035 .udt_dimm_no = 0, 1036 .udt_dimm_col = 0x3f, 1037 .udt_dimm_row = 0x18000, 1038 .udt_dimm_bank = 0, 1039 .udt_dimm_bank_group = 0, 1040 .udt_dimm_subchan = UINT8_MAX, 1041 .udt_dimm_rm = 0, 1042 .udt_dimm_cs = 0 1043 }, { 1044 .udt_desc = "COD 6ch (7)", 1045 .udt_umc = &zen_umc_cod_6ch, 1046 .udt_pa = 0x71ff, 1047 .udt_pass = B_TRUE, 1048 .udt_norm_addr = 0x3000001ff, 1049 .udt_sock = 0, 1050 .udt_die = 0, 1051 .udt_comp = 1, 1052 .udt_dimm_no = 0, 1053 .udt_dimm_col = 0x3f, 1054 .udt_dimm_row = 0x18000, 1055 .udt_dimm_bank = 0, 1056 .udt_dimm_bank_group = 0, 1057 .udt_dimm_subchan = UINT8_MAX, 1058 .udt_dimm_rm = 0, 1059 .udt_dimm_cs = 0 1060 }, { 1061 .udt_desc = "COD 6ch (8)", 1062 .udt_umc = &zen_umc_cod_6ch, 1063 .udt_pa = 0x81ff, 1064 .udt_pass = B_TRUE, 1065 .udt_norm_addr = 0x11ff, 1066 .udt_sock = 0, 1067 .udt_die = 0, 1068 .udt_comp = 1, 1069 .udt_dimm_no = 0, 1070 .udt_dimm_col = 0x23f, 1071 .udt_dimm_row = 0, 1072 .udt_dimm_bank = 0, 1073 .udt_dimm_bank_group = 0, 1074 .udt_dimm_subchan = UINT8_MAX, 1075 .udt_dimm_rm = 0, 1076 .udt_dimm_cs = 0 1077 }, { 1078 .udt_desc = "COD 6ch (9)", 1079 .udt_umc = &zen_umc_cod_6ch, 1080 .udt_pa = 0x91ff, 1081 .udt_pass = B_TRUE, 1082 .udt_norm_addr = 0x11ff, 1083 .udt_sock = 0, 1084 .udt_die = 0, 1085 .udt_comp = 0, 1086 .udt_dimm_no = 0, 1087 .udt_dimm_col = 0x23f, 1088 .udt_dimm_row = 0, 1089 .udt_dimm_bank = 0, 1090 .udt_dimm_bank_group = 0, 1091 .udt_dimm_subchan = UINT8_MAX, 1092 .udt_dimm_rm = 0, 1093 .udt_dimm_cs = 0 1094 }, { 1095 .udt_desc = "COD 6ch (10)", 1096 .udt_umc = &zen_umc_cod_6ch, 1097 .udt_pa = 0xa1ff, 1098 .udt_pass = B_TRUE, 1099 .udt_norm_addr = 0x11ff, 1100 .udt_sock = 0, 1101 .udt_die = 0, 1102 .udt_comp = 3, 1103 .udt_dimm_no = 0, 1104 .udt_dimm_col = 0x23f, 1105 .udt_dimm_row = 0, 1106 .udt_dimm_bank = 0, 1107 .udt_dimm_bank_group = 0, 1108 .udt_dimm_subchan = UINT8_MAX, 1109 .udt_dimm_rm = 0, 1110 .udt_dimm_cs = 0 1111 }, { 1112 .udt_desc = "COD 6ch (11)", 1113 .udt_umc = &zen_umc_cod_6ch, 1114 .udt_pa = 0xb1ff, 1115 .udt_pass = B_TRUE, 1116 .udt_norm_addr = 0x11ff, 1117 .udt_sock = 0, 1118 .udt_die = 0, 1119 .udt_comp = 2, 1120 .udt_dimm_no = 0, 1121 .udt_dimm_col = 0x23f, 1122 .udt_dimm_row = 0, 1123 .udt_dimm_bank = 0, 1124 .udt_dimm_bank_group = 0, 1125 .udt_dimm_subchan = UINT8_MAX, 1126 .udt_dimm_rm = 0, 1127 .udt_dimm_cs = 0 1128 }, { 1129 .udt_desc = "COD 6ch (12)", 1130 .udt_umc = &zen_umc_cod_6ch, 1131 .udt_pa = 0xc1ff, 1132 .udt_pass = B_TRUE, 1133 .udt_norm_addr = 0x11ff, 1134 .udt_sock = 0, 1135 .udt_die = 0, 1136 .udt_comp = 5, 1137 .udt_dimm_no = 0, 1138 .udt_dimm_col = 0x23f, 1139 .udt_dimm_row = 0, 1140 .udt_dimm_bank = 0, 1141 .udt_dimm_bank_group = 0, 1142 .udt_dimm_subchan = UINT8_MAX, 1143 .udt_dimm_rm = 0, 1144 .udt_dimm_cs = 0 1145 }, { 1146 .udt_desc = "COD 6ch (13)", 1147 .udt_umc = &zen_umc_cod_6ch, 1148 .udt_pa = 0xd1ff, 1149 .udt_pass = B_TRUE, 1150 .udt_norm_addr = 0x11ff, 1151 .udt_sock = 0, 1152 .udt_die = 0, 1153 .udt_comp = 4, 1154 .udt_dimm_no = 0, 1155 .udt_dimm_col = 0x23f, 1156 .udt_dimm_row = 0, 1157 .udt_dimm_bank = 0, 1158 .udt_dimm_bank_group = 0, 1159 .udt_dimm_subchan = UINT8_MAX, 1160 .udt_dimm_rm = 0, 1161 .udt_dimm_cs = 0 1162 }, { 1163 .udt_desc = "COD 6ch (14)", 1164 .udt_umc = &zen_umc_cod_6ch, 1165 .udt_pa = 0xe1ff, 1166 .udt_pass = B_TRUE, 1167 .udt_norm_addr = 0x3000011ff, 1168 .udt_sock = 0, 1169 .udt_die = 0, 1170 .udt_comp = 3, 1171 .udt_dimm_no = 0, 1172 .udt_dimm_col = 0x23f, 1173 .udt_dimm_row = 0x18000, 1174 .udt_dimm_bank = 0, 1175 .udt_dimm_bank_group = 0, 1176 .udt_dimm_subchan = UINT8_MAX, 1177 .udt_dimm_rm = 0, 1178 .udt_dimm_cs = 0 1179 }, { 1180 .udt_desc = "COD 6ch (15)", 1181 .udt_umc = &zen_umc_cod_6ch, 1182 .udt_pa = 0xf1ff, 1183 .udt_pass = B_TRUE, 1184 .udt_norm_addr = 0x3000011ff, 1185 .udt_sock = 0, 1186 .udt_die = 0, 1187 .udt_comp = 2, 1188 .udt_dimm_no = 0, 1189 .udt_dimm_col = 0x23f, 1190 .udt_dimm_row = 0x18000, 1191 .udt_dimm_bank = 0, 1192 .udt_dimm_bank_group = 0, 1193 .udt_dimm_subchan = UINT8_MAX, 1194 .udt_dimm_rm = 0, 1195 .udt_dimm_cs = 0 1196 }, 1197 /* 1198 * The above went through and showed that we can probably hash things correctly 1199 * and account for our mod-3 case. The ones below try to find the higher level 1200 * addresses that would result in the same normalized address that we have, but 1201 * on different dies to try and complete the set. 1202 */ 1203 { 1204 .udt_desc = "COD 6ch (16)", 1205 .udt_umc = &zen_umc_cod_6ch, 1206 .udt_pa = 0x8000061ff, 1207 .udt_pass = B_TRUE, 1208 .udt_norm_addr = 0x3000001ff, 1209 .udt_sock = 0, 1210 .udt_die = 0, 1211 .udt_comp = 2, 1212 .udt_dimm_no = 0, 1213 .udt_dimm_col = 0x3f, 1214 .udt_dimm_row = 0x18000, 1215 .udt_dimm_bank = 0, 1216 .udt_dimm_bank_group = 0, 1217 .udt_dimm_subchan = UINT8_MAX, 1218 .udt_dimm_rm = 0, 1219 .udt_dimm_cs = 0 1220 }, { 1221 .udt_desc = "COD 6ch (17)", 1222 .udt_umc = &zen_umc_cod_6ch, 1223 .udt_pa = 0x8000071ff, 1224 .udt_pass = B_TRUE, 1225 .udt_norm_addr = 0x3000001ff, 1226 .udt_sock = 0, 1227 .udt_die = 0, 1228 .udt_comp = 3, 1229 .udt_dimm_no = 0, 1230 .udt_dimm_col = 0x3f, 1231 .udt_dimm_row = 0x18000, 1232 .udt_dimm_bank = 0, 1233 .udt_dimm_bank_group = 0, 1234 .udt_dimm_subchan = UINT8_MAX, 1235 .udt_dimm_rm = 0, 1236 .udt_dimm_cs = 0 1237 }, { 1238 .udt_desc = "COD 6ch (18)", 1239 .udt_umc = &zen_umc_cod_6ch, 1240 .udt_pa = 0x10000061ff, 1241 .udt_pass = B_TRUE, 1242 .udt_norm_addr = 0x3000001ff, 1243 .udt_sock = 0, 1244 .udt_die = 0, 1245 .udt_comp = 4, 1246 .udt_dimm_no = 0, 1247 .udt_dimm_col = 0x3f, 1248 .udt_dimm_row = 0x18000, 1249 .udt_dimm_bank = 0, 1250 .udt_dimm_bank_group = 0, 1251 .udt_dimm_subchan = UINT8_MAX, 1252 .udt_dimm_rm = 0, 1253 .udt_dimm_cs = 0 1254 }, { 1255 .udt_desc = "COD 6ch (19)", 1256 .udt_umc = &zen_umc_cod_6ch, 1257 .udt_pa = 0x10000071ff, 1258 .udt_pass = B_TRUE, 1259 .udt_norm_addr = 0x3000001ff, 1260 .udt_sock = 0, 1261 .udt_die = 0, 1262 .udt_comp = 5, 1263 .udt_dimm_no = 0, 1264 .udt_dimm_col = 0x3f, 1265 .udt_dimm_row = 0x18000, 1266 .udt_dimm_bank = 0, 1267 .udt_dimm_bank_group = 0, 1268 .udt_dimm_subchan = UINT8_MAX, 1269 .udt_dimm_rm = 0, 1270 .udt_dimm_cs = 0 1271 }, 1272 /* 1273 * Now with that there, we go back and show that hashing actually impacts things 1274 * as we expect. Note, the bit 0 hash was already taken into account. 1275 */ 1276 { 1277 .udt_desc = "COD 6ch (20)", 1278 .udt_umc = &zen_umc_cod_6ch, 1279 .udt_pa = 0x8001ff, 1280 .udt_pass = B_TRUE, 1281 .udt_norm_addr = 0x1001ff, 1282 .udt_sock = 0, 1283 .udt_die = 0, 1284 .udt_comp = 1, 1285 .udt_dimm_no = 0, 1286 .udt_dimm_col = 0x3f, 1287 .udt_dimm_row = 0x8, 1288 .udt_dimm_bank = 0, 1289 .udt_dimm_bank_group = 0, 1290 .udt_dimm_subchan = UINT8_MAX, 1291 .udt_dimm_rm = 0, 1292 .udt_dimm_cs = 0 1293 }, { 1294 .udt_desc = "COD 6ch (21)", 1295 .udt_umc = &zen_umc_cod_6ch, 1296 .udt_pa = 0xa001ff, 1297 .udt_pass = B_TRUE, 1298 .udt_norm_addr = 0x1401ff, 1299 .udt_sock = 0, 1300 .udt_die = 0, 1301 .udt_comp = 3, 1302 .udt_dimm_no = 0, 1303 .udt_dimm_col = 0x3f, 1304 .udt_dimm_row = 0xa, 1305 .udt_dimm_bank = 0, 1306 .udt_dimm_bank_group = 0, 1307 .udt_dimm_subchan = UINT8_MAX, 1308 .udt_dimm_rm = 0, 1309 .udt_dimm_cs = 0 1310 }, { 1311 .udt_desc = "COD 6ch (22)", 1312 .udt_umc = &zen_umc_cod_6ch, 1313 .udt_pa = 0xe001ff, 1314 .udt_pass = B_TRUE, 1315 .udt_norm_addr = 0x3001c01ff, 1316 .udt_sock = 0, 1317 .udt_die = 0, 1318 .udt_comp = 3, 1319 .udt_dimm_no = 0, 1320 .udt_dimm_col = 0x3f, 1321 .udt_dimm_row = 0x1800e, 1322 .udt_dimm_bank = 0, 1323 .udt_dimm_bank_group = 0, 1324 .udt_dimm_subchan = UINT8_MAX, 1325 .udt_dimm_rm = 0, 1326 .udt_dimm_cs = 0 1327 }, { 1328 .udt_desc = "COD 6ch (23)", 1329 .udt_umc = &zen_umc_cod_6ch, 1330 .udt_pa = 0x180e001ff, 1331 .udt_pass = B_TRUE, 1332 .udt_norm_addr = 0x301c01ff, 1333 .udt_sock = 0, 1334 .udt_die = 0, 1335 .udt_comp = 2, 1336 .udt_dimm_no = 0, 1337 .udt_dimm_col = 0x3f, 1338 .udt_dimm_row = 0x180e, 1339 .udt_dimm_bank = 0, 1340 .udt_dimm_bank_group = 0, 1341 .udt_dimm_subchan = UINT8_MAX, 1342 .udt_dimm_rm = 0, 1343 .udt_dimm_cs = 0 1344 }, { 1345 .udt_desc = "COD 6ch (24)", 1346 .udt_umc = &zen_umc_cod_6ch, 1347 .udt_pa = 0x1c0e041ff, 1348 .udt_pass = B_TRUE, 1349 .udt_norm_addr = 0x381c01ff, 1350 .udt_sock = 0, 1351 .udt_die = 0, 1352 .udt_comp = 4, 1353 .udt_dimm_no = 0, 1354 .udt_dimm_col = 0x3f, 1355 .udt_dimm_row = 0x1c0e, 1356 .udt_dimm_bank = 0, 1357 .udt_dimm_bank_group = 0, 1358 .udt_dimm_subchan = UINT8_MAX, 1359 .udt_dimm_rm = 0, 1360 .udt_dimm_cs = 0 1361 }, { 1362 .udt_desc = NULL 1363 } }; 1364