1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 /* 17 * Here we test several different channel related test cases. In particular, we 18 * want to exercise the following situations: 19 * 20 * o Multiple DIMMs per channel (no hashing) 21 * o Multiple DIMMs per channel (chip-select interleaving) 22 * o CS Hashing 23 * o Bank Hashing 24 * o Bank Swaps 25 * o Basic sub-channel 26 * 27 * For all of these, we don't do anything special from the Data Fabric to 28 * strictly allow us to reason about the channel logic here. 29 * 30 * Currently, we do not have tests for the following because we don't have a 31 * great sense of how the AMD SoC will set this up for the decoder: 32 * 33 * o Cases where rank-multiplication and hashing are taking place 34 * o Cases where sub-channel hashing is being used 35 */ 36 37 #include "zen_umc_test.h" 38 39 /* 40 * This has two of our favorite 64 GiB DIMMs. Everything is done out linearly. 41 * Because of this, we don't apply any channel offsets. 42 */ 43 static const zen_umc_t zen_umc_chan_no_hash = { 44 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 45 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 46 .umc_df_rev = DF_REV_3, 47 /* Per milan_decomp */ 48 .umc_decomp = { 49 .dfd_sock_mask = 0x01, 50 .dfd_die_mask = 0x00, 51 .dfd_node_mask = 0x20, 52 .dfd_comp_mask = 0x1f, 53 .dfd_sock_shift = 0, 54 .dfd_die_shift = 0, 55 .dfd_node_shift = 5, 56 .dfd_comp_shift = 0 57 }, 58 .umc_ndfs = 1, 59 .umc_dfs = { { 60 .zud_dfno = 0, 61 .zud_ccm_inst = 0, 62 .zud_dram_nrules = 1, 63 .zud_nchan = 1, 64 .zud_cs_nremap = 0, 65 .zud_hole_base = 0, 66 .zud_rules = { { 67 .ddr_flags = DF_DRAM_F_VALID, 68 .ddr_base = 0, 69 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 70 .ddr_dest_fabid = 1, 71 .ddr_sock_ileave_bits = 0, 72 .ddr_die_ileave_bits = 0, 73 .ddr_addr_start = 9, 74 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 75 } }, 76 .zud_chan = { { 77 .chan_flags = UMC_CHAN_F_ECC_EN, 78 .chan_fabid = 1, 79 .chan_instid = 1, 80 .chan_logid = 0, 81 .chan_nrules = 1, 82 .chan_type = UMC_DIMM_T_DDR4, 83 .chan_rules = { { 84 .ddr_flags = DF_DRAM_F_VALID, 85 .ddr_base = 0, 86 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 87 1024ULL, 88 .ddr_dest_fabid = 1, 89 .ddr_sock_ileave_bits = 0, 90 .ddr_die_ileave_bits = 0, 91 .ddr_addr_start = 9, 92 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 93 } }, 94 .chan_dimms = { { 95 .ud_flags = UMC_DIMM_F_VALID, 96 .ud_width = UMC_DIMM_W_X4, 97 .ud_kind = UMC_DIMM_K_RDIMM, 98 .ud_dimmno = 0, 99 .ud_cs = { { 100 .ucs_flags = UMC_CS_F_DECODE_EN, 101 .ucs_base = { 102 .udb_base = 0, 103 .udb_valid = B_TRUE 104 }, 105 .ucs_base_mask = 0x7ffffffff, 106 .ucs_nbanks = 0x4, 107 .ucs_ncol = 0xa, 108 .ucs_nrow_lo = 0x12, 109 .ucs_nbank_groups = 0x2, 110 .ucs_row_hi_bit = 0x18, 111 .ucs_row_low_bit = 0x11, 112 .ucs_bank_bits = { 0xf, 0x10, 0xd, 113 0xe }, 114 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 115 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 116 }, { 117 .ucs_flags = UMC_CS_F_DECODE_EN, 118 .ucs_base = { 119 .udb_base = 0x800000000, 120 .udb_valid = B_TRUE 121 }, 122 .ucs_base_mask = 0x7ffffffff, 123 .ucs_nbanks = 0x4, 124 .ucs_ncol = 0xa, 125 .ucs_nrow_lo = 0x12, 126 .ucs_nbank_groups = 0x2, 127 .ucs_row_hi_bit = 0x18, 128 .ucs_row_low_bit = 0x11, 129 .ucs_bank_bits = { 0xf, 0x10, 0xd, 130 0xe }, 131 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 132 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 133 } } 134 }, { 135 .ud_flags = UMC_DIMM_F_VALID, 136 .ud_width = UMC_DIMM_W_X4, 137 .ud_kind = UMC_DIMM_K_RDIMM, 138 .ud_dimmno = 1, 139 .ud_cs = { { 140 .ucs_flags = UMC_CS_F_DECODE_EN, 141 .ucs_base = { 142 .udb_base = 0x1000000000, 143 .udb_valid = B_TRUE 144 }, 145 .ucs_base_mask = 0x7ffffffff, 146 .ucs_nbanks = 0x4, 147 .ucs_ncol = 0xa, 148 .ucs_nrow_lo = 0x12, 149 .ucs_nbank_groups = 0x2, 150 .ucs_row_hi_bit = 0x18, 151 .ucs_row_low_bit = 0x11, 152 .ucs_bank_bits = { 0xf, 0x10, 0xd, 153 0xe }, 154 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 155 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 156 }, { 157 .ucs_flags = UMC_CS_F_DECODE_EN, 158 .ucs_base = { 159 .udb_base = 0x1800000000, 160 .udb_valid = B_TRUE 161 }, 162 .ucs_base_mask = 0x7ffffffff, 163 .ucs_nbanks = 0x4, 164 .ucs_ncol = 0xa, 165 .ucs_nrow_lo = 0x12, 166 .ucs_nbank_groups = 0x2, 167 .ucs_row_hi_bit = 0x18, 168 .ucs_row_low_bit = 0x11, 169 .ucs_bank_bits = { 0xf, 0x10, 0xd, 170 0xe }, 171 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 172 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 173 } } 174 } } 175 } } 176 } } 177 }; 178 179 /* 180 * This is a variant on the prior where we begin to interleave across all 4 181 * ranks in a channel, which AMD calls chip-select interleaving. This basically 182 * uses bits in the middle of the address to select the rank and therefore 183 * shifts all the other bits that get used for rank and bank selection. This 184 * works by shifting which address bits are used to actually determine the row 185 * up, allowing us to interleave in the middle of this. 186 */ 187 static const zen_umc_t zen_umc_chan_ilv = { 188 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 189 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 190 .umc_df_rev = DF_REV_3, 191 /* Per milan_decomp */ 192 .umc_decomp = { 193 .dfd_sock_mask = 0x01, 194 .dfd_die_mask = 0x00, 195 .dfd_node_mask = 0x20, 196 .dfd_comp_mask = 0x1f, 197 .dfd_sock_shift = 0, 198 .dfd_die_shift = 0, 199 .dfd_node_shift = 5, 200 .dfd_comp_shift = 0 201 }, 202 .umc_ndfs = 1, 203 .umc_dfs = { { 204 .zud_dfno = 0, 205 .zud_ccm_inst = 0, 206 .zud_dram_nrules = 1, 207 .zud_nchan = 1, 208 .zud_cs_nremap = 0, 209 .zud_hole_base = 0, 210 .zud_rules = { { 211 .ddr_flags = DF_DRAM_F_VALID, 212 .ddr_base = 0, 213 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 214 .ddr_dest_fabid = 1, 215 .ddr_sock_ileave_bits = 0, 216 .ddr_die_ileave_bits = 0, 217 .ddr_addr_start = 9, 218 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 219 } }, 220 .zud_chan = { { 221 .chan_flags = UMC_CHAN_F_ECC_EN, 222 .chan_fabid = 1, 223 .chan_instid = 1, 224 .chan_logid = 0, 225 .chan_nrules = 1, 226 .chan_type = UMC_DIMM_T_DDR4, 227 .chan_rules = { { 228 .ddr_flags = DF_DRAM_F_VALID, 229 .ddr_base = 0, 230 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 231 1024ULL, 232 .ddr_dest_fabid = 1, 233 .ddr_sock_ileave_bits = 0, 234 .ddr_die_ileave_bits = 0, 235 .ddr_addr_start = 9, 236 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 237 } }, 238 .chan_dimms = { { 239 .ud_flags = UMC_DIMM_F_VALID, 240 .ud_width = UMC_DIMM_W_X4, 241 .ud_kind = UMC_DIMM_K_RDIMM, 242 .ud_dimmno = 0, 243 .ud_cs = { { 244 .ucs_flags = UMC_CS_F_DECODE_EN, 245 .ucs_base = { 246 .udb_base = 0, 247 .udb_valid = B_TRUE 248 }, 249 .ucs_base_mask = 0x1ffff9ffff, 250 .ucs_nbanks = 0x4, 251 .ucs_ncol = 0xa, 252 .ucs_nrow_lo = 0x12, 253 .ucs_nbank_groups = 0x2, 254 .ucs_row_hi_bit = 0x18, 255 .ucs_row_low_bit = 0x13, 256 .ucs_bank_bits = { 0xd, 0xe, 0xf, 257 0x10 }, 258 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 259 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 260 }, { 261 .ucs_flags = UMC_CS_F_DECODE_EN, 262 .ucs_base = { 263 .udb_base = 0x20000, 264 .udb_valid = B_TRUE 265 }, 266 .ucs_base_mask = 0x1ffff9ffff, 267 .ucs_nbanks = 0x4, 268 .ucs_ncol = 0xa, 269 .ucs_nrow_lo = 0x12, 270 .ucs_nbank_groups = 0x2, 271 .ucs_row_hi_bit = 0x18, 272 .ucs_row_low_bit = 0x13, 273 .ucs_bank_bits = { 0xd, 0xe, 0xf, 274 0x10 }, 275 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 276 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 277 } } 278 }, { 279 .ud_flags = UMC_DIMM_F_VALID, 280 .ud_width = UMC_DIMM_W_X4, 281 .ud_kind = UMC_DIMM_K_RDIMM, 282 .ud_dimmno = 1, 283 .ud_cs = { { 284 .ucs_flags = UMC_CS_F_DECODE_EN, 285 .ucs_base = { 286 .udb_base = 0x40000, 287 .udb_valid = B_TRUE 288 }, 289 .ucs_base_mask = 0x1ffff9ffff, 290 .ucs_nbanks = 0x4, 291 .ucs_ncol = 0xa, 292 .ucs_nrow_lo = 0x12, 293 .ucs_nbank_groups = 0x2, 294 .ucs_row_hi_bit = 0x18, 295 .ucs_row_low_bit = 0x13, 296 .ucs_bank_bits = { 0xd, 0xe, 0xf, 297 0x10 }, 298 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 299 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 300 }, { 301 .ucs_flags = UMC_CS_F_DECODE_EN, 302 .ucs_base = { 303 .udb_base = 0x60000, 304 .udb_valid = B_TRUE 305 }, 306 .ucs_base_mask = 0x1ffff9ffff, 307 .ucs_nbanks = 0x4, 308 .ucs_ncol = 0xa, 309 .ucs_nrow_lo = 0x12, 310 .ucs_nbank_groups = 0x2, 311 .ucs_row_hi_bit = 0x18, 312 .ucs_row_low_bit = 0x13, 313 .ucs_bank_bits = { 0xd, 0xe, 0xf, 314 0x10 }, 315 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 316 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 317 } } 318 } } 319 } } 320 } } 321 }; 322 323 /* 324 * This sets up a CS hash across all 4 ranks. The actual values here are 325 * representative of a set up we've seen on the CPU. 326 */ 327 static const zen_umc_t zen_umc_chan_ilv_cs_hash = { 328 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 329 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 330 .umc_df_rev = DF_REV_3, 331 /* Per milan_decomp */ 332 .umc_decomp = { 333 .dfd_sock_mask = 0x01, 334 .dfd_die_mask = 0x00, 335 .dfd_node_mask = 0x20, 336 .dfd_comp_mask = 0x1f, 337 .dfd_sock_shift = 0, 338 .dfd_die_shift = 0, 339 .dfd_node_shift = 5, 340 .dfd_comp_shift = 0 341 }, 342 .umc_ndfs = 1, 343 .umc_dfs = { { 344 .zud_dfno = 0, 345 .zud_ccm_inst = 0, 346 .zud_dram_nrules = 1, 347 .zud_nchan = 1, 348 .zud_cs_nremap = 0, 349 .zud_hole_base = 0, 350 .zud_rules = { { 351 .ddr_flags = DF_DRAM_F_VALID, 352 .ddr_base = 0, 353 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 354 .ddr_dest_fabid = 1, 355 .ddr_sock_ileave_bits = 0, 356 .ddr_die_ileave_bits = 0, 357 .ddr_addr_start = 9, 358 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 359 } }, 360 .zud_chan = { { 361 .chan_flags = UMC_CHAN_F_ECC_EN, 362 .chan_fabid = 1, 363 .chan_instid = 1, 364 .chan_logid = 0, 365 .chan_nrules = 1, 366 .chan_type = UMC_DIMM_T_DDR4, 367 .chan_rules = { { 368 .ddr_flags = DF_DRAM_F_VALID, 369 .ddr_base = 0, 370 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 371 1024ULL, 372 .ddr_dest_fabid = 1, 373 .ddr_sock_ileave_bits = 0, 374 .ddr_die_ileave_bits = 0, 375 .ddr_addr_start = 9, 376 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 377 } }, 378 .chan_dimms = { { 379 .ud_flags = UMC_DIMM_F_VALID, 380 .ud_width = UMC_DIMM_W_X4, 381 .ud_kind = UMC_DIMM_K_RDIMM, 382 .ud_dimmno = 0, 383 .ud_cs = { { 384 .ucs_flags = UMC_CS_F_DECODE_EN, 385 .ucs_base = { 386 .udb_base = 0, 387 .udb_valid = B_TRUE 388 }, 389 .ucs_base_mask = 0x1ffff9ffff, 390 .ucs_nbanks = 0x4, 391 .ucs_ncol = 0xa, 392 .ucs_nrow_lo = 0x12, 393 .ucs_nbank_groups = 0x2, 394 .ucs_row_hi_bit = 0x18, 395 .ucs_row_low_bit = 0x13, 396 .ucs_bank_bits = { 0xd, 0xe, 0xf, 397 0x10 }, 398 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 399 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 400 }, { 401 .ucs_flags = UMC_CS_F_DECODE_EN, 402 .ucs_base = { 403 .udb_base = 0x20000, 404 .udb_valid = B_TRUE 405 }, 406 .ucs_base_mask = 0x1ffff9ffff, 407 .ucs_nbanks = 0x4, 408 .ucs_ncol = 0xa, 409 .ucs_nrow_lo = 0x12, 410 .ucs_nbank_groups = 0x2, 411 .ucs_row_hi_bit = 0x18, 412 .ucs_row_low_bit = 0x13, 413 .ucs_bank_bits = { 0xd, 0xe, 0xf, 414 0x10 }, 415 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 416 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 417 } } 418 }, { 419 .ud_flags = UMC_DIMM_F_VALID, 420 .ud_width = UMC_DIMM_W_X4, 421 .ud_kind = UMC_DIMM_K_RDIMM, 422 .ud_dimmno = 1, 423 .ud_cs = { { 424 .ucs_flags = UMC_CS_F_DECODE_EN, 425 .ucs_base = { 426 .udb_base = 0x40000, 427 .udb_valid = B_TRUE 428 }, 429 .ucs_base_mask = 0x1ffff9ffff, 430 .ucs_nbanks = 0x4, 431 .ucs_ncol = 0xa, 432 .ucs_nrow_lo = 0x12, 433 .ucs_nbank_groups = 0x2, 434 .ucs_row_hi_bit = 0x18, 435 .ucs_row_low_bit = 0x13, 436 .ucs_bank_bits = { 0xd, 0xe, 0xf, 437 0x10 }, 438 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 439 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 440 }, { 441 .ucs_flags = UMC_CS_F_DECODE_EN, 442 .ucs_base = { 443 .udb_base = 0x60000, 444 .udb_valid = B_TRUE 445 }, 446 .ucs_base_mask = 0x1ffff9ffff, 447 .ucs_nbanks = 0x4, 448 .ucs_ncol = 0xa, 449 .ucs_nrow_lo = 0x12, 450 .ucs_nbank_groups = 0x2, 451 .ucs_row_hi_bit = 0x18, 452 .ucs_row_low_bit = 0x13, 453 .ucs_bank_bits = { 0xd, 0xe, 0xf, 454 0x10 }, 455 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 456 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 457 } } 458 } }, 459 .chan_hash = { 460 .uch_flags = UMC_CHAN_HASH_F_CS, 461 .uch_cs_hashes = { { 462 .uah_addr_xor = 0xaaaa80000, 463 .uah_en = B_TRUE 464 }, { 465 .uah_addr_xor = 0x1555500000, 466 .uah_en = B_TRUE 467 } } 468 } 469 } } 470 } } 471 }; 472 473 /* 474 * This enables bank hashing across both of the DIMMs in this configuration. The 475 * use of the row and not the column to select the bank is based on a CPU config 476 * seen in the wild. 477 */ 478 static const zen_umc_t zen_umc_chan_ilv_bank_hash = { 479 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 480 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 481 .umc_df_rev = DF_REV_3, 482 /* Per milan_decomp */ 483 .umc_decomp = { 484 .dfd_sock_mask = 0x01, 485 .dfd_die_mask = 0x00, 486 .dfd_node_mask = 0x20, 487 .dfd_comp_mask = 0x1f, 488 .dfd_sock_shift = 0, 489 .dfd_die_shift = 0, 490 .dfd_node_shift = 5, 491 .dfd_comp_shift = 0 492 }, 493 .umc_ndfs = 1, 494 .umc_dfs = { { 495 .zud_dfno = 0, 496 .zud_ccm_inst = 0, 497 .zud_dram_nrules = 1, 498 .zud_nchan = 1, 499 .zud_cs_nremap = 0, 500 .zud_hole_base = 0, 501 .zud_rules = { { 502 .ddr_flags = DF_DRAM_F_VALID, 503 .ddr_base = 0, 504 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 505 .ddr_dest_fabid = 1, 506 .ddr_sock_ileave_bits = 0, 507 .ddr_die_ileave_bits = 0, 508 .ddr_addr_start = 9, 509 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 510 } }, 511 .zud_chan = { { 512 .chan_flags = UMC_CHAN_F_ECC_EN, 513 .chan_fabid = 1, 514 .chan_instid = 1, 515 .chan_logid = 0, 516 .chan_nrules = 1, 517 .chan_type = UMC_DIMM_T_DDR4, 518 .chan_rules = { { 519 .ddr_flags = DF_DRAM_F_VALID, 520 .ddr_base = 0, 521 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 522 1024ULL, 523 .ddr_dest_fabid = 1, 524 .ddr_sock_ileave_bits = 0, 525 .ddr_die_ileave_bits = 0, 526 .ddr_addr_start = 9, 527 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 528 } }, 529 .chan_dimms = { { 530 .ud_flags = UMC_DIMM_F_VALID, 531 .ud_width = UMC_DIMM_W_X4, 532 .ud_kind = UMC_DIMM_K_RDIMM, 533 .ud_dimmno = 0, 534 .ud_cs = { { 535 .ucs_flags = UMC_CS_F_DECODE_EN, 536 .ucs_base = { 537 .udb_base = 0, 538 .udb_valid = B_TRUE 539 }, 540 .ucs_base_mask = 0x1ffff9ffff, 541 .ucs_nbanks = 0x4, 542 .ucs_ncol = 0xa, 543 .ucs_nrow_lo = 0x12, 544 .ucs_nbank_groups = 0x2, 545 .ucs_row_hi_bit = 0x18, 546 .ucs_row_low_bit = 0x13, 547 .ucs_bank_bits = { 0xd, 0xe, 0xf, 548 0x10 }, 549 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 550 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 551 }, { 552 .ucs_flags = UMC_CS_F_DECODE_EN, 553 .ucs_base = { 554 .udb_base = 0x20000, 555 .udb_valid = B_TRUE 556 }, 557 .ucs_base_mask = 0x1ffff9ffff, 558 .ucs_nbanks = 0x4, 559 .ucs_ncol = 0xa, 560 .ucs_nrow_lo = 0x12, 561 .ucs_nbank_groups = 0x2, 562 .ucs_row_hi_bit = 0x18, 563 .ucs_row_low_bit = 0x13, 564 .ucs_bank_bits = { 0xd, 0xe, 0xf, 565 0x10 }, 566 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 567 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 568 } } 569 }, { 570 .ud_flags = UMC_DIMM_F_VALID, 571 .ud_width = UMC_DIMM_W_X4, 572 .ud_kind = UMC_DIMM_K_RDIMM, 573 .ud_dimmno = 1, 574 .ud_cs = { { 575 .ucs_flags = UMC_CS_F_DECODE_EN, 576 .ucs_base = { 577 .udb_base = 0x40000, 578 .udb_valid = B_TRUE 579 }, 580 .ucs_base_mask = 0x1ffff9ffff, 581 .ucs_nbanks = 0x4, 582 .ucs_ncol = 0xa, 583 .ucs_nrow_lo = 0x12, 584 .ucs_nbank_groups = 0x2, 585 .ucs_row_hi_bit = 0x18, 586 .ucs_row_low_bit = 0x13, 587 .ucs_bank_bits = { 0xd, 0xe, 0xf, 588 0x10 }, 589 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 590 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 591 }, { 592 .ucs_flags = UMC_CS_F_DECODE_EN, 593 .ucs_base = { 594 .udb_base = 0x60000, 595 .udb_valid = B_TRUE 596 }, 597 .ucs_base_mask = 0x1ffff9ffff, 598 .ucs_nbanks = 0x4, 599 .ucs_ncol = 0xa, 600 .ucs_nrow_lo = 0x12, 601 .ucs_nbank_groups = 0x2, 602 .ucs_row_hi_bit = 0x18, 603 .ucs_row_low_bit = 0x13, 604 .ucs_bank_bits = { 0xd, 0xe, 0xf, 605 0x10 }, 606 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 607 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 608 } } 609 } }, 610 .chan_hash = { 611 .uch_flags = UMC_CHAN_HASH_F_BANK, 612 .uch_bank_hashes = { { 613 .ubh_row_xor = 0x11111, 614 .ubh_col_xor = 0, 615 .ubh_en = B_TRUE 616 }, { 617 .ubh_row_xor = 0x22222, 618 .ubh_col_xor = 0, 619 .ubh_en = B_TRUE 620 }, { 621 .ubh_row_xor = 0x4444, 622 .ubh_col_xor = 0, 623 .ubh_en = B_TRUE 624 }, { 625 .ubh_row_xor = 0x8888, 626 .ubh_col_xor = 0, 627 .ubh_en = B_TRUE 628 } } 629 } 630 } } 631 } } 632 }; 633 634 /* 635 * Some configurations allow optional bank swaps where by the bits we use for 636 * the column and the bank are swapped around. Do one of these just to make sure 637 * we haven't built in any surprise dependencies. 638 */ 639 static const zen_umc_t zen_umc_chan_ilv_bank_swap = { 640 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 641 .umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL, 642 .umc_df_rev = DF_REV_3, 643 .umc_decomp = { 644 .dfd_sock_mask = 0x01, 645 .dfd_die_mask = 0x00, 646 .dfd_node_mask = 0x20, 647 .dfd_comp_mask = 0x1f, 648 .dfd_sock_shift = 0, 649 .dfd_die_shift = 0, 650 .dfd_node_shift = 5, 651 .dfd_comp_shift = 0 652 }, 653 .umc_ndfs = 1, 654 .umc_dfs = { { 655 .zud_dfno = 0, 656 .zud_ccm_inst = 0, 657 .zud_dram_nrules = 1, 658 .zud_nchan = 1, 659 .zud_cs_nremap = 0, 660 .zud_hole_base = 0, 661 .zud_rules = { { 662 .ddr_flags = DF_DRAM_F_VALID, 663 .ddr_base = 0, 664 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL, 665 .ddr_dest_fabid = 1, 666 .ddr_sock_ileave_bits = 0, 667 .ddr_die_ileave_bits = 0, 668 .ddr_addr_start = 9, 669 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 670 } }, 671 .zud_chan = { { 672 .chan_flags = UMC_CHAN_F_ECC_EN, 673 .chan_fabid = 1, 674 .chan_instid = 1, 675 .chan_logid = 0, 676 .chan_nrules = 1, 677 .chan_type = UMC_DIMM_T_DDR4, 678 .chan_rules = { { 679 .ddr_flags = DF_DRAM_F_VALID, 680 .ddr_base = 0, 681 .ddr_limit = 128ULL * 1024ULL * 1024ULL * 682 1024ULL, 683 .ddr_dest_fabid = 1, 684 .ddr_sock_ileave_bits = 0, 685 .ddr_die_ileave_bits = 0, 686 .ddr_addr_start = 9, 687 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 688 } }, 689 .chan_dimms = { { 690 .ud_flags = UMC_DIMM_F_VALID, 691 .ud_width = UMC_DIMM_W_X4, 692 .ud_kind = UMC_DIMM_K_RDIMM, 693 .ud_dimmno = 0, 694 .ud_cs = { { 695 .ucs_flags = UMC_CS_F_DECODE_EN, 696 .ucs_base = { 697 .udb_base = 0, 698 .udb_valid = B_TRUE 699 }, 700 .ucs_base_mask = 0x1ffff9ffff, 701 .ucs_nbanks = 0x4, 702 .ucs_ncol = 0xa, 703 .ucs_nrow_lo = 0x12, 704 .ucs_nbank_groups = 0x2, 705 .ucs_row_hi_bit = 0x18, 706 .ucs_row_low_bit = 0x13, 707 .ucs_bank_bits = { 0x9, 0xa, 0x6, 708 0xb }, 709 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 710 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 711 }, { 712 .ucs_flags = UMC_CS_F_DECODE_EN, 713 .ucs_base = { 714 .udb_base = 0x20000, 715 .udb_valid = B_TRUE 716 }, 717 .ucs_base_mask = 0x1ffff9ffff, 718 .ucs_nbanks = 0x4, 719 .ucs_ncol = 0xa, 720 .ucs_nrow_lo = 0x12, 721 .ucs_nbank_groups = 0x2, 722 .ucs_row_hi_bit = 0x18, 723 .ucs_row_low_bit = 0x13, 724 .ucs_bank_bits = { 0x9, 0xa, 0x6, 725 0xb }, 726 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 727 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 728 } } 729 }, { 730 .ud_flags = UMC_DIMM_F_VALID, 731 .ud_width = UMC_DIMM_W_X4, 732 .ud_kind = UMC_DIMM_K_RDIMM, 733 .ud_dimmno = 1, 734 .ud_cs = { { 735 .ucs_flags = UMC_CS_F_DECODE_EN, 736 .ucs_base = { 737 .udb_base = 0x40000, 738 .udb_valid = B_TRUE 739 }, 740 .ucs_base_mask = 0x1ffff9ffff, 741 .ucs_nbanks = 0x4, 742 .ucs_ncol = 0xa, 743 .ucs_nrow_lo = 0x12, 744 .ucs_nbank_groups = 0x2, 745 .ucs_row_hi_bit = 0x18, 746 .ucs_row_low_bit = 0x13, 747 .ucs_bank_bits = { 0x9, 0xa, 0x6, 748 0xb }, 749 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 750 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 751 }, { 752 .ucs_flags = UMC_CS_F_DECODE_EN, 753 .ucs_base = { 754 .udb_base = 0x60000, 755 .udb_valid = B_TRUE 756 }, 757 .ucs_base_mask = 0x1ffff9ffff, 758 .ucs_nbanks = 0x4, 759 .ucs_ncol = 0xa, 760 .ucs_nrow_lo = 0x12, 761 .ucs_nbank_groups = 0x2, 762 .ucs_row_hi_bit = 0x18, 763 .ucs_row_low_bit = 0x13, 764 .ucs_bank_bits = { 0x9, 0xa, 0x6, 765 0xb }, 766 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x7, 767 0x8, 0xc, 0xd, 0xe, 0xf, 0x10 } 768 } } 769 } } 770 } } 771 } } 772 }; 773 774 /* 775 * This is a basic DDR5 channel. We only use a single DIMM and set up a 776 * sub-channel on it. 777 */ 778 static const zen_umc_t zen_umc_chan_subchan_no_hash = { 779 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 780 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 781 .umc_df_rev = DF_REV_3, 782 .umc_decomp = { 783 .dfd_sock_mask = 0x01, 784 .dfd_die_mask = 0x00, 785 .dfd_node_mask = 0x20, 786 .dfd_comp_mask = 0x1f, 787 .dfd_sock_shift = 0, 788 .dfd_die_shift = 0, 789 .dfd_node_shift = 5, 790 .dfd_comp_shift = 0 791 }, 792 .umc_ndfs = 1, 793 .umc_dfs = { { 794 .zud_dfno = 0, 795 .zud_ccm_inst = 0, 796 .zud_dram_nrules = 1, 797 .zud_nchan = 1, 798 .zud_cs_nremap = 0, 799 .zud_hole_base = 0, 800 .zud_rules = { { 801 .ddr_flags = DF_DRAM_F_VALID, 802 .ddr_base = 0, 803 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 1024ULL, 804 .ddr_dest_fabid = 1, 805 .ddr_sock_ileave_bits = 0, 806 .ddr_die_ileave_bits = 0, 807 .ddr_addr_start = 9, 808 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 809 } }, 810 .zud_chan = { { 811 .chan_flags = UMC_CHAN_F_ECC_EN, 812 .chan_fabid = 1, 813 .chan_instid = 1, 814 .chan_logid = 0, 815 .chan_nrules = 1, 816 .chan_type = UMC_DIMM_T_DDR5, 817 .chan_rules = { { 818 .ddr_flags = DF_DRAM_F_VALID, 819 .ddr_base = 0, 820 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 821 1024ULL, 822 .ddr_dest_fabid = 1, 823 .ddr_sock_ileave_bits = 0, 824 .ddr_die_ileave_bits = 0, 825 .ddr_addr_start = 9, 826 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 827 } }, 828 .chan_dimms = { { 829 .ud_flags = UMC_DIMM_F_VALID, 830 .ud_width = UMC_DIMM_W_X4, 831 .ud_kind = UMC_DIMM_K_RDIMM, 832 .ud_dimmno = 0, 833 .ud_cs = { { 834 .ucs_flags = UMC_CS_F_DECODE_EN, 835 .ucs_base = { 836 .udb_base = 0, 837 .udb_valid = B_TRUE 838 }, 839 .ucs_base_mask = 0x3ffffffff, 840 .ucs_nbanks = 0x5, 841 .ucs_ncol = 0xa, 842 .ucs_nrow_lo = 0x10, 843 .ucs_nbank_groups = 0x3, 844 .ucs_row_low_bit = 0x12, 845 .ucs_bank_bits = { 0xf, 0x10, 0x11, 846 0xd, 0xe }, 847 .ucs_col_bits = { 0x2, 0x3, 0x4, 0x5, 848 0x7, 0x8, 0x9, 0xa, 0xb, 0xc }, 849 .ucs_subchan = 0x6 850 } } 851 } } 852 } } 853 } } 854 }; 855 856 const umc_decode_test_t zen_umc_test_chans[] = { { 857 .udt_desc = "2 DPC 2R no ilv/hash (0)", 858 .udt_umc = &zen_umc_chan_no_hash, 859 .udt_pa = 0x0, 860 .udt_pass = B_TRUE, 861 .udt_norm_addr = 0x0, 862 .udt_sock = 0, 863 .udt_die = 0, 864 .udt_comp = 1, 865 .udt_dimm_no = 0, 866 .udt_dimm_col = 0, 867 .udt_dimm_row = 0, 868 .udt_dimm_bank = 0, 869 .udt_dimm_bank_group = 0, 870 .udt_dimm_subchan = UINT8_MAX, 871 .udt_dimm_rm = 0, 872 .udt_dimm_cs = 0 873 }, { 874 .udt_desc = "2 DPC 2R no ilv/hash (1)", 875 .udt_umc = &zen_umc_chan_no_hash, 876 .udt_pa = 0x800000000, 877 .udt_pass = B_TRUE, 878 .udt_norm_addr = 0x800000000, 879 .udt_sock = 0, 880 .udt_die = 0, 881 .udt_comp = 1, 882 .udt_dimm_no = 0, 883 .udt_dimm_col = 0, 884 .udt_dimm_row = 0, 885 .udt_dimm_bank = 0, 886 .udt_dimm_bank_group = 0, 887 .udt_dimm_subchan = UINT8_MAX, 888 .udt_dimm_rm = 0, 889 .udt_dimm_cs = 1 890 }, { 891 .udt_desc = "2 DPC 2R no ilv/hash (2)", 892 .udt_umc = &zen_umc_chan_no_hash, 893 .udt_pa = 0x1000000000, 894 .udt_pass = B_TRUE, 895 .udt_norm_addr = 0x1000000000, 896 .udt_sock = 0, 897 .udt_die = 0, 898 .udt_comp = 1, 899 .udt_dimm_no = 1, 900 .udt_dimm_col = 0, 901 .udt_dimm_row = 0, 902 .udt_dimm_bank = 0, 903 .udt_dimm_bank_group = 0, 904 .udt_dimm_subchan = UINT8_MAX, 905 .udt_dimm_rm = 0, 906 .udt_dimm_cs = 0 907 }, { 908 .udt_desc = "2 DPC 2R no ilv/hash (3)", 909 .udt_umc = &zen_umc_chan_no_hash, 910 .udt_pa = 0x1800000000, 911 .udt_pass = B_TRUE, 912 .udt_norm_addr = 0x1800000000, 913 .udt_sock = 0, 914 .udt_die = 0, 915 .udt_comp = 1, 916 .udt_dimm_no = 1, 917 .udt_dimm_col = 0, 918 .udt_dimm_row = 0, 919 .udt_dimm_bank = 0, 920 .udt_dimm_bank_group = 0, 921 .udt_dimm_subchan = UINT8_MAX, 922 .udt_dimm_rm = 0, 923 .udt_dimm_cs = 1 924 }, { 925 .udt_desc = "2 DPC 2R no ilv/hash (4)", 926 .udt_umc = &zen_umc_chan_no_hash, 927 .udt_pa = 0x0ff1ff120, 928 .udt_pass = B_TRUE, 929 .udt_norm_addr = 0x0ff1ff120, 930 .udt_sock = 0, 931 .udt_die = 0, 932 .udt_comp = 1, 933 .udt_dimm_no = 0, 934 .udt_dimm_col = 0x224, 935 .udt_dimm_row = 0x7f8f, 936 .udt_dimm_bank = 3, 937 .udt_dimm_bank_group = 3, 938 .udt_dimm_subchan = UINT8_MAX, 939 .udt_dimm_rm = 0, 940 .udt_dimm_cs = 0 941 }, { 942 .udt_desc = "2 DPC 2R no ilv/hash (5)", 943 .udt_umc = &zen_umc_chan_no_hash, 944 .udt_pa = 0x8ff4ff500, 945 .udt_pass = B_TRUE, 946 .udt_norm_addr = 0x8ff4ff500, 947 .udt_sock = 0, 948 .udt_die = 0, 949 .udt_comp = 1, 950 .udt_dimm_no = 0, 951 .udt_dimm_col = 0x2a0, 952 .udt_dimm_row = 0x7fa7, 953 .udt_dimm_bank = 3, 954 .udt_dimm_bank_group = 3, 955 .udt_dimm_subchan = UINT8_MAX, 956 .udt_dimm_rm = 0, 957 .udt_dimm_cs = 1 958 }, { 959 .udt_desc = "2 DPC 2R no ilv/hash (6)", 960 .udt_umc = &zen_umc_chan_no_hash, 961 .udt_pa = 0x10ff6ff700, 962 .udt_pass = B_TRUE, 963 .udt_norm_addr = 0x10ff6ff700, 964 .udt_sock = 0, 965 .udt_die = 0, 966 .udt_comp = 1, 967 .udt_dimm_no = 1, 968 .udt_dimm_col = 0x2e0, 969 .udt_dimm_row = 0x7fb7, 970 .udt_dimm_bank = 3, 971 .udt_dimm_bank_group = 3, 972 .udt_dimm_subchan = UINT8_MAX, 973 .udt_dimm_rm = 0, 974 .udt_dimm_cs = 0 975 }, { 976 .udt_desc = "2 DPC 2R no ilv/hash (7)", 977 .udt_umc = &zen_umc_chan_no_hash, 978 .udt_pa = 0x18ff8ff102, 979 .udt_pass = B_TRUE, 980 .udt_norm_addr = 0x18ff8ff102, 981 .udt_sock = 0, 982 .udt_die = 0, 983 .udt_comp = 1, 984 .udt_dimm_no = 1, 985 .udt_dimm_col = 0x220, 986 .udt_dimm_row = 0x7fc7, 987 .udt_dimm_bank = 3, 988 .udt_dimm_bank_group = 3, 989 .udt_dimm_subchan = UINT8_MAX, 990 .udt_dimm_rm = 0, 991 .udt_dimm_cs = 1 992 }, { 993 .udt_desc = "2 DPC 2R no hash, rank ilv (0)", 994 .udt_umc = &zen_umc_chan_ilv, 995 .udt_pa = 0x0, 996 .udt_pass = B_TRUE, 997 .udt_norm_addr = 0x0, 998 .udt_sock = 0, 999 .udt_die = 0, 1000 .udt_comp = 1, 1001 .udt_dimm_no = 0, 1002 .udt_dimm_col = 0, 1003 .udt_dimm_row = 0, 1004 .udt_dimm_bank = 0, 1005 .udt_dimm_bank_group = 0, 1006 .udt_dimm_subchan = UINT8_MAX, 1007 .udt_dimm_rm = 0, 1008 .udt_dimm_cs = 0 1009 }, { 1010 .udt_desc = "2 DPC 2R no hash, rank ilv (1)", 1011 .udt_umc = &zen_umc_chan_ilv, 1012 .udt_pa = 0x20000, 1013 .udt_pass = B_TRUE, 1014 .udt_norm_addr = 0x20000, 1015 .udt_sock = 0, 1016 .udt_die = 0, 1017 .udt_comp = 1, 1018 .udt_dimm_no = 0, 1019 .udt_dimm_col = 0, 1020 .udt_dimm_row = 0, 1021 .udt_dimm_bank = 0, 1022 .udt_dimm_bank_group = 0, 1023 .udt_dimm_subchan = UINT8_MAX, 1024 .udt_dimm_rm = 0, 1025 .udt_dimm_cs = 1 1026 }, { 1027 .udt_desc = "2 DPC 2R no hash, rank ilv (2)", 1028 .udt_umc = &zen_umc_chan_ilv, 1029 .udt_pa = 0x40000, 1030 .udt_pass = B_TRUE, 1031 .udt_norm_addr = 0x40000, 1032 .udt_sock = 0, 1033 .udt_die = 0, 1034 .udt_comp = 1, 1035 .udt_dimm_no = 1, 1036 .udt_dimm_col = 0, 1037 .udt_dimm_row = 0, 1038 .udt_dimm_bank = 0, 1039 .udt_dimm_bank_group = 0, 1040 .udt_dimm_subchan = UINT8_MAX, 1041 .udt_dimm_rm = 0, 1042 .udt_dimm_cs = 0 1043 }, { 1044 .udt_desc = "2 DPC 2R no hash, rank ilv (3)", 1045 .udt_umc = &zen_umc_chan_ilv, 1046 .udt_pa = 0x60000, 1047 .udt_pass = B_TRUE, 1048 .udt_norm_addr = 0x60000, 1049 .udt_sock = 0, 1050 .udt_die = 0, 1051 .udt_comp = 1, 1052 .udt_dimm_no = 1, 1053 .udt_dimm_col = 0, 1054 .udt_dimm_row = 0, 1055 .udt_dimm_bank = 0, 1056 .udt_dimm_bank_group = 0, 1057 .udt_dimm_subchan = UINT8_MAX, 1058 .udt_dimm_rm = 0, 1059 .udt_dimm_cs = 1 1060 }, { 1061 .udt_desc = "2 DPC 2R no hash, rank ilv (4)", 1062 .udt_umc = &zen_umc_chan_ilv, 1063 .udt_pa = 0xe1be12e00, 1064 .udt_pass = B_TRUE, 1065 .udt_norm_addr = 0xe1be12e00, 1066 .udt_sock = 0, 1067 .udt_die = 0, 1068 .udt_comp = 1, 1069 .udt_dimm_no = 0, 1070 .udt_dimm_col = 0x1c0, 1071 .udt_dimm_row = 0x1c37c, 1072 .udt_dimm_bank = 2, 1073 .udt_dimm_bank_group = 1, 1074 .udt_dimm_subchan = UINT8_MAX, 1075 .udt_dimm_rm = 0, 1076 .udt_dimm_cs = 0 1077 }, { 1078 .udt_desc = "2 DPC 2R no hash, rank ilv (5)", 1079 .udt_umc = &zen_umc_chan_ilv, 1080 .udt_pa = 0x1fffffffff, 1081 .udt_pass = B_TRUE, 1082 .udt_norm_addr = 0x1fffffffff, 1083 .udt_sock = 0, 1084 .udt_die = 0, 1085 .udt_comp = 1, 1086 .udt_dimm_no = 1, 1087 .udt_dimm_col = 0x3ff, 1088 .udt_dimm_row = 0x3ffff, 1089 .udt_dimm_bank = 3, 1090 .udt_dimm_bank_group = 3, 1091 .udt_dimm_subchan = UINT8_MAX, 1092 .udt_dimm_rm = 0, 1093 .udt_dimm_cs = 1 1094 }, 1095 /* 1096 * Test the CS hashing by first going back and using bits that aren't part of 1097 * the CS hash modification, e.g. the same 4 interleaving case that we hit 1098 * earlier. Next, we go through and tweak things that would normally go to a 1099 * given CS originally by tweaking the bits that would be used in a hash and 1100 * prove that they go elsewhere. 1101 */ 1102 { 1103 .udt_desc = "2 DPC 2R cs hash, rank ilv (0)", 1104 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1105 .udt_pa = 0x0, 1106 .udt_pass = B_TRUE, 1107 .udt_norm_addr = 0x0, 1108 .udt_sock = 0, 1109 .udt_die = 0, 1110 .udt_comp = 1, 1111 .udt_dimm_no = 0, 1112 .udt_dimm_col = 0, 1113 .udt_dimm_row = 0, 1114 .udt_dimm_bank = 0, 1115 .udt_dimm_bank_group = 0, 1116 .udt_dimm_subchan = UINT8_MAX, 1117 .udt_dimm_rm = 0, 1118 .udt_dimm_cs = 0 1119 }, { 1120 .udt_desc = "2 DPC 2R cs hash, rank ilv (1)", 1121 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1122 .udt_pa = 0x20000, 1123 .udt_pass = B_TRUE, 1124 .udt_norm_addr = 0x20000, 1125 .udt_sock = 0, 1126 .udt_die = 0, 1127 .udt_comp = 1, 1128 .udt_dimm_no = 0, 1129 .udt_dimm_col = 0, 1130 .udt_dimm_row = 0, 1131 .udt_dimm_bank = 0, 1132 .udt_dimm_bank_group = 0, 1133 .udt_dimm_subchan = UINT8_MAX, 1134 .udt_dimm_rm = 0, 1135 .udt_dimm_cs = 1 1136 }, { 1137 .udt_desc = "2 DPC 2R cs hash, rank ilv (2)", 1138 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1139 .udt_pa = 0x40000, 1140 .udt_pass = B_TRUE, 1141 .udt_norm_addr = 0x40000, 1142 .udt_sock = 0, 1143 .udt_die = 0, 1144 .udt_comp = 1, 1145 .udt_dimm_no = 1, 1146 .udt_dimm_col = 0, 1147 .udt_dimm_row = 0, 1148 .udt_dimm_bank = 0, 1149 .udt_dimm_bank_group = 0, 1150 .udt_dimm_subchan = UINT8_MAX, 1151 .udt_dimm_rm = 0, 1152 .udt_dimm_cs = 0 1153 }, { 1154 .udt_desc = "2 DPC 2R cs hash, rank ilv (3)", 1155 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1156 .udt_pa = 0x60000, 1157 .udt_pass = B_TRUE, 1158 .udt_norm_addr = 0x60000, 1159 .udt_sock = 0, 1160 .udt_die = 0, 1161 .udt_comp = 1, 1162 .udt_dimm_no = 1, 1163 .udt_dimm_col = 0, 1164 .udt_dimm_row = 0, 1165 .udt_dimm_bank = 0, 1166 .udt_dimm_bank_group = 0, 1167 .udt_dimm_subchan = UINT8_MAX, 1168 .udt_dimm_rm = 0, 1169 .udt_dimm_cs = 1 1170 }, { 1171 .udt_desc = "2 DPC 2R cs hash, rank ilv (4)", 1172 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1173 .udt_pa = 0x80000, 1174 .udt_pass = B_TRUE, 1175 .udt_norm_addr = 0x80000, 1176 .udt_sock = 0, 1177 .udt_die = 0, 1178 .udt_comp = 1, 1179 .udt_dimm_no = 0, 1180 .udt_dimm_col = 0, 1181 .udt_dimm_row = 1, 1182 .udt_dimm_bank = 0, 1183 .udt_dimm_bank_group = 0, 1184 .udt_dimm_subchan = UINT8_MAX, 1185 .udt_dimm_rm = 0, 1186 .udt_dimm_cs = 1 1187 }, { 1188 .udt_desc = "2 DPC 2R cs hash, rank ilv (5)", 1189 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1190 .udt_pa = 0x180000, 1191 .udt_pass = B_TRUE, 1192 .udt_norm_addr = 0x180000, 1193 .udt_sock = 0, 1194 .udt_die = 0, 1195 .udt_comp = 1, 1196 .udt_dimm_no = 1, 1197 .udt_dimm_col = 0, 1198 .udt_dimm_row = 3, 1199 .udt_dimm_bank = 0, 1200 .udt_dimm_bank_group = 0, 1201 .udt_dimm_subchan = UINT8_MAX, 1202 .udt_dimm_rm = 0, 1203 .udt_dimm_cs = 1 1204 }, { 1205 .udt_desc = "2 DPC 2R cs hash, rank ilv (6)", 1206 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1207 .udt_pa = 0x100000, 1208 .udt_pass = B_TRUE, 1209 .udt_norm_addr = 0x100000, 1210 .udt_sock = 0, 1211 .udt_die = 0, 1212 .udt_comp = 1, 1213 .udt_dimm_no = 1, 1214 .udt_dimm_col = 0, 1215 .udt_dimm_row = 2, 1216 .udt_dimm_bank = 0, 1217 .udt_dimm_bank_group = 0, 1218 .udt_dimm_subchan = UINT8_MAX, 1219 .udt_dimm_rm = 0, 1220 .udt_dimm_cs = 0 1221 }, { 1222 .udt_desc = "2 DPC 2R cs hash, rank ilv (7)", 1223 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1224 .udt_pa = 0x18180000, 1225 .udt_pass = B_TRUE, 1226 .udt_norm_addr = 0x18180000, 1227 .udt_sock = 0, 1228 .udt_die = 0, 1229 .udt_comp = 1, 1230 .udt_dimm_no = 0, 1231 .udt_dimm_col = 0, 1232 .udt_dimm_row = 0x303, 1233 .udt_dimm_bank = 0, 1234 .udt_dimm_bank_group = 0, 1235 .udt_dimm_subchan = UINT8_MAX, 1236 .udt_dimm_rm = 0, 1237 .udt_dimm_cs = 0 1238 }, { 1239 .udt_desc = "2 DPC 2R cs hash, rank ilv (8)", 1240 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1241 .udt_pa = 0x181a0000, 1242 .udt_pass = B_TRUE, 1243 .udt_norm_addr = 0x181a0000, 1244 .udt_sock = 0, 1245 .udt_die = 0, 1246 .udt_comp = 1, 1247 .udt_dimm_no = 0, 1248 .udt_dimm_col = 0, 1249 .udt_dimm_row = 0x303, 1250 .udt_dimm_bank = 0, 1251 .udt_dimm_bank_group = 0, 1252 .udt_dimm_subchan = UINT8_MAX, 1253 .udt_dimm_rm = 0, 1254 .udt_dimm_cs = 1 1255 }, { 1256 .udt_desc = "2 DPC 2R cs hash, rank ilv (9)", 1257 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1258 .udt_pa = 0x181c0000, 1259 .udt_pass = B_TRUE, 1260 .udt_norm_addr = 0x181c0000, 1261 .udt_sock = 0, 1262 .udt_die = 0, 1263 .udt_comp = 1, 1264 .udt_dimm_no = 1, 1265 .udt_dimm_col = 0, 1266 .udt_dimm_row = 0x303, 1267 .udt_dimm_bank = 0, 1268 .udt_dimm_bank_group = 0, 1269 .udt_dimm_subchan = UINT8_MAX, 1270 .udt_dimm_rm = 0, 1271 .udt_dimm_cs = 0 1272 }, { 1273 .udt_desc = "2 DPC 2R cs hash, rank ilv (10)", 1274 .udt_umc = &zen_umc_chan_ilv_cs_hash, 1275 .udt_pa = 0x181e0000, 1276 .udt_pass = B_TRUE, 1277 .udt_norm_addr = 0x181e0000, 1278 .udt_sock = 0, 1279 .udt_die = 0, 1280 .udt_comp = 1, 1281 .udt_dimm_no = 1, 1282 .udt_dimm_col = 0, 1283 .udt_dimm_row = 0x303, 1284 .udt_dimm_bank = 0, 1285 .udt_dimm_bank_group = 0, 1286 .udt_dimm_subchan = UINT8_MAX, 1287 .udt_dimm_rm = 0, 1288 .udt_dimm_cs = 1 1289 }, 1290 /* 1291 * For the bank hash we first prove that we can target a given row/column in 1292 * each bank and bank group without hashing (this leads to a total of 16 1293 * combinations). We then later go back and start tweaking the row/column to 1294 * change which bank and group we end up in. 1295 */ 1296 { 1297 .udt_desc = "2 DPC 2R bank hash, rank ilv (0)", 1298 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1299 .udt_pa = 0x0, 1300 .udt_pass = B_TRUE, 1301 .udt_norm_addr = 0x0, 1302 .udt_sock = 0, 1303 .udt_die = 0, 1304 .udt_comp = 1, 1305 .udt_dimm_no = 0, 1306 .udt_dimm_col = 0, 1307 .udt_dimm_row = 0, 1308 .udt_dimm_bank = 0, 1309 .udt_dimm_bank_group = 0, 1310 .udt_dimm_subchan = UINT8_MAX, 1311 .udt_dimm_rm = 0, 1312 .udt_dimm_cs = 0 1313 }, { 1314 .udt_desc = "2 DPC 2R bank hash, rank ilv (1)", 1315 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1316 .udt_pa = 0x8000, 1317 .udt_pass = B_TRUE, 1318 .udt_norm_addr = 0x8000, 1319 .udt_sock = 0, 1320 .udt_die = 0, 1321 .udt_comp = 1, 1322 .udt_dimm_no = 0, 1323 .udt_dimm_col = 0, 1324 .udt_dimm_row = 0, 1325 .udt_dimm_bank = 1, 1326 .udt_dimm_bank_group = 0, 1327 .udt_dimm_subchan = UINT8_MAX, 1328 .udt_dimm_rm = 0, 1329 .udt_dimm_cs = 0 1330 }, { 1331 .udt_desc = "2 DPC 2R bank hash, rank ilv (2)", 1332 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1333 .udt_pa = 0x10000, 1334 .udt_pass = B_TRUE, 1335 .udt_norm_addr = 0x10000, 1336 .udt_sock = 0, 1337 .udt_die = 0, 1338 .udt_comp = 1, 1339 .udt_dimm_no = 0, 1340 .udt_dimm_col = 0, 1341 .udt_dimm_row = 0, 1342 .udt_dimm_bank = 2, 1343 .udt_dimm_bank_group = 0, 1344 .udt_dimm_subchan = UINT8_MAX, 1345 .udt_dimm_rm = 0, 1346 .udt_dimm_cs = 0 1347 }, { 1348 .udt_desc = "2 DPC 2R bank hash, rank ilv (3)", 1349 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1350 .udt_pa = 0x18000, 1351 .udt_pass = B_TRUE, 1352 .udt_norm_addr = 0x18000, 1353 .udt_sock = 0, 1354 .udt_die = 0, 1355 .udt_comp = 1, 1356 .udt_dimm_no = 0, 1357 .udt_dimm_col = 0, 1358 .udt_dimm_row = 0, 1359 .udt_dimm_bank = 3, 1360 .udt_dimm_bank_group = 0, 1361 .udt_dimm_subchan = UINT8_MAX, 1362 .udt_dimm_rm = 0, 1363 .udt_dimm_cs = 0 1364 }, { 1365 .udt_desc = "2 DPC 2R bank hash, rank ilv (4)", 1366 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1367 .udt_pa = 0x2000, 1368 .udt_pass = B_TRUE, 1369 .udt_norm_addr = 0x2000, 1370 .udt_sock = 0, 1371 .udt_die = 0, 1372 .udt_comp = 1, 1373 .udt_dimm_no = 0, 1374 .udt_dimm_col = 0, 1375 .udt_dimm_row = 0, 1376 .udt_dimm_bank = 0, 1377 .udt_dimm_bank_group = 1, 1378 .udt_dimm_subchan = UINT8_MAX, 1379 .udt_dimm_rm = 0, 1380 .udt_dimm_cs = 0 1381 }, { 1382 .udt_desc = "2 DPC 2R bank hash, rank ilv (5)", 1383 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1384 .udt_pa = 0xa000, 1385 .udt_pass = B_TRUE, 1386 .udt_norm_addr = 0xa000, 1387 .udt_sock = 0, 1388 .udt_die = 0, 1389 .udt_comp = 1, 1390 .udt_dimm_no = 0, 1391 .udt_dimm_col = 0, 1392 .udt_dimm_row = 0, 1393 .udt_dimm_bank = 1, 1394 .udt_dimm_bank_group = 1, 1395 .udt_dimm_subchan = UINT8_MAX, 1396 .udt_dimm_rm = 0, 1397 .udt_dimm_cs = 0 1398 }, { 1399 .udt_desc = "2 DPC 2R bank hash, rank ilv (6)", 1400 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1401 .udt_pa = 0x12000, 1402 .udt_pass = B_TRUE, 1403 .udt_norm_addr = 0x12000, 1404 .udt_sock = 0, 1405 .udt_die = 0, 1406 .udt_comp = 1, 1407 .udt_dimm_no = 0, 1408 .udt_dimm_col = 0, 1409 .udt_dimm_row = 0, 1410 .udt_dimm_bank = 2, 1411 .udt_dimm_bank_group = 1, 1412 .udt_dimm_subchan = UINT8_MAX, 1413 .udt_dimm_rm = 0, 1414 .udt_dimm_cs = 0 1415 }, { 1416 .udt_desc = "2 DPC 2R bank hash, rank ilv (7)", 1417 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1418 .udt_pa = 0x1a000, 1419 .udt_pass = B_TRUE, 1420 .udt_norm_addr = 0x1a000, 1421 .udt_sock = 0, 1422 .udt_die = 0, 1423 .udt_comp = 1, 1424 .udt_dimm_no = 0, 1425 .udt_dimm_col = 0, 1426 .udt_dimm_row = 0, 1427 .udt_dimm_bank = 3, 1428 .udt_dimm_bank_group = 1, 1429 .udt_dimm_subchan = UINT8_MAX, 1430 .udt_dimm_rm = 0, 1431 .udt_dimm_cs = 0 1432 }, { 1433 .udt_desc = "2 DPC 2R bank hash, rank ilv (8)", 1434 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1435 .udt_pa = 0x4000, 1436 .udt_pass = B_TRUE, 1437 .udt_norm_addr = 0x4000, 1438 .udt_sock = 0, 1439 .udt_die = 0, 1440 .udt_comp = 1, 1441 .udt_dimm_no = 0, 1442 .udt_dimm_col = 0, 1443 .udt_dimm_row = 0, 1444 .udt_dimm_bank = 0, 1445 .udt_dimm_bank_group = 2, 1446 .udt_dimm_subchan = UINT8_MAX, 1447 .udt_dimm_rm = 0, 1448 .udt_dimm_cs = 0 1449 }, { 1450 .udt_desc = "2 DPC 2R bank hash, rank ilv (9)", 1451 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1452 .udt_pa = 0xc000, 1453 .udt_pass = B_TRUE, 1454 .udt_norm_addr = 0xc000, 1455 .udt_sock = 0, 1456 .udt_die = 0, 1457 .udt_comp = 1, 1458 .udt_dimm_no = 0, 1459 .udt_dimm_col = 0, 1460 .udt_dimm_row = 0, 1461 .udt_dimm_bank = 1, 1462 .udt_dimm_bank_group = 2, 1463 .udt_dimm_subchan = UINT8_MAX, 1464 .udt_dimm_rm = 0, 1465 .udt_dimm_cs = 0 1466 }, { 1467 .udt_desc = "2 DPC 2R bank hash, rank ilv (10)", 1468 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1469 .udt_pa = 0x14000, 1470 .udt_pass = B_TRUE, 1471 .udt_norm_addr = 0x14000, 1472 .udt_sock = 0, 1473 .udt_die = 0, 1474 .udt_comp = 1, 1475 .udt_dimm_no = 0, 1476 .udt_dimm_col = 0, 1477 .udt_dimm_row = 0, 1478 .udt_dimm_bank = 2, 1479 .udt_dimm_bank_group = 2, 1480 .udt_dimm_subchan = UINT8_MAX, 1481 .udt_dimm_rm = 0, 1482 .udt_dimm_cs = 0 1483 }, { 1484 .udt_desc = "2 DPC 2R bank hash, rank ilv (11)", 1485 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1486 .udt_pa = 0x1c000, 1487 .udt_pass = B_TRUE, 1488 .udt_norm_addr = 0x1c000, 1489 .udt_sock = 0, 1490 .udt_die = 0, 1491 .udt_comp = 1, 1492 .udt_dimm_no = 0, 1493 .udt_dimm_col = 0, 1494 .udt_dimm_row = 0, 1495 .udt_dimm_bank = 3, 1496 .udt_dimm_bank_group = 2, 1497 .udt_dimm_subchan = UINT8_MAX, 1498 .udt_dimm_rm = 0, 1499 .udt_dimm_cs = 0 1500 }, { 1501 .udt_desc = "2 DPC 2R bank hash, rank ilv (12)", 1502 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1503 .udt_pa = 0x6000, 1504 .udt_pass = B_TRUE, 1505 .udt_norm_addr = 0x6000, 1506 .udt_sock = 0, 1507 .udt_die = 0, 1508 .udt_comp = 1, 1509 .udt_dimm_no = 0, 1510 .udt_dimm_col = 0, 1511 .udt_dimm_row = 0, 1512 .udt_dimm_bank = 0, 1513 .udt_dimm_bank_group = 3, 1514 .udt_dimm_subchan = UINT8_MAX, 1515 .udt_dimm_rm = 0, 1516 .udt_dimm_cs = 0 1517 }, { 1518 .udt_desc = "2 DPC 2R bank hash, rank ilv (13)", 1519 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1520 .udt_pa = 0xe000, 1521 .udt_pass = B_TRUE, 1522 .udt_norm_addr = 0xe000, 1523 .udt_sock = 0, 1524 .udt_die = 0, 1525 .udt_comp = 1, 1526 .udt_dimm_no = 0, 1527 .udt_dimm_col = 0, 1528 .udt_dimm_row = 0, 1529 .udt_dimm_bank = 1, 1530 .udt_dimm_bank_group = 3, 1531 .udt_dimm_subchan = UINT8_MAX, 1532 .udt_dimm_rm = 0, 1533 .udt_dimm_cs = 0 1534 }, { 1535 .udt_desc = "2 DPC 2R bank hash, rank ilv (14)", 1536 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1537 .udt_pa = 0x16000, 1538 .udt_pass = B_TRUE, 1539 .udt_norm_addr = 0x16000, 1540 .udt_sock = 0, 1541 .udt_die = 0, 1542 .udt_comp = 1, 1543 .udt_dimm_no = 0, 1544 .udt_dimm_col = 0, 1545 .udt_dimm_row = 0, 1546 .udt_dimm_bank = 2, 1547 .udt_dimm_bank_group = 3, 1548 .udt_dimm_subchan = UINT8_MAX, 1549 .udt_dimm_rm = 0, 1550 .udt_dimm_cs = 0 1551 }, { 1552 .udt_desc = "2 DPC 2R bank hash, rank ilv (15)", 1553 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1554 .udt_pa = 0x1e000, 1555 .udt_pass = B_TRUE, 1556 .udt_norm_addr = 0x1e000, 1557 .udt_sock = 0, 1558 .udt_die = 0, 1559 .udt_comp = 1, 1560 .udt_dimm_no = 0, 1561 .udt_dimm_col = 0, 1562 .udt_dimm_row = 0, 1563 .udt_dimm_bank = 3, 1564 .udt_dimm_bank_group = 3, 1565 .udt_dimm_subchan = UINT8_MAX, 1566 .udt_dimm_rm = 0, 1567 .udt_dimm_cs = 0 1568 }, { 1569 .udt_desc = "2 DPC 2R bank hash, rank ilv (16)", 1570 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1571 .udt_pa = 0x79c000, 1572 .udt_pass = B_TRUE, 1573 .udt_norm_addr = 0x79c000, 1574 .udt_sock = 0, 1575 .udt_die = 0, 1576 .udt_comp = 1, 1577 .udt_dimm_no = 0, 1578 .udt_dimm_col = 0, 1579 .udt_dimm_row = 0xf, 1580 .udt_dimm_bank = 0, 1581 .udt_dimm_bank_group = 1, 1582 .udt_dimm_subchan = UINT8_MAX, 1583 .udt_dimm_rm = 0, 1584 .udt_dimm_cs = 0 1585 }, { 1586 .udt_desc = "2 DPC 2R bank hash, rank ilv (17)", 1587 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1588 .udt_pa = 0x7f9c000, 1589 .udt_pass = B_TRUE, 1590 .udt_norm_addr = 0x7f9c000, 1591 .udt_sock = 0, 1592 .udt_die = 0, 1593 .udt_comp = 1, 1594 .udt_dimm_no = 0, 1595 .udt_dimm_col = 0, 1596 .udt_dimm_row = 0xff, 1597 .udt_dimm_bank = 3, 1598 .udt_dimm_bank_group = 2, 1599 .udt_dimm_subchan = UINT8_MAX, 1600 .udt_dimm_rm = 0, 1601 .udt_dimm_cs = 0 1602 }, { 1603 .udt_desc = "2 DPC 2R bank hash, rank ilv (18)", 1604 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1605 .udt_pa = 0x7ff9c000, 1606 .udt_pass = B_TRUE, 1607 .udt_norm_addr = 0x7ff9c000, 1608 .udt_sock = 0, 1609 .udt_die = 0, 1610 .udt_comp = 1, 1611 .udt_dimm_no = 0, 1612 .udt_dimm_col = 0, 1613 .udt_dimm_row = 0xfff, 1614 .udt_dimm_bank = 0, 1615 .udt_dimm_bank_group = 1, 1616 .udt_dimm_subchan = UINT8_MAX, 1617 .udt_dimm_rm = 0, 1618 .udt_dimm_cs = 0 1619 }, { 1620 .udt_desc = "2 DPC 2R bank hash, rank ilv (19)", 1621 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1622 .udt_pa = 0x71c000, 1623 .udt_pass = B_TRUE, 1624 .udt_norm_addr = 0x71c000, 1625 .udt_sock = 0, 1626 .udt_die = 0, 1627 .udt_comp = 1, 1628 .udt_dimm_no = 0, 1629 .udt_dimm_col = 0, 1630 .udt_dimm_row = 0xe, 1631 .udt_dimm_bank = 0, 1632 .udt_dimm_bank_group = 0, 1633 .udt_dimm_subchan = UINT8_MAX, 1634 .udt_dimm_rm = 0, 1635 .udt_dimm_cs = 0 1636 }, { 1637 .udt_desc = "2 DPC 2R bank hash, rank ilv (20)", 1638 .udt_umc = &zen_umc_chan_ilv_bank_hash, 1639 .udt_pa = 0x71c118, 1640 .udt_pass = B_TRUE, 1641 .udt_norm_addr = 0x71c118, 1642 .udt_sock = 0, 1643 .udt_die = 0, 1644 .udt_comp = 1, 1645 .udt_dimm_no = 0, 1646 .udt_dimm_col = 0x23, 1647 .udt_dimm_row = 0xe, 1648 .udt_dimm_bank = 0, 1649 .udt_dimm_bank_group = 0, 1650 .udt_dimm_subchan = UINT8_MAX, 1651 .udt_dimm_rm = 0, 1652 .udt_dimm_cs = 0 1653 }, 1654 /* 1655 * Bank swapping. We basically do a few sanity tests on this just to make sure 1656 * the right bits are triggering things here in the first DIMM/rank. 1657 */ 1658 { 1659 .udt_desc = "2 DPC 2R bank swap, rank ilv (0)", 1660 .udt_umc = &zen_umc_chan_ilv_bank_swap, 1661 .udt_pa = 0x4247, 1662 .udt_pass = B_TRUE, 1663 .udt_norm_addr = 0x4247, 1664 .udt_sock = 0, 1665 .udt_die = 0, 1666 .udt_comp = 1, 1667 .udt_dimm_no = 0, 1668 .udt_dimm_col = 0x80, 1669 .udt_dimm_row = 0, 1670 .udt_dimm_bank = 1, 1671 .udt_dimm_bank_group = 1, 1672 .udt_dimm_subchan = UINT8_MAX, 1673 .udt_dimm_rm = 0, 1674 .udt_dimm_cs = 0 1675 }, { 1676 .udt_desc = "2 DPC 2R bank swap, rank ilv (1)", 1677 .udt_umc = &zen_umc_chan_ilv_bank_swap, 1678 .udt_pa = 0xff6214247, 1679 .udt_pass = B_TRUE, 1680 .udt_norm_addr = 0xff6214247, 1681 .udt_sock = 0, 1682 .udt_die = 0, 1683 .udt_comp = 1, 1684 .udt_dimm_no = 0, 1685 .udt_dimm_col = 0x280, 1686 .udt_dimm_row = 0x1fec4, 1687 .udt_dimm_bank = 1, 1688 .udt_dimm_bank_group = 1, 1689 .udt_dimm_subchan = UINT8_MAX, 1690 .udt_dimm_rm = 0, 1691 .udt_dimm_cs = 0 1692 }, { 1693 .udt_desc = "Basic DDR5 Sub-channel (0)", 1694 .udt_umc = &zen_umc_chan_subchan_no_hash, 1695 .udt_pa = 0x0, 1696 .udt_pass = B_TRUE, 1697 .udt_norm_addr = 0x0, 1698 .udt_sock = 0, 1699 .udt_die = 0, 1700 .udt_comp = 1, 1701 .udt_dimm_no = 0, 1702 .udt_dimm_col = 0x0, 1703 .udt_dimm_row = 0x0, 1704 .udt_dimm_bank = 0, 1705 .udt_dimm_bank_group = 0, 1706 .udt_dimm_subchan = 0, 1707 .udt_dimm_rm = 0, 1708 .udt_dimm_cs = 0 1709 }, { 1710 .udt_desc = "Basic DDR5 Sub-channel (1)", 1711 .udt_umc = &zen_umc_chan_subchan_no_hash, 1712 .udt_pa = 0x9999, 1713 .udt_pass = B_TRUE, 1714 .udt_norm_addr = 0x9999, 1715 .udt_sock = 0, 1716 .udt_die = 0, 1717 .udt_comp = 1, 1718 .udt_dimm_no = 0, 1719 .udt_dimm_col = 0x336, 1720 .udt_dimm_row = 0x0, 1721 .udt_dimm_bank = 0, 1722 .udt_dimm_bank_group = 1, 1723 .udt_dimm_subchan = 0, 1724 .udt_dimm_rm = 0, 1725 .udt_dimm_cs = 0 1726 }, { 1727 .udt_desc = "Basic DDR5 Sub-channel (2)", 1728 .udt_umc = &zen_umc_chan_subchan_no_hash, 1729 .udt_pa = 0x99d9, 1730 .udt_pass = B_TRUE, 1731 .udt_norm_addr = 0x99d9, 1732 .udt_sock = 0, 1733 .udt_die = 0, 1734 .udt_comp = 1, 1735 .udt_dimm_no = 0, 1736 .udt_dimm_col = 0x336, 1737 .udt_dimm_row = 0x0, 1738 .udt_dimm_bank = 0, 1739 .udt_dimm_bank_group = 1, 1740 .udt_dimm_subchan = 1, 1741 .udt_dimm_rm = 0, 1742 .udt_dimm_cs = 0 1743 }, { 1744 .udt_desc = NULL 1745 } }; 1746