1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 /* 17 * This provides a simple case with one DIMM, one channel, one socket, and no 18 * interleaving, and no DRAM hole. This sends everything to exactly one DIMM. In 19 * particular we have configurations with the following DIMM sizes: 20 * 21 * o 16 GiB RDIMM (1 rank) 22 * o 64 GiB RDIMM (2 rank) 23 * 24 * There is no hashing going on in the channel in any way here (e.g. no CS 25 * interleaving). This is basically simple linear mappings. 26 */ 27 28 #include "zen_umc_test.h" 29 30 static const zen_umc_t zen_umc_basic_1p1c1d = { 31 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 32 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 33 .umc_df_rev = DF_REV_3, 34 /* Per milan_decomp */ 35 .umc_decomp = { 36 .dfd_sock_mask = 0x01, 37 .dfd_die_mask = 0x00, 38 .dfd_node_mask = 0x20, 39 .dfd_comp_mask = 0x1f, 40 .dfd_sock_shift = 0, 41 .dfd_die_shift = 0, 42 .dfd_node_shift = 5, 43 .dfd_comp_shift = 0 44 }, 45 .umc_ndfs = 1, 46 .umc_dfs = { { 47 .zud_dfno = 0, 48 .zud_ccm_inst = 0, 49 .zud_dram_nrules = 1, 50 .zud_nchan = 1, 51 .zud_cs_nremap = 0, 52 .zud_hole_base = 0, 53 .zud_rules = { { 54 .ddr_flags = DF_DRAM_F_VALID, 55 .ddr_base = 0, 56 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 1024ULL, 57 .ddr_dest_fabid = 1, 58 .ddr_sock_ileave_bits = 0, 59 .ddr_die_ileave_bits = 0, 60 .ddr_addr_start = 9, 61 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 62 } }, 63 .zud_chan = { { 64 .chan_flags = UMC_CHAN_F_ECC_EN, 65 .chan_fabid = 1, 66 .chan_instid = 1, 67 .chan_logid = 0, 68 .chan_nrules = 1, 69 .chan_type = UMC_DIMM_T_DDR4, 70 .chan_rules = { { 71 .ddr_flags = DF_DRAM_F_VALID, 72 .ddr_base = 0, 73 .ddr_limit = 16ULL * 1024ULL * 1024ULL * 74 1024ULL, 75 .ddr_dest_fabid = 1, 76 .ddr_sock_ileave_bits = 0, 77 .ddr_die_ileave_bits = 0, 78 .ddr_addr_start = 9, 79 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 80 } }, 81 .chan_dimms = { { 82 .ud_flags = UMC_DIMM_F_VALID, 83 .ud_width = UMC_DIMM_W_X4, 84 .ud_kind = UMC_DIMM_K_RDIMM, 85 .ud_dimmno = 0, 86 .ud_cs = { { 87 .ucs_flags = UMC_CS_F_DECODE_EN, 88 .ucs_base = { 89 .udb_base = 0, 90 .udb_valid = B_TRUE 91 }, 92 .ucs_base_mask = 0x3ffffffff, 93 .ucs_nbanks = 0x4, 94 .ucs_ncol = 0xa, 95 .ucs_nrow_lo = 0x11, 96 .ucs_nbank_groups = 0x2, 97 .ucs_row_hi_bit = 0x18, 98 .ucs_row_low_bit = 0x11, 99 .ucs_bank_bits = { 0xf, 0x10, 0xd, 100 0xe }, 101 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 102 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 103 } } 104 } }, 105 } } 106 } } 107 }; 108 109 static const zen_umc_t zen_umc_basic_1p1c1d_64g = { 110 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 111 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 112 .umc_df_rev = DF_REV_3, 113 /* Per milan_decomp */ 114 .umc_decomp = { 115 .dfd_sock_mask = 0x01, 116 .dfd_die_mask = 0x00, 117 .dfd_node_mask = 0x20, 118 .dfd_comp_mask = 0x1f, 119 .dfd_sock_shift = 0, 120 .dfd_die_shift = 0, 121 .dfd_node_shift = 5, 122 .dfd_comp_shift = 0 123 }, 124 .umc_ndfs = 1, 125 .umc_dfs = { { 126 .zud_dfno = 0, 127 .zud_ccm_inst = 0, 128 .zud_dram_nrules = 1, 129 .zud_nchan = 1, 130 .zud_cs_nremap = 0, 131 .zud_hole_base = 0, 132 .zud_rules = { { 133 .ddr_flags = DF_DRAM_F_VALID, 134 .ddr_base = 0, 135 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 136 .ddr_dest_fabid = 1, 137 .ddr_sock_ileave_bits = 0, 138 .ddr_die_ileave_bits = 0, 139 .ddr_addr_start = 9, 140 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 141 } }, 142 .zud_chan = { { 143 .chan_flags = UMC_CHAN_F_ECC_EN, 144 .chan_fabid = 1, 145 .chan_instid = 1, 146 .chan_logid = 0, 147 .chan_nrules = 1, 148 .chan_type = UMC_DIMM_T_DDR4, 149 .chan_rules = { { 150 .ddr_flags = DF_DRAM_F_VALID, 151 .ddr_base = 0, 152 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 153 1024ULL, 154 .ddr_dest_fabid = 1, 155 .ddr_sock_ileave_bits = 0, 156 .ddr_die_ileave_bits = 0, 157 .ddr_addr_start = 9, 158 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 159 } }, 160 .chan_dimms = { { 161 .ud_flags = UMC_DIMM_F_VALID, 162 .ud_width = UMC_DIMM_W_X4, 163 .ud_kind = UMC_DIMM_K_RDIMM, 164 .ud_dimmno = 0, 165 .ud_cs = { { 166 .ucs_flags = UMC_CS_F_DECODE_EN, 167 .ucs_base = { 168 .udb_base = 0, 169 .udb_valid = B_TRUE 170 }, 171 .ucs_base_mask = 0x7ffffffff, 172 .ucs_nbanks = 0x4, 173 .ucs_ncol = 0xa, 174 .ucs_nrow_lo = 0x12, 175 .ucs_nbank_groups = 0x2, 176 .ucs_row_hi_bit = 0x18, 177 .ucs_row_low_bit = 0x11, 178 .ucs_bank_bits = { 0xf, 0x10, 0xd, 179 0xe }, 180 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 181 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 182 }, { 183 .ucs_flags = UMC_CS_F_DECODE_EN, 184 .ucs_base = { 185 .udb_base = 0x800000000, 186 .udb_valid = B_TRUE 187 }, 188 .ucs_base_mask = 0x7ffffffff, 189 .ucs_nbanks = 0x4, 190 .ucs_ncol = 0xa, 191 .ucs_nrow_lo = 0x12, 192 .ucs_nbank_groups = 0x2, 193 .ucs_row_hi_bit = 0x18, 194 .ucs_row_low_bit = 0x11, 195 .ucs_bank_bits = { 0xf, 0x10, 0xd, 196 0xe }, 197 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 198 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 199 } } 200 } }, 201 } } 202 } } 203 }; 204 205 const umc_decode_test_t zen_umc_test_basics[] = { { 206 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (0)", 207 .udt_umc = &zen_umc_basic_1p1c1d, 208 .udt_pa = 0, 209 .udt_pass = B_TRUE, 210 .udt_norm_addr = 0, 211 .udt_sock = 0, 212 .udt_die = 0, 213 .udt_comp = 1, 214 .udt_dimm_no = 0, 215 .udt_dimm_col = 0, 216 .udt_dimm_row = 0, 217 .udt_dimm_bank = 0, 218 .udt_dimm_bank_group = 0, 219 .udt_dimm_subchan = 0, 220 .udt_dimm_rm = 0, 221 .udt_dimm_cs = 0 222 }, { 223 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (1)", 224 .udt_umc = &zen_umc_basic_1p1c1d, 225 .udt_pa = 0x123, 226 .udt_pass = B_TRUE, 227 .udt_norm_addr = 0x123, 228 .udt_sock = 0, 229 .udt_die = 0, 230 .udt_comp = 1, 231 .udt_dimm_no = 0, 232 .udt_dimm_col = 0x24, 233 .udt_dimm_row = 0, 234 .udt_dimm_bank = 0, 235 .udt_dimm_bank_group = 0, 236 .udt_dimm_subchan = UINT8_MAX, 237 .udt_dimm_rm = 0, 238 .udt_dimm_cs = 0 239 }, { 240 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (2)", 241 .udt_umc = &zen_umc_basic_1p1c1d, 242 .udt_pa = 0x5000, 243 .udt_pass = B_TRUE, 244 .udt_norm_addr = 0x5000, 245 .udt_sock = 0, 246 .udt_die = 0, 247 .udt_comp = 1, 248 .udt_dimm_no = 0, 249 .udt_dimm_col = 0x200, 250 .udt_dimm_row = 0, 251 .udt_dimm_bank = 0x2, 252 .udt_dimm_bank_group = 0, 253 .udt_dimm_subchan = UINT8_MAX, 254 .udt_dimm_rm = 0, 255 .udt_dimm_cs = 0 256 }, { 257 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (3)", 258 .udt_umc = &zen_umc_basic_1p1c1d, 259 .udt_pa = 0x345678901, 260 .udt_pass = B_TRUE, 261 .udt_norm_addr = 0x345678901, 262 .udt_sock = 0, 263 .udt_die = 0, 264 .udt_comp = 1, 265 .udt_dimm_no = 0, 266 .udt_dimm_col = 0x120, 267 .udt_dimm_row = 0x1a2b3, 268 .udt_dimm_bank = 0, 269 .udt_dimm_bank_group = 0x3, 270 .udt_dimm_subchan = UINT8_MAX, 271 .udt_dimm_rm = 0, 272 .udt_dimm_cs = 0 273 }, { 274 .udt_desc = "decode basic single socket/channel/DIMM DDR4 (4)", 275 .udt_umc = &zen_umc_basic_1p1c1d, 276 .udt_pa = 0x3ffffffff, 277 .udt_pass = B_TRUE, 278 .udt_norm_addr = 0x3ffffffff, 279 .udt_sock = 0, 280 .udt_die = 0, 281 .udt_comp = 1, 282 .udt_dimm_no = 0, 283 .udt_dimm_col = 0x3ff, 284 .udt_dimm_row = 0x1ffff, 285 .udt_dimm_bank = 0x3, 286 .udt_dimm_bank_group = 0x3, 287 .udt_dimm_subchan = UINT8_MAX, 288 .udt_dimm_rm = 0, 289 .udt_dimm_cs = 0 290 }, { 291 .udt_desc = "single socket/channel/DIMM 2R DDR4 (0)", 292 .udt_umc = &zen_umc_basic_1p1c1d_64g, 293 .udt_pa = 0, 294 .udt_pass = B_TRUE, 295 .udt_norm_addr = 0, 296 .udt_sock = 0, 297 .udt_die = 0, 298 .udt_comp = 1, 299 .udt_dimm_no = 0, 300 .udt_dimm_col = 0, 301 .udt_dimm_row = 0, 302 .udt_dimm_bank = 0, 303 .udt_dimm_bank_group = 0, 304 .udt_dimm_subchan = 0, 305 .udt_dimm_rm = 0, 306 .udt_dimm_cs = 0 307 }, { 308 .udt_desc = "single socket/channel/DIMM 2R DDR4 (1)", 309 .udt_umc = &zen_umc_basic_1p1c1d_64g, 310 .udt_pa = 0x800000000, 311 .udt_pass = B_TRUE, 312 .udt_norm_addr = 0x800000000, 313 .udt_sock = 0, 314 .udt_die = 0, 315 .udt_comp = 1, 316 .udt_dimm_no = 0, 317 .udt_dimm_col = 0, 318 .udt_dimm_row = 0, 319 .udt_dimm_bank = 0, 320 .udt_dimm_bank_group = 0, 321 .udt_dimm_subchan = 0, 322 .udt_dimm_rm = 0, 323 .udt_dimm_cs = 1 324 }, { 325 .udt_desc = "single socket/channel/DIMM 2R DDR4 (2)", 326 .udt_umc = &zen_umc_basic_1p1c1d_64g, 327 .udt_pa = 0x876543210, 328 .udt_pass = B_TRUE, 329 .udt_norm_addr = 0x876543210, 330 .udt_sock = 0, 331 .udt_die = 0, 332 .udt_comp = 1, 333 .udt_dimm_no = 0, 334 .udt_dimm_col = 0x242, 335 .udt_dimm_row = 0x3b2a, 336 .udt_dimm_bank = 1, 337 .udt_dimm_bank_group = 0, 338 .udt_dimm_subchan = 0, 339 .udt_dimm_rm = 0, 340 .udt_dimm_cs = 1 341 }, { 342 .udt_desc = "single socket/channel/DIMM 2R DDR4 (3)", 343 .udt_umc = &zen_umc_basic_1p1c1d_64g, 344 .udt_pa = 0x076543210, 345 .udt_pass = B_TRUE, 346 .udt_norm_addr = 0x076543210, 347 .udt_sock = 0, 348 .udt_die = 0, 349 .udt_comp = 1, 350 .udt_dimm_no = 0, 351 .udt_dimm_col = 0x242, 352 .udt_dimm_row = 0x3b2a, 353 .udt_dimm_bank = 1, 354 .udt_dimm_bank_group = 0, 355 .udt_dimm_subchan = 0, 356 .udt_dimm_rm = 0, 357 .udt_dimm_cs = 0 358 }, { 359 .udt_desc = NULL 360 } }; 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