xref: /illumos-gate/usr/src/test/os-tests/tests/zen_umc/zen_umc_test_ilv.c (revision 0dd92943508086ca1800de461a7c66109737bcd5)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2023 Oxide Computer Company
14  */
15 
16 /*
17  * Test the basic interleave scenarios that don't involve hashing or non-powers
18  * of 2. Every DRAM channel we map to always has a single 16 GiB DIMM to keep
19  * things straightforward. For all of these designs, UMC channels are labeled
20  * consecutively. Note, there is no remapping going on here, that is saved for
21  * elsewhere. In particular we cover:
22  *
23  * o Channel Interleaving
24  * o Channel + Die Interleaving
25  * o Channel + Socket Interleaving
26  * o Channel + Die + Socket Interleaving
27  *
28  * Throughout these we end up trying to vary what the starting address here and
29  * we adjust the DF decomposition to try and be something close to an existing
30  * DF revision.
31  */
32 
33 #include "zen_umc_test.h"
34 
35 /*
36  * Our first version of this, 4-way channel interleaving.
37  */
38 static const zen_umc_t zen_umc_ilv_1p1d4c_4ch = {
39 	.umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL,
40 	.umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL,
41 	.umc_df_rev = DF_REV_3,
42 	.umc_decomp = {
43 		.dfd_sock_mask = 0x01,
44 		.dfd_die_mask = 0x00,
45 		.dfd_node_mask = 0x20,
46 		.dfd_comp_mask = 0x1f,
47 		.dfd_sock_shift = 0,
48 		.dfd_die_shift = 0,
49 		.dfd_node_shift = 5,
50 		.dfd_comp_shift = 0
51 	},
52 	.umc_ndfs = 1,
53 	.umc_dfs = { {
54 		.zud_dfno = 0,
55 		.zud_dram_nrules = 1,
56 		.zud_nchan = 4,
57 		.zud_cs_nremap = 0,
58 		.zud_hole_base = 0,
59 		.zud_rules = { {
60 			.ddr_flags = DF_DRAM_F_VALID,
61 			.ddr_base = 0,
62 			.ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL,
63 			.ddr_dest_fabid = 0,
64 			.ddr_sock_ileave_bits = 0,
65 			.ddr_die_ileave_bits = 0,
66 			.ddr_addr_start = 9,
67 			.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
68 		} },
69 		.zud_chan = { {
70 			.chan_flags = UMC_CHAN_F_ECC_EN,
71 			.chan_fabid = 0,
72 			.chan_instid = 0,
73 			.chan_logid = 0,
74 			.chan_nrules = 1,
75 			.chan_type = UMC_DIMM_T_DDR4,
76 			.chan_rules = { {
77 				.ddr_flags = DF_DRAM_F_VALID,
78 				.ddr_base = 0,
79 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
80 				    1024ULL,
81 				.ddr_dest_fabid = 0,
82 				.ddr_sock_ileave_bits = 0,
83 				.ddr_die_ileave_bits = 0,
84 				.ddr_addr_start = 9,
85 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
86 			} },
87 			.chan_dimms = { {
88 				.ud_flags = UMC_DIMM_F_VALID,
89 				.ud_width = UMC_DIMM_W_X4,
90 				.ud_kind = UMC_DIMM_K_RDIMM,
91 				.ud_dimmno = 0,
92 				.ud_cs = { {
93 					.ucs_base = {
94 						.udb_base = 0,
95 						.udb_valid = B_TRUE
96 					},
97 					.ucs_base_mask = 0x3ffffffff,
98 					.ucs_nbanks = 0x4,
99 					.ucs_ncol = 0xa,
100 					.ucs_nrow_lo = 0x11,
101 					.ucs_nbank_groups = 0x2,
102 					.ucs_row_hi_bit = 0x18,
103 					.ucs_row_low_bit = 0x11,
104 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
105 					    0xe },
106 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
107 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
108 				} }
109 			} },
110 		}, {
111 			.chan_flags = UMC_CHAN_F_ECC_EN,
112 			.chan_fabid = 1,
113 			.chan_instid = 1,
114 			.chan_logid = 1,
115 			.chan_nrules = 1,
116 			.chan_type = UMC_DIMM_T_DDR4,
117 			.chan_rules = { {
118 				.ddr_flags = DF_DRAM_F_VALID,
119 				.ddr_base = 0,
120 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
121 				    1024ULL,
122 				.ddr_dest_fabid = 0,
123 				.ddr_sock_ileave_bits = 0,
124 				.ddr_die_ileave_bits = 0,
125 				.ddr_addr_start = 9,
126 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
127 			} },
128 			.chan_dimms = { {
129 				.ud_flags = UMC_DIMM_F_VALID,
130 				.ud_width = UMC_DIMM_W_X4,
131 				.ud_kind = UMC_DIMM_K_RDIMM,
132 				.ud_dimmno = 0,
133 				.ud_cs = { {
134 					.ucs_base = {
135 						.udb_base = 0,
136 						.udb_valid = B_TRUE
137 					},
138 					.ucs_base_mask = 0x3ffffffff,
139 					.ucs_nbanks = 0x4,
140 					.ucs_ncol = 0xa,
141 					.ucs_nrow_lo = 0x11,
142 					.ucs_nbank_groups = 0x2,
143 					.ucs_row_hi_bit = 0x18,
144 					.ucs_row_low_bit = 0x11,
145 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
146 					    0xe },
147 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
148 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
149 				} }
150 			} },
151 		}, {
152 			.chan_flags = UMC_CHAN_F_ECC_EN,
153 			.chan_fabid = 2,
154 			.chan_instid = 2,
155 			.chan_logid = 2,
156 			.chan_nrules = 1,
157 			.chan_type = UMC_DIMM_T_DDR4,
158 			.chan_rules = { {
159 				.ddr_flags = DF_DRAM_F_VALID,
160 				.ddr_base = 0,
161 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
162 				    1024ULL,
163 				.ddr_dest_fabid = 0,
164 				.ddr_sock_ileave_bits = 0,
165 				.ddr_die_ileave_bits = 0,
166 				.ddr_addr_start = 9,
167 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
168 			} },
169 			.chan_dimms = { {
170 				.ud_flags = UMC_DIMM_F_VALID,
171 				.ud_width = UMC_DIMM_W_X4,
172 				.ud_kind = UMC_DIMM_K_RDIMM,
173 				.ud_dimmno = 0,
174 				.ud_cs = { {
175 					.ucs_base = {
176 						.udb_base = 0,
177 						.udb_valid = B_TRUE
178 					},
179 					.ucs_base_mask = 0x3ffffffff,
180 					.ucs_nbanks = 0x4,
181 					.ucs_ncol = 0xa,
182 					.ucs_nrow_lo = 0x11,
183 					.ucs_nbank_groups = 0x2,
184 					.ucs_row_hi_bit = 0x18,
185 					.ucs_row_low_bit = 0x11,
186 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
187 					    0xe },
188 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
189 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
190 				} }
191 			} },
192 		}, {
193 			.chan_flags = UMC_CHAN_F_ECC_EN,
194 			.chan_fabid = 3,
195 			.chan_instid = 3,
196 			.chan_logid = 3,
197 			.chan_nrules = 1,
198 			.chan_type = UMC_DIMM_T_DDR4,
199 			.chan_rules = { {
200 				.ddr_flags = DF_DRAM_F_VALID,
201 				.ddr_base = 0,
202 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
203 				    1024ULL,
204 				.ddr_dest_fabid = 0,
205 				.ddr_sock_ileave_bits = 0,
206 				.ddr_die_ileave_bits = 0,
207 				.ddr_addr_start = 9,
208 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
209 			} },
210 			.chan_dimms = { {
211 				.ud_flags = UMC_DIMM_F_VALID,
212 				.ud_width = UMC_DIMM_W_X4,
213 				.ud_kind = UMC_DIMM_K_RDIMM,
214 				.ud_dimmno = 0,
215 				.ud_cs = { {
216 					.ucs_base = {
217 						.udb_base = 0,
218 						.udb_valid = B_TRUE
219 					},
220 					.ucs_base_mask = 0x3ffffffff,
221 					.ucs_nbanks = 0x4,
222 					.ucs_ncol = 0xa,
223 					.ucs_nrow_lo = 0x11,
224 					.ucs_nbank_groups = 0x2,
225 					.ucs_row_hi_bit = 0x18,
226 					.ucs_row_low_bit = 0x11,
227 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
228 					    0xe },
229 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
230 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
231 				} }
232 			} },
233 		}  }
234 	} }
235 };
236 
237 /*
238  * 2P configuration with 4 channels each. We interleave across 2 sockets and 4
239  * channels. This uses a single rule.
240  */
241 static const zen_umc_t zen_umc_ilv_2p1d4c_2s4ch = {
242 	.umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL,
243 	.umc_tom2 = 128ULL * 1024ULL * 1024ULL * 1024ULL,
244 	.umc_df_rev = DF_REV_3,
245 	.umc_decomp = {
246 		.dfd_sock_mask = 0x01,
247 		.dfd_die_mask = 0x00,
248 		.dfd_node_mask = 0x20,
249 		.dfd_comp_mask = 0x1f,
250 		.dfd_sock_shift = 0,
251 		.dfd_die_shift = 0,
252 		.dfd_node_shift = 5,
253 		.dfd_comp_shift = 0
254 	},
255 	.umc_ndfs = 2,
256 	.umc_dfs = { {
257 		.zud_dfno = 0,
258 		.zud_dram_nrules = 1,
259 		.zud_nchan = 4,
260 		.zud_cs_nremap = 0,
261 		.zud_hole_base = 0,
262 		.zud_rules = { {
263 			.ddr_flags = DF_DRAM_F_VALID,
264 			.ddr_base = 0,
265 			.ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL,
266 			.ddr_dest_fabid = 0,
267 			.ddr_sock_ileave_bits = 1,
268 			.ddr_die_ileave_bits = 0,
269 			.ddr_addr_start = 10,
270 			.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
271 		} },
272 		.zud_chan = { {
273 			.chan_flags = UMC_CHAN_F_ECC_EN,
274 			.chan_fabid = 0,
275 			.chan_instid = 0,
276 			.chan_logid = 0,
277 			.chan_nrules = 1,
278 			.chan_type = UMC_DIMM_T_DDR4,
279 			.chan_rules = { {
280 				.ddr_flags = DF_DRAM_F_VALID,
281 				.ddr_base = 0,
282 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
283 				    1024ULL,
284 				.ddr_dest_fabid = 0,
285 				.ddr_sock_ileave_bits = 1,
286 				.ddr_die_ileave_bits = 0,
287 				.ddr_addr_start = 10,
288 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
289 			} },
290 			.chan_dimms = { {
291 				.ud_flags = UMC_DIMM_F_VALID,
292 				.ud_width = UMC_DIMM_W_X4,
293 				.ud_kind = UMC_DIMM_K_RDIMM,
294 				.ud_dimmno = 0,
295 				.ud_cs = { {
296 					.ucs_base = {
297 						.udb_base = 0,
298 						.udb_valid = B_TRUE
299 					},
300 					.ucs_base_mask = 0x3ffffffff,
301 					.ucs_nbanks = 0x4,
302 					.ucs_ncol = 0xa,
303 					.ucs_nrow_lo = 0x11,
304 					.ucs_nbank_groups = 0x2,
305 					.ucs_row_hi_bit = 0x18,
306 					.ucs_row_low_bit = 0x11,
307 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
308 					    0xe },
309 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
310 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
311 				} }
312 			} },
313 		}, {
314 			.chan_flags = UMC_CHAN_F_ECC_EN,
315 			.chan_fabid = 1,
316 			.chan_instid = 1,
317 			.chan_logid = 1,
318 			.chan_nrules = 1,
319 			.chan_type = UMC_DIMM_T_DDR4,
320 			.chan_rules = { {
321 				.ddr_flags = DF_DRAM_F_VALID,
322 				.ddr_base = 0,
323 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
324 				    1024ULL,
325 				.ddr_dest_fabid = 0,
326 				.ddr_sock_ileave_bits = 1,
327 				.ddr_die_ileave_bits = 0,
328 				.ddr_addr_start = 10,
329 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
330 			} },
331 			.chan_dimms = { {
332 				.ud_flags = UMC_DIMM_F_VALID,
333 				.ud_width = UMC_DIMM_W_X4,
334 				.ud_kind = UMC_DIMM_K_RDIMM,
335 				.ud_dimmno = 0,
336 				.ud_cs = { {
337 					.ucs_base = {
338 						.udb_base = 0,
339 						.udb_valid = B_TRUE
340 					},
341 					.ucs_base_mask = 0x3ffffffff,
342 					.ucs_nbanks = 0x4,
343 					.ucs_ncol = 0xa,
344 					.ucs_nrow_lo = 0x11,
345 					.ucs_nbank_groups = 0x2,
346 					.ucs_row_hi_bit = 0x18,
347 					.ucs_row_low_bit = 0x11,
348 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
349 					    0xe },
350 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
351 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
352 				} }
353 			} },
354 		}, {
355 			.chan_flags = UMC_CHAN_F_ECC_EN,
356 			.chan_fabid = 2,
357 			.chan_instid = 2,
358 			.chan_logid = 2,
359 			.chan_nrules = 1,
360 			.chan_type = UMC_DIMM_T_DDR4,
361 			.chan_rules = { {
362 				.ddr_flags = DF_DRAM_F_VALID,
363 				.ddr_base = 0,
364 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
365 				    1024ULL,
366 				.ddr_dest_fabid = 0,
367 				.ddr_sock_ileave_bits = 1,
368 				.ddr_die_ileave_bits = 0,
369 				.ddr_addr_start = 10,
370 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
371 			} },
372 			.chan_dimms = { {
373 				.ud_flags = UMC_DIMM_F_VALID,
374 				.ud_width = UMC_DIMM_W_X4,
375 				.ud_kind = UMC_DIMM_K_RDIMM,
376 				.ud_dimmno = 0,
377 				.ud_cs = { {
378 					.ucs_base = {
379 						.udb_base = 0,
380 						.udb_valid = B_TRUE
381 					},
382 					.ucs_base_mask = 0x3ffffffff,
383 					.ucs_nbanks = 0x4,
384 					.ucs_ncol = 0xa,
385 					.ucs_nrow_lo = 0x11,
386 					.ucs_nbank_groups = 0x2,
387 					.ucs_row_hi_bit = 0x18,
388 					.ucs_row_low_bit = 0x11,
389 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
390 					    0xe },
391 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
392 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
393 				} }
394 			} },
395 		}, {
396 			.chan_flags = UMC_CHAN_F_ECC_EN,
397 			.chan_fabid = 3,
398 			.chan_instid = 3,
399 			.chan_logid = 3,
400 			.chan_nrules = 1,
401 			.chan_type = UMC_DIMM_T_DDR4,
402 			.chan_rules = { {
403 				.ddr_flags = DF_DRAM_F_VALID,
404 				.ddr_base = 0,
405 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
406 				    1024ULL,
407 				.ddr_dest_fabid = 0,
408 				.ddr_sock_ileave_bits = 1,
409 				.ddr_die_ileave_bits = 0,
410 				.ddr_addr_start = 10,
411 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
412 			} },
413 			.chan_dimms = { {
414 				.ud_flags = UMC_DIMM_F_VALID,
415 				.ud_width = UMC_DIMM_W_X4,
416 				.ud_kind = UMC_DIMM_K_RDIMM,
417 				.ud_dimmno = 0,
418 				.ud_cs = { {
419 					.ucs_base = {
420 						.udb_base = 0,
421 						.udb_valid = B_TRUE
422 					},
423 					.ucs_base_mask = 0x3ffffffff,
424 					.ucs_nbanks = 0x4,
425 					.ucs_ncol = 0xa,
426 					.ucs_nrow_lo = 0x11,
427 					.ucs_nbank_groups = 0x2,
428 					.ucs_row_hi_bit = 0x18,
429 					.ucs_row_low_bit = 0x11,
430 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
431 					    0xe },
432 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
433 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
434 				} }
435 			} },
436 		}  }
437 	}, {
438 		.zud_dfno = 1,
439 		.zud_dram_nrules = 2,
440 		.zud_nchan = 4,
441 		.zud_cs_nremap = 0,
442 		.zud_hole_base = 0,
443 		.zud_rules = { {
444 			.ddr_flags = DF_DRAM_F_VALID,
445 			.ddr_base = 0,
446 			.ddr_limit = 128ULL * 1024ULL * 1024ULL * 1024ULL,
447 			.ddr_dest_fabid = 0,
448 			.ddr_sock_ileave_bits = 1,
449 			.ddr_die_ileave_bits = 0,
450 			.ddr_addr_start = 10,
451 			.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
452 		} },
453 		.zud_chan = { {
454 			.chan_flags = UMC_CHAN_F_ECC_EN,
455 			.chan_fabid = 0x20,
456 			.chan_instid = 0,
457 			.chan_logid = 0,
458 			.chan_nrules = 1,
459 			.chan_type = UMC_DIMM_T_DDR4,
460 			.chan_rules = { {
461 				.ddr_flags = DF_DRAM_F_VALID,
462 				.ddr_base = 0,
463 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
464 				    1024ULL,
465 				.ddr_dest_fabid = 0,
466 				.ddr_sock_ileave_bits = 1,
467 				.ddr_die_ileave_bits = 0,
468 				.ddr_addr_start = 10,
469 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
470 			} },
471 			.chan_dimms = { {
472 				.ud_flags = UMC_DIMM_F_VALID,
473 				.ud_width = UMC_DIMM_W_X4,
474 				.ud_kind = UMC_DIMM_K_RDIMM,
475 				.ud_dimmno = 0,
476 				.ud_cs = { {
477 					.ucs_base = {
478 						.udb_base = 0,
479 						.udb_valid = B_TRUE
480 					},
481 					.ucs_base_mask = 0x3ffffffff,
482 					.ucs_nbanks = 0x4,
483 					.ucs_ncol = 0xa,
484 					.ucs_nrow_lo = 0x11,
485 					.ucs_nbank_groups = 0x2,
486 					.ucs_row_hi_bit = 0x18,
487 					.ucs_row_low_bit = 0x11,
488 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
489 					    0xe },
490 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
491 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
492 				} }
493 			} },
494 		}, {
495 			.chan_flags = UMC_CHAN_F_ECC_EN,
496 			.chan_fabid = 0x21,
497 			.chan_instid = 1,
498 			.chan_logid = 1,
499 			.chan_nrules = 1,
500 			.chan_type = UMC_DIMM_T_DDR4,
501 			.chan_rules = { {
502 				.ddr_flags = DF_DRAM_F_VALID,
503 				.ddr_base = 0,
504 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
505 				    1024ULL,
506 				.ddr_dest_fabid = 0,
507 				.ddr_sock_ileave_bits = 1,
508 				.ddr_die_ileave_bits = 0,
509 				.ddr_addr_start = 10,
510 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
511 			} },
512 			.chan_dimms = { {
513 				.ud_flags = UMC_DIMM_F_VALID,
514 				.ud_width = UMC_DIMM_W_X4,
515 				.ud_kind = UMC_DIMM_K_RDIMM,
516 				.ud_dimmno = 0,
517 				.ud_cs = { {
518 					.ucs_base = {
519 						.udb_base = 0,
520 						.udb_valid = B_TRUE
521 					},
522 					.ucs_base_mask = 0x3ffffffff,
523 					.ucs_nbanks = 0x4,
524 					.ucs_ncol = 0xa,
525 					.ucs_nrow_lo = 0x11,
526 					.ucs_nbank_groups = 0x2,
527 					.ucs_row_hi_bit = 0x18,
528 					.ucs_row_low_bit = 0x11,
529 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
530 					    0xe },
531 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
532 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
533 				} }
534 			} },
535 		}, {
536 			.chan_flags = UMC_CHAN_F_ECC_EN,
537 			.chan_fabid = 0x22,
538 			.chan_instid = 2,
539 			.chan_logid = 2,
540 			.chan_nrules = 1,
541 			.chan_type = UMC_DIMM_T_DDR4,
542 			.chan_rules = { {
543 				.ddr_flags = DF_DRAM_F_VALID,
544 				.ddr_base = 0,
545 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
546 				    1024ULL,
547 				.ddr_dest_fabid = 0,
548 				.ddr_sock_ileave_bits = 1,
549 				.ddr_die_ileave_bits = 0,
550 				.ddr_addr_start = 10,
551 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
552 			} },
553 			.chan_dimms = { {
554 				.ud_flags = UMC_DIMM_F_VALID,
555 				.ud_width = UMC_DIMM_W_X4,
556 				.ud_kind = UMC_DIMM_K_RDIMM,
557 				.ud_dimmno = 0,
558 				.ud_cs = { {
559 					.ucs_base = {
560 						.udb_base = 0,
561 						.udb_valid = B_TRUE
562 					},
563 					.ucs_base_mask = 0x3ffffffff,
564 					.ucs_nbanks = 0x4,
565 					.ucs_ncol = 0xa,
566 					.ucs_nrow_lo = 0x11,
567 					.ucs_nbank_groups = 0x2,
568 					.ucs_row_hi_bit = 0x18,
569 					.ucs_row_low_bit = 0x11,
570 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
571 					    0xe },
572 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
573 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
574 				} }
575 			} },
576 		}, {
577 			.chan_flags = UMC_CHAN_F_ECC_EN,
578 			.chan_fabid = 0x23,
579 			.chan_instid = 3,
580 			.chan_logid = 3,
581 			.chan_nrules = 1,
582 			.chan_type = UMC_DIMM_T_DDR4,
583 			.chan_rules = { {
584 				.ddr_flags = DF_DRAM_F_VALID,
585 				.ddr_base = 0,
586 				.ddr_limit = 128ULL * 1024ULL * 1024ULL *
587 				    1024ULL,
588 				.ddr_dest_fabid = 0,
589 				.ddr_sock_ileave_bits = 1,
590 				.ddr_die_ileave_bits = 0,
591 				.ddr_addr_start = 10,
592 				.ddr_chan_ileave = DF_CHAN_ILEAVE_4CH
593 			} },
594 			.chan_dimms = { {
595 				.ud_flags = UMC_DIMM_F_VALID,
596 				.ud_width = UMC_DIMM_W_X4,
597 				.ud_kind = UMC_DIMM_K_RDIMM,
598 				.ud_dimmno = 0,
599 				.ud_cs = { {
600 					.ucs_base = {
601 						.udb_base = 0,
602 						.udb_valid = B_TRUE
603 					},
604 					.ucs_base_mask = 0x3ffffffff,
605 					.ucs_nbanks = 0x4,
606 					.ucs_ncol = 0xa,
607 					.ucs_nrow_lo = 0x11,
608 					.ucs_nbank_groups = 0x2,
609 					.ucs_row_hi_bit = 0x18,
610 					.ucs_row_low_bit = 0x11,
611 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
612 					    0xe },
613 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
614 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
615 				} }
616 			} },
617 		}  }
618 	} }
619 };
620 
621 /*
622  * This is a 2 Die, 2 Channel interleave.
623  */
624 static const zen_umc_t zen_umc_ilv_1p2d2c_2d2ch = {
625 	.umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL,
626 	.umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL,
627 	.umc_df_rev = DF_REV_3,
628 	.umc_decomp = {
629 		.dfd_sock_mask = 0x00,
630 		.dfd_die_mask = 0x01,
631 		.dfd_node_mask = 0x20,
632 		.dfd_comp_mask = 0x1f,
633 		.dfd_sock_shift = 0,
634 		.dfd_die_shift = 0,
635 		.dfd_node_shift = 5,
636 		.dfd_comp_shift = 0
637 	},
638 	.umc_ndfs = 2,
639 	.umc_dfs = { {
640 		.zud_dfno = 0,
641 		.zud_dram_nrules = 1,
642 		.zud_nchan = 2,
643 		.zud_cs_nremap = 0,
644 		.zud_hole_base = 0,
645 		.zud_rules = { {
646 			.ddr_flags = DF_DRAM_F_VALID,
647 			.ddr_base = 0,
648 			.ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL,
649 			.ddr_dest_fabid = 0,
650 			.ddr_sock_ileave_bits = 0,
651 			.ddr_die_ileave_bits = 1,
652 			.ddr_addr_start = 12,
653 			.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
654 		} },
655 		.zud_chan = { {
656 			.chan_flags = UMC_CHAN_F_ECC_EN,
657 			.chan_fabid = 0,
658 			.chan_instid = 0,
659 			.chan_logid = 0,
660 			.chan_nrules = 1,
661 			.chan_type = UMC_DIMM_T_DDR4,
662 			.chan_rules = { {
663 				.ddr_flags = DF_DRAM_F_VALID,
664 				.ddr_base = 0,
665 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
666 				    1024ULL,
667 				.ddr_dest_fabid = 0,
668 				.ddr_sock_ileave_bits = 0,
669 				.ddr_die_ileave_bits = 1,
670 				.ddr_addr_start = 12,
671 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
672 			} },
673 			.chan_dimms = { {
674 				.ud_flags = UMC_DIMM_F_VALID,
675 				.ud_width = UMC_DIMM_W_X4,
676 				.ud_kind = UMC_DIMM_K_RDIMM,
677 				.ud_dimmno = 0,
678 				.ud_cs = { {
679 					.ucs_base = {
680 						.udb_base = 0,
681 						.udb_valid = B_TRUE
682 					},
683 					.ucs_base_mask = 0x3ffffffff,
684 					.ucs_nbanks = 0x4,
685 					.ucs_ncol = 0xa,
686 					.ucs_nrow_lo = 0x11,
687 					.ucs_nbank_groups = 0x2,
688 					.ucs_row_hi_bit = 0x18,
689 					.ucs_row_low_bit = 0x11,
690 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
691 					    0xe },
692 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
693 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
694 				} }
695 			} },
696 		}, {
697 			.chan_flags = UMC_CHAN_F_ECC_EN,
698 			.chan_fabid = 1,
699 			.chan_instid = 1,
700 			.chan_logid = 1,
701 			.chan_nrules = 1,
702 			.chan_type = UMC_DIMM_T_DDR4,
703 			.chan_rules = { {
704 				.ddr_flags = DF_DRAM_F_VALID,
705 				.ddr_base = 0,
706 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
707 				    1024ULL,
708 				.ddr_dest_fabid = 0,
709 				.ddr_sock_ileave_bits = 0,
710 				.ddr_die_ileave_bits = 1,
711 				.ddr_addr_start = 12,
712 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
713 			} },
714 			.chan_dimms = { {
715 				.ud_flags = UMC_DIMM_F_VALID,
716 				.ud_width = UMC_DIMM_W_X4,
717 				.ud_kind = UMC_DIMM_K_RDIMM,
718 				.ud_dimmno = 0,
719 				.ud_cs = { {
720 					.ucs_base = {
721 						.udb_base = 0,
722 						.udb_valid = B_TRUE
723 					},
724 					.ucs_base_mask = 0x3ffffffff,
725 					.ucs_nbanks = 0x4,
726 					.ucs_ncol = 0xa,
727 					.ucs_nrow_lo = 0x11,
728 					.ucs_nbank_groups = 0x2,
729 					.ucs_row_hi_bit = 0x18,
730 					.ucs_row_low_bit = 0x11,
731 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
732 					    0xe },
733 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
734 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
735 				} }
736 			} },
737 		} }
738 	}, {
739 		.zud_dfno = 1,
740 		.zud_dram_nrules = 2,
741 		.zud_nchan = 4,
742 		.zud_cs_nremap = 0,
743 		.zud_hole_base = 0,
744 		.zud_rules = { {
745 			.ddr_flags = DF_DRAM_F_VALID,
746 			.ddr_base = 0,
747 			.ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL,
748 			.ddr_dest_fabid = 0,
749 			.ddr_sock_ileave_bits = 0,
750 			.ddr_die_ileave_bits = 1,
751 			.ddr_addr_start = 12,
752 			.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
753 		} },
754 		.zud_chan = { {
755 			.chan_flags = UMC_CHAN_F_ECC_EN,
756 			.chan_fabid = 0x20,
757 			.chan_instid = 0,
758 			.chan_logid = 0,
759 			.chan_nrules = 1,
760 			.chan_type = UMC_DIMM_T_DDR4,
761 			.chan_rules = { {
762 				.ddr_flags = DF_DRAM_F_VALID,
763 				.ddr_base = 0,
764 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
765 				    1024ULL,
766 				.ddr_dest_fabid = 0,
767 				.ddr_sock_ileave_bits = 0,
768 				.ddr_die_ileave_bits = 1,
769 				.ddr_addr_start = 12,
770 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
771 			} },
772 			.chan_dimms = { {
773 				.ud_flags = UMC_DIMM_F_VALID,
774 				.ud_width = UMC_DIMM_W_X4,
775 				.ud_kind = UMC_DIMM_K_RDIMM,
776 				.ud_dimmno = 0,
777 				.ud_cs = { {
778 					.ucs_base = {
779 						.udb_base = 0,
780 						.udb_valid = B_TRUE
781 					},
782 					.ucs_base_mask = 0x3ffffffff,
783 					.ucs_nbanks = 0x4,
784 					.ucs_ncol = 0xa,
785 					.ucs_nrow_lo = 0x11,
786 					.ucs_nbank_groups = 0x2,
787 					.ucs_row_hi_bit = 0x18,
788 					.ucs_row_low_bit = 0x11,
789 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
790 					    0xe },
791 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
792 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
793 				} }
794 			} },
795 		}, {
796 			.chan_flags = UMC_CHAN_F_ECC_EN,
797 			.chan_fabid = 0x21,
798 			.chan_instid = 1,
799 			.chan_logid = 1,
800 			.chan_nrules = 1,
801 			.chan_type = UMC_DIMM_T_DDR4,
802 			.chan_rules = { {
803 				.ddr_flags = DF_DRAM_F_VALID,
804 				.ddr_base = 0,
805 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
806 				    1024ULL,
807 				.ddr_dest_fabid = 0,
808 				.ddr_sock_ileave_bits = 0,
809 				.ddr_die_ileave_bits = 1,
810 				.ddr_addr_start = 12,
811 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
812 			} },
813 			.chan_dimms = { {
814 				.ud_flags = UMC_DIMM_F_VALID,
815 				.ud_width = UMC_DIMM_W_X4,
816 				.ud_kind = UMC_DIMM_K_RDIMM,
817 				.ud_dimmno = 0,
818 				.ud_cs = { {
819 					.ucs_base = {
820 						.udb_base = 0,
821 						.udb_valid = B_TRUE
822 					},
823 					.ucs_base_mask = 0x3ffffffff,
824 					.ucs_nbanks = 0x4,
825 					.ucs_ncol = 0xa,
826 					.ucs_nrow_lo = 0x11,
827 					.ucs_nbank_groups = 0x2,
828 					.ucs_row_hi_bit = 0x18,
829 					.ucs_row_low_bit = 0x11,
830 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
831 					    0xe },
832 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
833 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
834 				} }
835 			} },
836 		} }
837 	} }
838 };
839 
840 /*
841  * This is a 2 Socket 2 Die, 2 Channel interleave, aka naples-light, but with a
842  * contiguous DFv4 style socket ID.
843  */
844 static const zen_umc_t zen_umc_ilv_naplesish = {
845 	.umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL,
846 	.umc_tom2 = 256ULL * 1024ULL * 1024ULL * 1024ULL,
847 	.umc_df_rev = DF_REV_3,
848 	.umc_decomp = {
849 		.dfd_sock_mask = 0x1e,
850 		.dfd_die_mask = 0x01,
851 		.dfd_node_mask = 0xf80,
852 		.dfd_comp_mask = 0x7f,
853 		.dfd_sock_shift = 1,
854 		.dfd_die_shift = 0,
855 		.dfd_node_shift = 7,
856 		.dfd_comp_shift = 0
857 	},
858 	.umc_ndfs = 4,
859 	.umc_dfs = { {
860 		.zud_dfno = 0,
861 		.zud_dram_nrules = 1,
862 		.zud_nchan = 2,
863 		.zud_cs_nremap = 0,
864 		.zud_hole_base = 0,
865 		.zud_rules = { {
866 			.ddr_flags = DF_DRAM_F_VALID,
867 			.ddr_base = 0,
868 			.ddr_limit = 256ULL * 1024ULL * 1024ULL * 1024ULL,
869 			.ddr_dest_fabid = 0,
870 			.ddr_sock_ileave_bits = 1,
871 			.ddr_die_ileave_bits = 1,
872 			.ddr_addr_start = 8,
873 			.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
874 		} },
875 		.zud_chan = { {
876 			.chan_flags = UMC_CHAN_F_ECC_EN,
877 			.chan_fabid = 0,
878 			.chan_instid = 0,
879 			.chan_logid = 0,
880 			.chan_nrules = 1,
881 			.chan_type = UMC_DIMM_T_DDR4,
882 			.chan_rules = { {
883 				.ddr_flags = DF_DRAM_F_VALID,
884 				.ddr_base = 0,
885 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
886 				    1024ULL,
887 				.ddr_dest_fabid = 0,
888 				.ddr_sock_ileave_bits = 1,
889 				.ddr_die_ileave_bits = 1,
890 				.ddr_addr_start = 8,
891 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
892 			} },
893 			.chan_dimms = { {
894 				.ud_flags = UMC_DIMM_F_VALID,
895 				.ud_width = UMC_DIMM_W_X4,
896 				.ud_kind = UMC_DIMM_K_RDIMM,
897 				.ud_dimmno = 0,
898 				.ud_cs = { {
899 					.ucs_base = {
900 						.udb_base = 0,
901 						.udb_valid = B_TRUE
902 					},
903 					.ucs_base_mask = 0x3ffffffff,
904 					.ucs_nbanks = 0x4,
905 					.ucs_ncol = 0xa,
906 					.ucs_nrow_lo = 0x11,
907 					.ucs_nbank_groups = 0x2,
908 					.ucs_row_hi_bit = 0x18,
909 					.ucs_row_low_bit = 0x11,
910 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
911 					    0xe },
912 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
913 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
914 				} }
915 			} },
916 		}, {
917 			.chan_flags = UMC_CHAN_F_ECC_EN,
918 			.chan_fabid = 1,
919 			.chan_instid = 1,
920 			.chan_logid = 1,
921 			.chan_nrules = 1,
922 			.chan_type = UMC_DIMM_T_DDR4,
923 			.chan_rules = { {
924 				.ddr_flags = DF_DRAM_F_VALID,
925 				.ddr_base = 0,
926 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
927 				    1024ULL,
928 				.ddr_dest_fabid = 0,
929 				.ddr_sock_ileave_bits = 1,
930 				.ddr_die_ileave_bits = 1,
931 				.ddr_addr_start = 8,
932 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
933 			} },
934 			.chan_dimms = { {
935 				.ud_flags = UMC_DIMM_F_VALID,
936 				.ud_width = UMC_DIMM_W_X4,
937 				.ud_kind = UMC_DIMM_K_RDIMM,
938 				.ud_dimmno = 0,
939 				.ud_cs = { {
940 					.ucs_base = {
941 						.udb_base = 0,
942 						.udb_valid = B_TRUE
943 					},
944 					.ucs_base_mask = 0x3ffffffff,
945 					.ucs_nbanks = 0x4,
946 					.ucs_ncol = 0xa,
947 					.ucs_nrow_lo = 0x11,
948 					.ucs_nbank_groups = 0x2,
949 					.ucs_row_hi_bit = 0x18,
950 					.ucs_row_low_bit = 0x11,
951 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
952 					    0xe },
953 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
954 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
955 				} }
956 			} },
957 		} }
958 	}, {
959 		.zud_dfno = 0,
960 		.zud_dram_nrules = 1,
961 		.zud_nchan = 2,
962 		.zud_cs_nremap = 0,
963 		.zud_hole_base = 0,
964 		.zud_rules = { {
965 			.ddr_flags = DF_DRAM_F_VALID,
966 			.ddr_base = 0,
967 			.ddr_limit = 256ULL * 1024ULL * 1024ULL * 1024ULL,
968 			.ddr_dest_fabid = 0,
969 			.ddr_sock_ileave_bits = 1,
970 			.ddr_die_ileave_bits = 1,
971 			.ddr_addr_start = 8,
972 			.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
973 		} },
974 		.zud_chan = { {
975 			.chan_flags = UMC_CHAN_F_ECC_EN,
976 			.chan_fabid = 0x80,
977 			.chan_instid = 0,
978 			.chan_logid = 0,
979 			.chan_nrules = 1,
980 			.chan_type = UMC_DIMM_T_DDR4,
981 			.chan_rules = { {
982 				.ddr_flags = DF_DRAM_F_VALID,
983 				.ddr_base = 0,
984 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
985 				    1024ULL,
986 				.ddr_dest_fabid = 0,
987 				.ddr_sock_ileave_bits = 1,
988 				.ddr_die_ileave_bits = 1,
989 				.ddr_addr_start = 8,
990 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
991 			} },
992 			.chan_dimms = { {
993 				.ud_flags = UMC_DIMM_F_VALID,
994 				.ud_width = UMC_DIMM_W_X4,
995 				.ud_kind = UMC_DIMM_K_RDIMM,
996 				.ud_dimmno = 0,
997 				.ud_cs = { {
998 					.ucs_base = {
999 						.udb_base = 0,
1000 						.udb_valid = B_TRUE
1001 					},
1002 					.ucs_base_mask = 0x3ffffffff,
1003 					.ucs_nbanks = 0x4,
1004 					.ucs_ncol = 0xa,
1005 					.ucs_nrow_lo = 0x11,
1006 					.ucs_nbank_groups = 0x2,
1007 					.ucs_row_hi_bit = 0x18,
1008 					.ucs_row_low_bit = 0x11,
1009 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
1010 					    0xe },
1011 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
1012 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
1013 				} }
1014 			} },
1015 		}, {
1016 			.chan_flags = UMC_CHAN_F_ECC_EN,
1017 			.chan_fabid = 0x81,
1018 			.chan_instid = 1,
1019 			.chan_logid = 1,
1020 			.chan_nrules = 1,
1021 			.chan_type = UMC_DIMM_T_DDR4,
1022 			.chan_rules = { {
1023 				.ddr_flags = DF_DRAM_F_VALID,
1024 				.ddr_base = 0,
1025 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
1026 				    1024ULL,
1027 				.ddr_dest_fabid = 0,
1028 				.ddr_sock_ileave_bits = 1,
1029 				.ddr_die_ileave_bits = 1,
1030 				.ddr_addr_start = 8,
1031 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1032 			} },
1033 			.chan_dimms = { {
1034 				.ud_flags = UMC_DIMM_F_VALID,
1035 				.ud_width = UMC_DIMM_W_X4,
1036 				.ud_kind = UMC_DIMM_K_RDIMM,
1037 				.ud_dimmno = 0,
1038 				.ud_cs = { {
1039 					.ucs_base = {
1040 						.udb_base = 0,
1041 						.udb_valid = B_TRUE
1042 					},
1043 					.ucs_base_mask = 0x3ffffffff,
1044 					.ucs_nbanks = 0x4,
1045 					.ucs_ncol = 0xa,
1046 					.ucs_nrow_lo = 0x11,
1047 					.ucs_nbank_groups = 0x2,
1048 					.ucs_row_hi_bit = 0x18,
1049 					.ucs_row_low_bit = 0x11,
1050 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
1051 					    0xe },
1052 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
1053 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
1054 				} }
1055 			} },
1056 		} }
1057 	}, {
1058 		.zud_dfno = 0,
1059 		.zud_dram_nrules = 1,
1060 		.zud_nchan = 2,
1061 		.zud_cs_nremap = 0,
1062 		.zud_hole_base = 0,
1063 		.zud_rules = { {
1064 			.ddr_flags = DF_DRAM_F_VALID,
1065 			.ddr_base = 0,
1066 			.ddr_limit = 256ULL * 1024ULL * 1024ULL * 1024ULL,
1067 			.ddr_dest_fabid = 0,
1068 			.ddr_sock_ileave_bits = 1,
1069 			.ddr_die_ileave_bits = 1,
1070 			.ddr_addr_start = 8,
1071 			.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1072 		} },
1073 		.zud_chan = { {
1074 			.chan_flags = UMC_CHAN_F_ECC_EN,
1075 			.chan_fabid = 0x100,
1076 			.chan_instid = 0,
1077 			.chan_logid = 0,
1078 			.chan_nrules = 1,
1079 			.chan_type = UMC_DIMM_T_DDR4,
1080 			.chan_rules = { {
1081 				.ddr_flags = DF_DRAM_F_VALID,
1082 				.ddr_base = 0,
1083 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
1084 				    1024ULL,
1085 				.ddr_dest_fabid = 0,
1086 				.ddr_sock_ileave_bits = 1,
1087 				.ddr_die_ileave_bits = 1,
1088 				.ddr_addr_start = 8,
1089 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1090 			} },
1091 			.chan_dimms = { {
1092 				.ud_flags = UMC_DIMM_F_VALID,
1093 				.ud_width = UMC_DIMM_W_X4,
1094 				.ud_kind = UMC_DIMM_K_RDIMM,
1095 				.ud_dimmno = 0,
1096 				.ud_cs = { {
1097 					.ucs_base = {
1098 						.udb_base = 0,
1099 						.udb_valid = B_TRUE
1100 					},
1101 					.ucs_base_mask = 0x3ffffffff,
1102 					.ucs_nbanks = 0x4,
1103 					.ucs_ncol = 0xa,
1104 					.ucs_nrow_lo = 0x11,
1105 					.ucs_nbank_groups = 0x2,
1106 					.ucs_row_hi_bit = 0x18,
1107 					.ucs_row_low_bit = 0x11,
1108 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
1109 					    0xe },
1110 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
1111 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
1112 				} }
1113 			} },
1114 		}, {
1115 			.chan_flags = UMC_CHAN_F_ECC_EN,
1116 			.chan_fabid = 0x101,
1117 			.chan_instid = 1,
1118 			.chan_logid = 1,
1119 			.chan_nrules = 1,
1120 			.chan_type = UMC_DIMM_T_DDR4,
1121 			.chan_rules = { {
1122 				.ddr_flags = DF_DRAM_F_VALID,
1123 				.ddr_base = 0,
1124 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
1125 				    1024ULL,
1126 				.ddr_dest_fabid = 0,
1127 				.ddr_sock_ileave_bits = 1,
1128 				.ddr_die_ileave_bits = 1,
1129 				.ddr_addr_start = 8,
1130 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1131 			} },
1132 			.chan_dimms = { {
1133 				.ud_flags = UMC_DIMM_F_VALID,
1134 				.ud_width = UMC_DIMM_W_X4,
1135 				.ud_kind = UMC_DIMM_K_RDIMM,
1136 				.ud_dimmno = 0,
1137 				.ud_cs = { {
1138 					.ucs_base = {
1139 						.udb_base = 0,
1140 						.udb_valid = B_TRUE
1141 					},
1142 					.ucs_base_mask = 0x3ffffffff,
1143 					.ucs_nbanks = 0x4,
1144 					.ucs_ncol = 0xa,
1145 					.ucs_nrow_lo = 0x11,
1146 					.ucs_nbank_groups = 0x2,
1147 					.ucs_row_hi_bit = 0x18,
1148 					.ucs_row_low_bit = 0x11,
1149 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
1150 					    0xe },
1151 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
1152 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
1153 				} }
1154 			} },
1155 		} }
1156 	}, {
1157 		.zud_dfno = 1,
1158 		.zud_dram_nrules = 2,
1159 		.zud_nchan = 4,
1160 		.zud_cs_nremap = 0,
1161 		.zud_hole_base = 0,
1162 		.zud_rules = { {
1163 			.ddr_flags = DF_DRAM_F_VALID,
1164 			.ddr_base = 0,
1165 			.ddr_limit = 256ULL * 1024ULL * 1024ULL * 1024ULL,
1166 			.ddr_dest_fabid = 0,
1167 			.ddr_sock_ileave_bits = 1,
1168 			.ddr_die_ileave_bits = 1,
1169 			.ddr_addr_start = 8,
1170 			.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1171 		} },
1172 		.zud_chan = { {
1173 			.chan_flags = UMC_CHAN_F_ECC_EN,
1174 			.chan_fabid = 0x180,
1175 			.chan_instid = 0,
1176 			.chan_logid = 0,
1177 			.chan_nrules = 1,
1178 			.chan_type = UMC_DIMM_T_DDR4,
1179 			.chan_rules = { {
1180 				.ddr_flags = DF_DRAM_F_VALID,
1181 				.ddr_base = 0,
1182 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
1183 				    1024ULL,
1184 				.ddr_dest_fabid = 0,
1185 				.ddr_sock_ileave_bits = 1,
1186 				.ddr_die_ileave_bits = 1,
1187 				.ddr_addr_start = 8,
1188 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1189 			} },
1190 			.chan_dimms = { {
1191 				.ud_flags = UMC_DIMM_F_VALID,
1192 				.ud_width = UMC_DIMM_W_X4,
1193 				.ud_kind = UMC_DIMM_K_RDIMM,
1194 				.ud_dimmno = 0,
1195 				.ud_cs = { {
1196 					.ucs_base = {
1197 						.udb_base = 0,
1198 						.udb_valid = B_TRUE
1199 					},
1200 					.ucs_base_mask = 0x3ffffffff,
1201 					.ucs_nbanks = 0x4,
1202 					.ucs_ncol = 0xa,
1203 					.ucs_nrow_lo = 0x11,
1204 					.ucs_nbank_groups = 0x2,
1205 					.ucs_row_hi_bit = 0x18,
1206 					.ucs_row_low_bit = 0x11,
1207 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
1208 					    0xe },
1209 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
1210 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
1211 				} }
1212 			} },
1213 		}, {
1214 			.chan_flags = UMC_CHAN_F_ECC_EN,
1215 			.chan_fabid = 0x181,
1216 			.chan_instid = 1,
1217 			.chan_logid = 1,
1218 			.chan_nrules = 1,
1219 			.chan_type = UMC_DIMM_T_DDR4,
1220 			.chan_rules = { {
1221 				.ddr_flags = DF_DRAM_F_VALID,
1222 				.ddr_base = 0,
1223 				.ddr_limit = 256ULL * 1024ULL * 1024ULL *
1224 				    1024ULL,
1225 				.ddr_dest_fabid = 0,
1226 				.ddr_sock_ileave_bits = 1,
1227 				.ddr_die_ileave_bits = 1,
1228 				.ddr_addr_start = 8,
1229 				.ddr_chan_ileave = DF_CHAN_ILEAVE_2CH
1230 			} },
1231 			.chan_dimms = { {
1232 				.ud_flags = UMC_DIMM_F_VALID,
1233 				.ud_width = UMC_DIMM_W_X4,
1234 				.ud_kind = UMC_DIMM_K_RDIMM,
1235 				.ud_dimmno = 0,
1236 				.ud_cs = { {
1237 					.ucs_base = {
1238 						.udb_base = 0,
1239 						.udb_valid = B_TRUE
1240 					},
1241 					.ucs_base_mask = 0x3ffffffff,
1242 					.ucs_nbanks = 0x4,
1243 					.ucs_ncol = 0xa,
1244 					.ucs_nrow_lo = 0x11,
1245 					.ucs_nbank_groups = 0x2,
1246 					.ucs_row_hi_bit = 0x18,
1247 					.ucs_row_low_bit = 0x11,
1248 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
1249 					    0xe },
1250 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
1251 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
1252 				} }
1253 			} },
1254 		} }
1255 	} }
1256 };
1257 
1258 const umc_decode_test_t zen_umc_test_ilv[] = { {
1259 	.udt_desc = "ILV: 1/1/4 4-way Channel (0)",
1260 	.udt_umc = &zen_umc_ilv_1p1d4c_4ch,
1261 	.udt_pa = 0x1ff,
1262 	.udt_pass = B_TRUE,
1263 	.udt_norm_addr = 0x1ff,
1264 	.udt_sock = 0,
1265 	.udt_die = 0,
1266 	.udt_comp = 0,
1267 	.udt_dimm_no = 0,
1268 	.udt_dimm_col = 0x3f,
1269 	.udt_dimm_row = 0,
1270 	.udt_dimm_bank = 0,
1271 	.udt_dimm_bank_group = 0,
1272 	.udt_dimm_subchan = UINT8_MAX,
1273 	.udt_dimm_rm = 0,
1274 	.udt_dimm_cs = 0
1275 }, {
1276 	.udt_desc = "ILV: 1/1/4 4-way Channel (1)",
1277 	.udt_umc = &zen_umc_ilv_1p1d4c_4ch,
1278 	.udt_pa = 0x3ff,
1279 	.udt_pass = B_TRUE,
1280 	.udt_norm_addr = 0x1ff,
1281 	.udt_sock = 0,
1282 	.udt_die = 0,
1283 	.udt_comp = 1,
1284 	.udt_dimm_no = 0,
1285 	.udt_dimm_col = 0x3f,
1286 	.udt_dimm_row = 0,
1287 	.udt_dimm_bank = 0,
1288 	.udt_dimm_bank_group = 0,
1289 	.udt_dimm_subchan = UINT8_MAX,
1290 	.udt_dimm_rm = 0,
1291 	.udt_dimm_cs = 0
1292 }, {
1293 	.udt_desc = "ILV: 1/1/4 4-way Channel (2)",
1294 	.udt_umc = &zen_umc_ilv_1p1d4c_4ch,
1295 	.udt_pa = 0x5ff,
1296 	.udt_pass = B_TRUE,
1297 	.udt_norm_addr = 0x1ff,
1298 	.udt_sock = 0,
1299 	.udt_die = 0,
1300 	.udt_comp = 2,
1301 	.udt_dimm_no = 0,
1302 	.udt_dimm_col = 0x3f,
1303 	.udt_dimm_row = 0,
1304 	.udt_dimm_bank = 0,
1305 	.udt_dimm_bank_group = 0,
1306 	.udt_dimm_subchan = UINT8_MAX,
1307 	.udt_dimm_rm = 0,
1308 	.udt_dimm_cs = 0
1309 }, {
1310 	.udt_desc = "ILV: 1/1/4 4-way Channel (3)",
1311 	.udt_umc = &zen_umc_ilv_1p1d4c_4ch,
1312 	.udt_pa = 0x7ff,
1313 	.udt_pass = B_TRUE,
1314 	.udt_norm_addr = 0x1ff,
1315 	.udt_sock = 0,
1316 	.udt_die = 0,
1317 	.udt_comp = 3,
1318 	.udt_dimm_no = 0,
1319 	.udt_dimm_col = 0x3f,
1320 	.udt_dimm_row = 0,
1321 	.udt_dimm_bank = 0,
1322 	.udt_dimm_bank_group = 0,
1323 	.udt_dimm_subchan = UINT8_MAX,
1324 	.udt_dimm_rm = 0,
1325 	.udt_dimm_cs = 0
1326 }, {
1327 	.udt_desc = "ILV: 1/1/4 4-way Channel (4)",
1328 	.udt_umc = &zen_umc_ilv_1p1d4c_4ch,
1329 	.udt_pa = 0x42231679,
1330 	.udt_pass = B_TRUE,
1331 	.udt_norm_addr = 0x1088c479,
1332 	.udt_sock = 0,
1333 	.udt_die = 0,
1334 	.udt_comp = 3,
1335 	.udt_dimm_no = 0,
1336 	.udt_dimm_col = 0x8f,
1337 	.udt_dimm_row = 0x844,
1338 	.udt_dimm_bank = 2,
1339 	.udt_dimm_bank_group = 1,
1340 	.udt_dimm_subchan = UINT8_MAX,
1341 	.udt_dimm_rm = 0,
1342 	.udt_dimm_cs = 0
1343 }, {
1344 	.udt_desc = "ILV: 2/1/4 2P-way, 4-way Channel (0)",
1345 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1346 	.udt_pa = 0x21ff,
1347 	.udt_pass = B_TRUE,
1348 	.udt_norm_addr = 0x5ff,
1349 	.udt_sock = 0,
1350 	.udt_die = 0,
1351 	.udt_comp = 0,
1352 	.udt_dimm_no = 0,
1353 	.udt_dimm_col = 0xbf,
1354 	.udt_dimm_row = 0,
1355 	.udt_dimm_bank = 0,
1356 	.udt_dimm_bank_group = 0,
1357 	.udt_dimm_subchan = UINT8_MAX,
1358 	.udt_dimm_rm = 0,
1359 	.udt_dimm_cs = 0
1360 }, {
1361 	.udt_desc = "ILV: 2/1/4 2P-way, 4-way Channel (1)",
1362 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1363 	.udt_pa = 0x23ff,
1364 	.udt_pass = B_TRUE,
1365 	.udt_norm_addr = 0x7ff,
1366 	.udt_sock = 0,
1367 	.udt_die = 0,
1368 	.udt_comp = 0,
1369 	.udt_dimm_no = 0,
1370 	.udt_dimm_col = 0xff,
1371 	.udt_dimm_row = 0,
1372 	.udt_dimm_bank = 0,
1373 	.udt_dimm_bank_group = 0,
1374 	.udt_dimm_subchan = UINT8_MAX,
1375 	.udt_dimm_rm = 0,
1376 	.udt_dimm_cs = 0
1377 }, {
1378 	.udt_desc = "ILV: 2/1/4 2P-way, 4-way Channel (2)",
1379 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1380 	.udt_pa = 0xbadc201ff,
1381 	.udt_pass = B_TRUE,
1382 	.udt_norm_addr = 0x175b841ff,
1383 	.udt_sock = 0,
1384 	.udt_die = 0,
1385 	.udt_comp = 0,
1386 	.udt_dimm_no = 0,
1387 	.udt_dimm_col = 0x3f,
1388 	.udt_dimm_row = 0xbadc,
1389 	.udt_dimm_bank = 2,
1390 	.udt_dimm_bank_group = 0,
1391 	.udt_dimm_subchan = UINT8_MAX,
1392 	.udt_dimm_rm = 0,
1393 	.udt_dimm_cs = 0
1394 }, {
1395 	.udt_desc = "ilv: 2/1/4 2p-way, 4-way channel (3)",
1396 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1397 	.udt_pa = 0xbadc205ff,
1398 	.udt_pass = B_TRUE,
1399 	.udt_norm_addr = 0x175b841ff,
1400 	.udt_sock = 0,
1401 	.udt_die = 0,
1402 	.udt_comp = 1,
1403 	.udt_dimm_no = 0,
1404 	.udt_dimm_col = 0x3f,
1405 	.udt_dimm_row = 0xbadc,
1406 	.udt_dimm_bank = 2,
1407 	.udt_dimm_bank_group = 0,
1408 	.udt_dimm_subchan = UINT8_MAX,
1409 	.udt_dimm_rm = 0,
1410 	.udt_dimm_cs = 0
1411 }, {
1412 	.udt_desc = "ilv: 2/1/4 2p-way, 4-way channel (4)",
1413 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1414 	.udt_pa = 0xbadc209ff,
1415 	.udt_pass = B_TRUE,
1416 	.udt_norm_addr = 0x175b841ff,
1417 	.udt_sock = 0,
1418 	.udt_die = 0,
1419 	.udt_comp = 2,
1420 	.udt_dimm_no = 0,
1421 	.udt_dimm_col = 0x3f,
1422 	.udt_dimm_row = 0xbadc,
1423 	.udt_dimm_bank = 2,
1424 	.udt_dimm_bank_group = 0,
1425 	.udt_dimm_subchan = UINT8_MAX,
1426 	.udt_dimm_rm = 0,
1427 	.udt_dimm_cs = 0
1428 }, {
1429 	.udt_desc = "ilv: 2/1/4 2p-way, 4-way channel (5)",
1430 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1431 	.udt_pa = 0xbadc20dff,
1432 	.udt_pass = B_TRUE,
1433 	.udt_norm_addr = 0x175b841ff,
1434 	.udt_sock = 0,
1435 	.udt_die = 0,
1436 	.udt_comp = 3,
1437 	.udt_dimm_no = 0,
1438 	.udt_dimm_col = 0x3f,
1439 	.udt_dimm_row = 0xbadc,
1440 	.udt_dimm_bank = 2,
1441 	.udt_dimm_bank_group = 0,
1442 	.udt_dimm_subchan = UINT8_MAX,
1443 	.udt_dimm_rm = 0,
1444 	.udt_dimm_cs = 0
1445 }, {
1446 	.udt_desc = "ILV: 2/1/4 2P-way, 4-way Channel (6)",
1447 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1448 	.udt_pa = 0xbadc211ff,
1449 	.udt_pass = B_TRUE,
1450 	.udt_norm_addr = 0x175b841ff,
1451 	.udt_sock = 1,
1452 	.udt_die = 0,
1453 	.udt_comp = 0,
1454 	.udt_dimm_no = 0,
1455 	.udt_dimm_col = 0x3f,
1456 	.udt_dimm_row = 0xbadc,
1457 	.udt_dimm_bank = 2,
1458 	.udt_dimm_bank_group = 0,
1459 	.udt_dimm_subchan = UINT8_MAX,
1460 	.udt_dimm_rm = 0,
1461 	.udt_dimm_cs = 0
1462 }, {
1463 	.udt_desc = "ilv: 2/1/4 2p-way, 4-way channel (7)",
1464 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1465 	.udt_pa = 0xbadc215ff,
1466 	.udt_pass = B_TRUE,
1467 	.udt_norm_addr = 0x175b841ff,
1468 	.udt_sock = 1,
1469 	.udt_die = 0,
1470 	.udt_comp = 1,
1471 	.udt_dimm_no = 0,
1472 	.udt_dimm_col = 0x3f,
1473 	.udt_dimm_row = 0xbadc,
1474 	.udt_dimm_bank = 2,
1475 	.udt_dimm_bank_group = 0,
1476 	.udt_dimm_subchan = UINT8_MAX,
1477 	.udt_dimm_rm = 0,
1478 	.udt_dimm_cs = 0
1479 }, {
1480 	.udt_desc = "ilv: 2/1/4 2p-way, 4-way channel (8)",
1481 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1482 	.udt_pa = 0xbadc219ff,
1483 	.udt_pass = B_TRUE,
1484 	.udt_norm_addr = 0x175b841ff,
1485 	.udt_sock = 1,
1486 	.udt_die = 0,
1487 	.udt_comp = 2,
1488 	.udt_dimm_no = 0,
1489 	.udt_dimm_col = 0x3f,
1490 	.udt_dimm_row = 0xbadc,
1491 	.udt_dimm_bank = 2,
1492 	.udt_dimm_bank_group = 0,
1493 	.udt_dimm_subchan = UINT8_MAX,
1494 	.udt_dimm_rm = 0,
1495 	.udt_dimm_cs = 0
1496 }, {
1497 	.udt_desc = "ilv: 2/1/4 2p-way, 4-way channel (9)",
1498 	.udt_umc = &zen_umc_ilv_2p1d4c_2s4ch,
1499 	.udt_pa = 0xbadc21dff,
1500 	.udt_pass = B_TRUE,
1501 	.udt_norm_addr = 0x175b841ff,
1502 	.udt_sock = 1,
1503 	.udt_die = 0,
1504 	.udt_comp = 3,
1505 	.udt_dimm_no = 0,
1506 	.udt_dimm_col = 0x3f,
1507 	.udt_dimm_row = 0xbadc,
1508 	.udt_dimm_bank = 2,
1509 	.udt_dimm_bank_group = 0,
1510 	.udt_dimm_subchan = UINT8_MAX,
1511 	.udt_dimm_rm = 0,
1512 	.udt_dimm_cs = 0
1513 }, {
1514 	.udt_desc = "ilv: 1/2/2 2-way die, 2-way channel (0)",
1515 	.udt_umc = &zen_umc_ilv_1p2d2c_2d2ch,
1516 	.udt_pa = 0x12233cfbb,
1517 	.udt_pass = B_TRUE,
1518 	.udt_norm_addr = 0x488cffbb,
1519 	.udt_sock = 0,
1520 	.udt_die = 0,
1521 	.udt_comp = 0,
1522 	.udt_dimm_no = 0,
1523 	.udt_dimm_col = 0x3f7,
1524 	.udt_dimm_row = 0x2446,
1525 	.udt_dimm_bank = 3,
1526 	.udt_dimm_bank_group = 1,
1527 	.udt_dimm_subchan = UINT8_MAX,
1528 	.udt_dimm_rm = 0,
1529 	.udt_dimm_cs = 0
1530 }, {
1531 	.udt_desc = "ilv: 1/2/2 2-way die, 2-way channel (1)",
1532 	.udt_umc = &zen_umc_ilv_1p2d2c_2d2ch,
1533 	.udt_pa = 0x12233efbb,
1534 	.udt_pass = B_TRUE,
1535 	.udt_norm_addr = 0x488cffbb,
1536 	.udt_sock = 0,
1537 	.udt_die = 1,
1538 	.udt_comp = 0,
1539 	.udt_dimm_no = 0,
1540 	.udt_dimm_col = 0x3f7,
1541 	.udt_dimm_row = 0x2446,
1542 	.udt_dimm_bank = 3,
1543 	.udt_dimm_bank_group = 1,
1544 	.udt_dimm_subchan = UINT8_MAX,
1545 	.udt_dimm_rm = 0,
1546 	.udt_dimm_cs = 0
1547 }, {
1548 	.udt_desc = "ilv: 1/2/2 2-way die, 2-way channel (2)",
1549 	.udt_umc = &zen_umc_ilv_1p2d2c_2d2ch,
1550 	.udt_pa = 0x12233ffbb,
1551 	.udt_pass = B_TRUE,
1552 	.udt_norm_addr = 0x488cffbb,
1553 	.udt_sock = 0,
1554 	.udt_die = 1,
1555 	.udt_comp = 1,
1556 	.udt_dimm_no = 0,
1557 	.udt_dimm_col = 0x3f7,
1558 	.udt_dimm_row = 0x2446,
1559 	.udt_dimm_bank = 3,
1560 	.udt_dimm_bank_group = 1,
1561 	.udt_dimm_subchan = UINT8_MAX,
1562 	.udt_dimm_rm = 0,
1563 	.udt_dimm_cs = 0
1564 }, {
1565 	.udt_desc = "ilv: 1/2/2 2-way die, 2-way channel (3)",
1566 	.udt_umc = &zen_umc_ilv_1p2d2c_2d2ch,
1567 	.udt_pa = 0x12233dfbb,
1568 	.udt_pass = B_TRUE,
1569 	.udt_norm_addr = 0x488cffbb,
1570 	.udt_sock = 0,
1571 	.udt_die = 0,
1572 	.udt_comp = 1,
1573 	.udt_dimm_no = 0,
1574 	.udt_dimm_col = 0x3f7,
1575 	.udt_dimm_row = 0x2446,
1576 	.udt_dimm_bank = 3,
1577 	.udt_dimm_bank_group = 1,
1578 	.udt_dimm_subchan = UINT8_MAX,
1579 	.udt_dimm_rm = 0,
1580 	.udt_dimm_cs = 0
1581 }, {
1582 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (0)",
1583 	.udt_umc = &zen_umc_ilv_naplesish,
1584 	.udt_pa = 0xffed37f42,
1585 	.udt_pass = B_TRUE,
1586 	.udt_norm_addr = 0x1ffda6f42,
1587 	.udt_sock = 1,
1588 	.udt_die = 1,
1589 	.udt_comp = 1,
1590 	.udt_dimm_no = 0,
1591 	.udt_dimm_col = 0x1e8,
1592 	.udt_dimm_row = 0xffed,
1593 	.udt_dimm_bank = 3,
1594 	.udt_dimm_bank_group = 0,
1595 	.udt_dimm_subchan = UINT8_MAX,
1596 	.udt_dimm_rm = 0,
1597 	.udt_dimm_cs = 0
1598 }, {
1599 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (1)",
1600 	.udt_umc = &zen_umc_ilv_naplesish,
1601 	.udt_pa = 0xffed37e42,
1602 	.udt_pass = B_TRUE,
1603 	.udt_norm_addr = 0x1ffda6f42,
1604 	.udt_sock = 1,
1605 	.udt_die = 1,
1606 	.udt_comp = 0,
1607 	.udt_dimm_no = 0,
1608 	.udt_dimm_col = 0x1e8,
1609 	.udt_dimm_row = 0xffed,
1610 	.udt_dimm_bank = 3,
1611 	.udt_dimm_bank_group = 0,
1612 	.udt_dimm_subchan = UINT8_MAX,
1613 	.udt_dimm_rm = 0,
1614 	.udt_dimm_cs = 0
1615 }, {
1616 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (2)",
1617 	.udt_umc = &zen_umc_ilv_naplesish,
1618 	.udt_pa = 0xffed37d42,
1619 	.udt_pass = B_TRUE,
1620 	.udt_norm_addr = 0x1ffda6f42,
1621 	.udt_sock = 1,
1622 	.udt_die = 0,
1623 	.udt_comp = 1,
1624 	.udt_dimm_no = 0,
1625 	.udt_dimm_col = 0x1e8,
1626 	.udt_dimm_row = 0xffed,
1627 	.udt_dimm_bank = 3,
1628 	.udt_dimm_bank_group = 0,
1629 	.udt_dimm_subchan = UINT8_MAX,
1630 	.udt_dimm_rm = 0,
1631 	.udt_dimm_cs = 0
1632 }, {
1633 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (3)",
1634 	.udt_umc = &zen_umc_ilv_naplesish,
1635 	.udt_pa = 0xffed37c42,
1636 	.udt_pass = B_TRUE,
1637 	.udt_norm_addr = 0x1ffda6f42,
1638 	.udt_sock = 1,
1639 	.udt_die = 0,
1640 	.udt_comp = 0,
1641 	.udt_dimm_no = 0,
1642 	.udt_dimm_col = 0x1e8,
1643 	.udt_dimm_row = 0xffed,
1644 	.udt_dimm_bank = 3,
1645 	.udt_dimm_bank_group = 0,
1646 	.udt_dimm_subchan = UINT8_MAX,
1647 	.udt_dimm_rm = 0,
1648 	.udt_dimm_cs = 0
1649 }, {
1650 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (4)",
1651 	.udt_umc = &zen_umc_ilv_naplesish,
1652 	.udt_pa = 0xffed37b42,
1653 	.udt_pass = B_TRUE,
1654 	.udt_norm_addr = 0x1ffda6f42,
1655 	.udt_sock = 0,
1656 	.udt_die = 1,
1657 	.udt_comp = 1,
1658 	.udt_dimm_no = 0,
1659 	.udt_dimm_col = 0x1e8,
1660 	.udt_dimm_row = 0xffed,
1661 	.udt_dimm_bank = 3,
1662 	.udt_dimm_bank_group = 0,
1663 	.udt_dimm_subchan = UINT8_MAX,
1664 	.udt_dimm_rm = 0,
1665 	.udt_dimm_cs = 0
1666 }, {
1667 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (5)",
1668 	.udt_umc = &zen_umc_ilv_naplesish,
1669 	.udt_pa = 0xffed37a42,
1670 	.udt_pass = B_TRUE,
1671 	.udt_norm_addr = 0x1ffda6f42,
1672 	.udt_sock = 0,
1673 	.udt_die = 1,
1674 	.udt_comp = 0,
1675 	.udt_dimm_no = 0,
1676 	.udt_dimm_col = 0x1e8,
1677 	.udt_dimm_row = 0xffed,
1678 	.udt_dimm_bank = 3,
1679 	.udt_dimm_bank_group = 0,
1680 	.udt_dimm_subchan = UINT8_MAX,
1681 	.udt_dimm_rm = 0,
1682 	.udt_dimm_cs = 0
1683 }, {
1684 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (6)",
1685 	.udt_umc = &zen_umc_ilv_naplesish,
1686 	.udt_pa = 0xffed37942,
1687 	.udt_pass = B_TRUE,
1688 	.udt_norm_addr = 0x1ffda6f42,
1689 	.udt_sock = 0,
1690 	.udt_die = 0,
1691 	.udt_comp = 1,
1692 	.udt_dimm_no = 0,
1693 	.udt_dimm_col = 0x1e8,
1694 	.udt_dimm_row = 0xffed,
1695 	.udt_dimm_bank = 3,
1696 	.udt_dimm_bank_group = 0,
1697 	.udt_dimm_subchan = UINT8_MAX,
1698 	.udt_dimm_rm = 0,
1699 	.udt_dimm_cs = 0
1700 }, {
1701 	.udt_desc = "ilv: 2/2/2 2-way sock, 2-way die, 2-way channel (7)",
1702 	.udt_umc = &zen_umc_ilv_naplesish,
1703 	.udt_pa = 0xffed37842,
1704 	.udt_pass = B_TRUE,
1705 	.udt_norm_addr = 0x1ffda6f42,
1706 	.udt_sock = 0,
1707 	.udt_die = 0,
1708 	.udt_comp = 0,
1709 	.udt_dimm_no = 0,
1710 	.udt_dimm_col = 0x1e8,
1711 	.udt_dimm_row = 0xffed,
1712 	.udt_dimm_bank = 3,
1713 	.udt_dimm_bank_group = 0,
1714 	.udt_dimm_subchan = UINT8_MAX,
1715 	.udt_dimm_rm = 0,
1716 	.udt_dimm_cs = 0
1717 }, {
1718 	.udt_desc = NULL
1719 } };
1720