xref: /illumos-gate/usr/src/test/os-tests/tests/zen_umc/zen_umc_test_cod.c (revision 0dd92943508086ca1800de461a7c66109737bcd5)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2023 Oxide Computer Company
14  */
15 
16 /*
17  * Here we try to test a few variants of the Zen 3 COD based hashing, including
18  * our favorite 6 channel. These all use DFv3 and 1 DPC 16 GiB channels without
19  * any internal hashing (that is tested elsewhere).
20  */
21 
22 #include "zen_umc_test.h"
23 
24 /*
25  * This is a basic 4-channel hash, sending us out to one of four locations. This
26  * enables hashing in all three regions because 6 channel variant does not seem
27  * to use them.
28  */
29 static const zen_umc_t zen_umc_cod_4ch = {
30 	.umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL,
31 	.umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL,
32 	.umc_df_rev = DF_REV_3,
33 	.umc_decomp = {
34 		.dfd_sock_mask = 0x01,
35 		.dfd_die_mask = 0x00,
36 		.dfd_node_mask = 0x20,
37 		.dfd_comp_mask = 0x1f,
38 		.dfd_sock_shift = 0,
39 		.dfd_die_shift = 0,
40 		.dfd_node_shift = 5,
41 		.dfd_comp_shift = 0
42 	},
43 	.umc_ndfs = 1,
44 	.umc_dfs = { {
45 		.zud_dfno = 0,
46 		.zud_dram_nrules = 1,
47 		.zud_nchan = 4,
48 		.zud_cs_nremap = 0,
49 		.zud_hole_base = 0,
50 		.zud_rules = { {
51 			.ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_16_18 |
52 			    DF_DRAM_F_HASH_21_23 | DF_DRAM_F_HASH_30_32,
53 			.ddr_base = 0,
54 			.ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL,
55 			.ddr_dest_fabid = 0,
56 			.ddr_sock_ileave_bits = 0,
57 			.ddr_die_ileave_bits = 0,
58 			.ddr_addr_start = 9,
59 			.ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH
60 		} },
61 		.zud_chan = { {
62 			.chan_flags = UMC_CHAN_F_ECC_EN,
63 			.chan_fabid = 0,
64 			.chan_instid = 0,
65 			.chan_logid = 0,
66 			.chan_nrules = 1,
67 			.chan_type = UMC_DIMM_T_DDR4,
68 			.chan_rules = { {
69 				.ddr_flags = DF_DRAM_F_VALID |
70 				    DF_DRAM_F_HASH_16_18 |
71 				    DF_DRAM_F_HASH_21_23 |
72 				    DF_DRAM_F_HASH_30_32,
73 				.ddr_base = 0,
74 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
75 				    1024ULL,
76 				.ddr_dest_fabid = 0,
77 				.ddr_sock_ileave_bits = 0,
78 				.ddr_die_ileave_bits = 0,
79 				.ddr_addr_start = 9,
80 				.ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH
81 			} },
82 			.chan_dimms = { {
83 				.ud_flags = UMC_DIMM_F_VALID,
84 				.ud_width = UMC_DIMM_W_X4,
85 				.ud_kind = UMC_DIMM_K_RDIMM,
86 				.ud_dimmno = 0,
87 				.ud_cs = { {
88 					.ucs_base = {
89 						.udb_base = 0,
90 						.udb_valid = B_TRUE
91 					},
92 					.ucs_base_mask = 0x3ffffffff,
93 					.ucs_nbanks = 0x4,
94 					.ucs_ncol = 0xa,
95 					.ucs_nrow_lo = 0x11,
96 					.ucs_nbank_groups = 0x2,
97 					.ucs_row_hi_bit = 0x18,
98 					.ucs_row_low_bit = 0x11,
99 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
100 					    0xe },
101 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
102 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
103 				} }
104 			} },
105 		}, {
106 			.chan_flags = UMC_CHAN_F_ECC_EN,
107 			.chan_fabid = 1,
108 			.chan_instid = 1,
109 			.chan_logid = 1,
110 			.chan_nrules = 1,
111 			.chan_rules = { {
112 				.ddr_flags = DF_DRAM_F_VALID |
113 				    DF_DRAM_F_HASH_16_18 |
114 				    DF_DRAM_F_HASH_21_23 |
115 				    DF_DRAM_F_HASH_30_32,
116 				.ddr_base = 0,
117 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
118 				    1024ULL,
119 				.ddr_dest_fabid = 0,
120 				.ddr_sock_ileave_bits = 0,
121 				.ddr_die_ileave_bits = 0,
122 				.ddr_addr_start = 9,
123 				.ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH
124 			} },
125 			.chan_dimms = { {
126 				.ud_flags = UMC_DIMM_F_VALID,
127 				.ud_width = UMC_DIMM_W_X4,
128 				.ud_kind = UMC_DIMM_K_RDIMM,
129 				.ud_dimmno = 0,
130 				.ud_cs = { {
131 					.ucs_base = {
132 						.udb_base = 0,
133 						.udb_valid = B_TRUE
134 					},
135 					.ucs_base_mask = 0x3ffffffff,
136 					.ucs_nbanks = 0x4,
137 					.ucs_ncol = 0xa,
138 					.ucs_nrow_lo = 0x11,
139 					.ucs_nbank_groups = 0x2,
140 					.ucs_row_hi_bit = 0x18,
141 					.ucs_row_low_bit = 0x11,
142 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
143 					    0xe },
144 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
145 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
146 				} }
147 			} },
148 		}, {
149 			.chan_flags = UMC_CHAN_F_ECC_EN,
150 			.chan_fabid = 2,
151 			.chan_instid = 2,
152 			.chan_logid = 2,
153 			.chan_nrules = 1,
154 			.chan_type = UMC_DIMM_T_DDR4,
155 			.chan_rules = { {
156 				.ddr_flags = DF_DRAM_F_VALID |
157 				    DF_DRAM_F_HASH_16_18 |
158 				    DF_DRAM_F_HASH_21_23 |
159 				    DF_DRAM_F_HASH_30_32,
160 				.ddr_base = 0,
161 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
162 				    1024ULL,
163 				.ddr_dest_fabid = 0,
164 				.ddr_sock_ileave_bits = 0,
165 				.ddr_die_ileave_bits = 0,
166 				.ddr_addr_start = 9,
167 				.ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH
168 			} },
169 			.chan_dimms = { {
170 				.ud_flags = UMC_DIMM_F_VALID,
171 				.ud_width = UMC_DIMM_W_X4,
172 				.ud_kind = UMC_DIMM_K_RDIMM,
173 				.ud_dimmno = 0,
174 				.ud_cs = { {
175 					.ucs_base = {
176 						.udb_base = 0,
177 						.udb_valid = B_TRUE
178 					},
179 					.ucs_base_mask = 0x3ffffffff,
180 					.ucs_nbanks = 0x4,
181 					.ucs_ncol = 0xa,
182 					.ucs_nrow_lo = 0x11,
183 					.ucs_nbank_groups = 0x2,
184 					.ucs_row_hi_bit = 0x18,
185 					.ucs_row_low_bit = 0x11,
186 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
187 					    0xe },
188 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
189 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
190 				} }
191 			} },
192 		}, {
193 			.chan_flags = UMC_CHAN_F_ECC_EN,
194 			.chan_fabid = 3,
195 			.chan_instid = 3,
196 			.chan_logid = 3,
197 			.chan_nrules = 1,
198 			.chan_type = UMC_DIMM_T_DDR4,
199 			.chan_rules = { {
200 				.ddr_flags = DF_DRAM_F_VALID |
201 				    DF_DRAM_F_HASH_16_18 |
202 				    DF_DRAM_F_HASH_21_23 |
203 				    DF_DRAM_F_HASH_30_32,
204 				.ddr_base = 0,
205 				.ddr_limit = 64ULL * 1024ULL * 1024ULL *
206 				    1024ULL,
207 				.ddr_dest_fabid = 0,
208 				.ddr_sock_ileave_bits = 0,
209 				.ddr_die_ileave_bits = 0,
210 				.ddr_addr_start = 9,
211 				.ddr_chan_ileave = DF_CHAN_ILEAVE_COD2_4CH
212 			} },
213 			.chan_dimms = { {
214 				.ud_flags = UMC_DIMM_F_VALID,
215 				.ud_width = UMC_DIMM_W_X4,
216 				.ud_kind = UMC_DIMM_K_RDIMM,
217 				.ud_dimmno = 0,
218 				.ud_cs = { {
219 					.ucs_base = {
220 						.udb_base = 0,
221 						.udb_valid = B_TRUE
222 					},
223 					.ucs_base_mask = 0x3ffffffff,
224 					.ucs_nbanks = 0x4,
225 					.ucs_ncol = 0xa,
226 					.ucs_nrow_lo = 0x11,
227 					.ucs_nbank_groups = 0x2,
228 					.ucs_row_hi_bit = 0x18,
229 					.ucs_row_low_bit = 0x11,
230 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
231 					    0xe },
232 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
233 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
234 				} }
235 			} },
236 		}  }
237 	} }
238 };
239 
240 static const zen_umc_t zen_umc_cod_6ch = {
241 	.umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL,
242 	.umc_tom2 = 96ULL * 1024ULL * 1024ULL * 1024ULL,
243 	.umc_df_rev = DF_REV_3,
244 	.umc_decomp = {
245 		.dfd_sock_mask = 0x01,
246 		.dfd_die_mask = 0x00,
247 		.dfd_node_mask = 0x20,
248 		.dfd_comp_mask = 0x1f,
249 		.dfd_sock_shift = 0,
250 		.dfd_die_shift = 0,
251 		.dfd_node_shift = 5,
252 		.dfd_comp_shift = 0
253 	},
254 	.umc_ndfs = 1,
255 	.umc_dfs = { {
256 		.zud_dfno = 0,
257 		.zud_dram_nrules = 1,
258 		.zud_nchan = 6,
259 		.zud_cs_nremap = 0,
260 		.zud_hole_base = 0,
261 		.zud_rules = { {
262 			.ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HASH_21_23 |
263 			    DF_DRAM_F_HASH_30_32,
264 			.ddr_base = 0,
265 			.ddr_limit = 96ULL * 1024ULL * 1024ULL * 1024ULL,
266 			.ddr_dest_fabid = 0,
267 			.ddr_sock_ileave_bits = 0,
268 			.ddr_die_ileave_bits = 0,
269 			.ddr_addr_start = 12,
270 			.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
271 		} },
272 		.zud_chan = { {
273 			.chan_flags = UMC_CHAN_F_ECC_EN,
274 			.chan_fabid = 0,
275 			.chan_instid = 0,
276 			.chan_logid = 0,
277 			.chan_nrules = 1,
278 			.chan_type = UMC_DIMM_T_DDR4,
279 			.chan_np2_space0 = 21,
280 			.chan_rules = { {
281 				.ddr_flags = DF_DRAM_F_VALID |
282 				    DF_DRAM_F_HASH_21_23 |
283 				    DF_DRAM_F_HASH_30_32,
284 				.ddr_base = 0,
285 				.ddr_limit = 96ULL * 1024ULL * 1024ULL *
286 				    1024ULL,
287 				.ddr_dest_fabid = 0,
288 				.ddr_sock_ileave_bits = 0,
289 				.ddr_die_ileave_bits = 0,
290 				.ddr_addr_start = 12,
291 				.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
292 			} },
293 			.chan_dimms = { {
294 				.ud_flags = UMC_DIMM_F_VALID,
295 				.ud_width = UMC_DIMM_W_X4,
296 				.ud_kind = UMC_DIMM_K_RDIMM,
297 				.ud_dimmno = 0,
298 				.ud_cs = { {
299 					.ucs_base = {
300 						.udb_base = 0,
301 						.udb_valid = B_TRUE
302 					},
303 					.ucs_base_mask = 0x3ffffffff,
304 					.ucs_nbanks = 0x4,
305 					.ucs_ncol = 0xa,
306 					.ucs_nrow_lo = 0x11,
307 					.ucs_nbank_groups = 0x2,
308 					.ucs_row_hi_bit = 0x18,
309 					.ucs_row_low_bit = 0x11,
310 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
311 					    0xe },
312 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
313 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
314 				} }
315 			} },
316 		}, {
317 			.chan_flags = UMC_CHAN_F_ECC_EN,
318 			.chan_fabid = 1,
319 			.chan_instid = 1,
320 			.chan_logid = 1,
321 			.chan_nrules = 1,
322 			.chan_np2_space0 = 21,
323 			.chan_type = UMC_DIMM_T_DDR4,
324 			.chan_rules = { {
325 				.ddr_flags = DF_DRAM_F_VALID |
326 				    DF_DRAM_F_HASH_21_23 |
327 				    DF_DRAM_F_HASH_30_32,
328 				.ddr_base = 0,
329 				.ddr_limit = 96ULL * 1024ULL * 1024ULL *
330 				    1024ULL,
331 				.ddr_dest_fabid = 0,
332 				.ddr_sock_ileave_bits = 0,
333 				.ddr_die_ileave_bits = 0,
334 				.ddr_addr_start = 12,
335 				.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
336 			} },
337 			.chan_dimms = { {
338 				.ud_flags = UMC_DIMM_F_VALID,
339 				.ud_width = UMC_DIMM_W_X4,
340 				.ud_kind = UMC_DIMM_K_RDIMM,
341 				.ud_dimmno = 0,
342 				.ud_cs = { {
343 					.ucs_base = {
344 						.udb_base = 0,
345 						.udb_valid = B_TRUE
346 					},
347 					.ucs_base_mask = 0x3ffffffff,
348 					.ucs_nbanks = 0x4,
349 					.ucs_ncol = 0xa,
350 					.ucs_nrow_lo = 0x11,
351 					.ucs_nbank_groups = 0x2,
352 					.ucs_row_hi_bit = 0x18,
353 					.ucs_row_low_bit = 0x11,
354 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
355 					    0xe },
356 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
357 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
358 				} }
359 			} },
360 		}, {
361 			.chan_flags = UMC_CHAN_F_ECC_EN,
362 			.chan_fabid = 2,
363 			.chan_instid = 2,
364 			.chan_logid = 2,
365 			.chan_nrules = 1,
366 			.chan_np2_space0 = 21,
367 			.chan_type = UMC_DIMM_T_DDR4,
368 			.chan_rules = { {
369 				.ddr_flags = DF_DRAM_F_VALID |
370 				    DF_DRAM_F_HASH_21_23 |
371 				    DF_DRAM_F_HASH_30_32,
372 				.ddr_base = 0,
373 				.ddr_limit = 96ULL * 1024ULL * 1024ULL *
374 				    1024ULL,
375 				.ddr_dest_fabid = 0,
376 				.ddr_sock_ileave_bits = 0,
377 				.ddr_die_ileave_bits = 0,
378 				.ddr_addr_start = 12,
379 				.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
380 			} },
381 			.chan_dimms = { {
382 				.ud_flags = UMC_DIMM_F_VALID,
383 				.ud_width = UMC_DIMM_W_X4,
384 				.ud_kind = UMC_DIMM_K_RDIMM,
385 				.ud_dimmno = 0,
386 				.ud_cs = { {
387 					.ucs_base = {
388 						.udb_base = 0,
389 						.udb_valid = B_TRUE
390 					},
391 					.ucs_base_mask = 0x3ffffffff,
392 					.ucs_nbanks = 0x4,
393 					.ucs_ncol = 0xa,
394 					.ucs_nrow_lo = 0x11,
395 					.ucs_nbank_groups = 0x2,
396 					.ucs_row_hi_bit = 0x18,
397 					.ucs_row_low_bit = 0x11,
398 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
399 					    0xe },
400 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
401 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
402 				} }
403 			} },
404 		}, {
405 			.chan_flags = UMC_CHAN_F_ECC_EN,
406 			.chan_fabid = 3,
407 			.chan_instid = 3,
408 			.chan_logid = 3,
409 			.chan_nrules = 1,
410 			.chan_np2_space0 = 21,
411 			.chan_type = UMC_DIMM_T_DDR4,
412 			.chan_rules = { {
413 				.ddr_flags = DF_DRAM_F_VALID |
414 				    DF_DRAM_F_HASH_21_23 |
415 				    DF_DRAM_F_HASH_30_32,
416 				.ddr_base = 0,
417 				.ddr_limit = 96ULL * 1024ULL * 1024ULL *
418 				    1024ULL,
419 				.ddr_dest_fabid = 0,
420 				.ddr_sock_ileave_bits = 0,
421 				.ddr_die_ileave_bits = 0,
422 				.ddr_addr_start = 12,
423 				.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
424 			} },
425 			.chan_dimms = { {
426 				.ud_flags = UMC_DIMM_F_VALID,
427 				.ud_width = UMC_DIMM_W_X4,
428 				.ud_kind = UMC_DIMM_K_RDIMM,
429 				.ud_dimmno = 0,
430 				.ud_cs = { {
431 					.ucs_base = {
432 						.udb_base = 0,
433 						.udb_valid = B_TRUE
434 					},
435 					.ucs_base_mask = 0x3ffffffff,
436 					.ucs_nbanks = 0x4,
437 					.ucs_ncol = 0xa,
438 					.ucs_nrow_lo = 0x11,
439 					.ucs_nbank_groups = 0x2,
440 					.ucs_row_hi_bit = 0x18,
441 					.ucs_row_low_bit = 0x11,
442 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
443 					    0xe },
444 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
445 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
446 				} }
447 			} },
448 		}, {
449 			.chan_flags = UMC_CHAN_F_ECC_EN,
450 			.chan_fabid = 4,
451 			.chan_instid = 4,
452 			.chan_logid = 4,
453 			.chan_nrules = 1,
454 			.chan_np2_space0 = 21,
455 			.chan_type = UMC_DIMM_T_DDR4,
456 			.chan_rules = { {
457 				.ddr_flags = DF_DRAM_F_VALID |
458 				    DF_DRAM_F_HASH_21_23 |
459 				    DF_DRAM_F_HASH_30_32,
460 				.ddr_base = 0,
461 				.ddr_limit = 96ULL * 1024ULL * 1024ULL *
462 				    1024ULL,
463 				.ddr_dest_fabid = 0,
464 				.ddr_sock_ileave_bits = 0,
465 				.ddr_die_ileave_bits = 0,
466 				.ddr_addr_start = 12,
467 				.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
468 			} },
469 			.chan_dimms = { {
470 				.ud_flags = UMC_DIMM_F_VALID,
471 				.ud_width = UMC_DIMM_W_X4,
472 				.ud_kind = UMC_DIMM_K_RDIMM,
473 				.ud_dimmno = 0,
474 				.ud_cs = { {
475 					.ucs_base = {
476 						.udb_base = 0,
477 						.udb_valid = B_TRUE
478 					},
479 					.ucs_base_mask = 0x3ffffffff,
480 					.ucs_nbanks = 0x4,
481 					.ucs_ncol = 0xa,
482 					.ucs_nrow_lo = 0x11,
483 					.ucs_nbank_groups = 0x2,
484 					.ucs_row_hi_bit = 0x18,
485 					.ucs_row_low_bit = 0x11,
486 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
487 					    0xe },
488 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
489 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
490 				} }
491 			} },
492 		}, {
493 			.chan_flags = UMC_CHAN_F_ECC_EN,
494 			.chan_fabid = 5,
495 			.chan_instid = 5,
496 			.chan_logid = 5,
497 			.chan_nrules = 1,
498 			.chan_np2_space0 = 21,
499 			.chan_type = UMC_DIMM_T_DDR4,
500 			.chan_rules = { {
501 				.ddr_flags = DF_DRAM_F_VALID |
502 				    DF_DRAM_F_HASH_21_23 |
503 				    DF_DRAM_F_HASH_30_32,
504 				.ddr_base = 0,
505 				.ddr_limit = 96ULL * 1024ULL * 1024ULL *
506 				    1024ULL,
507 				.ddr_dest_fabid = 0,
508 				.ddr_sock_ileave_bits = 0,
509 				.ddr_die_ileave_bits = 0,
510 				.ddr_addr_start = 12,
511 				.ddr_chan_ileave = DF_CHAN_ILEAVE_6CH
512 			} },
513 			.chan_dimms = { {
514 				.ud_flags = UMC_DIMM_F_VALID,
515 				.ud_width = UMC_DIMM_W_X4,
516 				.ud_kind = UMC_DIMM_K_RDIMM,
517 				.ud_dimmno = 0,
518 				.ud_cs = { {
519 					.ucs_base = {
520 						.udb_base = 0,
521 						.udb_valid = B_TRUE
522 					},
523 					.ucs_base_mask = 0x3ffffffff,
524 					.ucs_nbanks = 0x4,
525 					.ucs_ncol = 0xa,
526 					.ucs_nrow_lo = 0x11,
527 					.ucs_nbank_groups = 0x2,
528 					.ucs_row_hi_bit = 0x18,
529 					.ucs_row_low_bit = 0x11,
530 					.ucs_bank_bits = { 0xf, 0x10, 0xd,
531 					    0xe },
532 					.ucs_col_bits = { 0x3, 0x4, 0x5, 0x6,
533 					    0x7, 0x8, 0x9, 0xa, 0xb, 0xc }
534 				} }
535 			} },
536 		}  }
537 	} }
538 };
539 
540 const umc_decode_test_t zen_umc_test_cod[] = { {
541 	.udt_desc = "COD 4ch (0)",
542 	.udt_umc = &zen_umc_cod_4ch,
543 	.udt_pa = 0x1ff,
544 	.udt_pass = B_TRUE,
545 	.udt_norm_addr = 0x1ff,
546 	.udt_sock = 0,
547 	.udt_die = 0,
548 	.udt_comp = 0,
549 	.udt_dimm_no = 0,
550 	.udt_dimm_col = 0x3f,
551 	.udt_dimm_row = 0,
552 	.udt_dimm_bank = 0,
553 	.udt_dimm_bank_group = 0,
554 	.udt_dimm_subchan = UINT8_MAX,
555 	.udt_dimm_rm = 0,
556 	.udt_dimm_cs = 0
557 }, {
558 	.udt_desc = "COD 4ch (1)",
559 	.udt_umc = &zen_umc_cod_4ch,
560 	.udt_pa = 0x3ff,
561 	.udt_pass = B_TRUE,
562 	.udt_norm_addr = 0x1ff,
563 	.udt_sock = 0,
564 	.udt_die = 0,
565 	.udt_comp = 1,
566 	.udt_dimm_no = 0,
567 	.udt_dimm_col = 0x3f,
568 	.udt_dimm_row = 0,
569 	.udt_dimm_bank = 0,
570 	.udt_dimm_bank_group = 0,
571 	.udt_dimm_subchan = UINT8_MAX,
572 	.udt_dimm_rm = 0,
573 	.udt_dimm_cs = 0
574 },  {
575 	.udt_desc = "COD 4ch (2)",
576 	.udt_umc = &zen_umc_cod_4ch,
577 	.udt_pa = 0x11ff,
578 	.udt_pass = B_TRUE,
579 	.udt_norm_addr = 0x1ff,
580 	.udt_sock = 0,
581 	.udt_die = 0,
582 	.udt_comp = 2,
583 	.udt_dimm_no = 0,
584 	.udt_dimm_col = 0x3f,
585 	.udt_dimm_row = 0,
586 	.udt_dimm_bank = 0,
587 	.udt_dimm_bank_group = 0,
588 	.udt_dimm_subchan = UINT8_MAX,
589 	.udt_dimm_rm = 0,
590 	.udt_dimm_cs = 0
591 }, {
592 	.udt_desc = "COD 4ch (3)",
593 	.udt_umc = &zen_umc_cod_4ch,
594 	.udt_pa = 0x13ff,
595 	.udt_pass = B_TRUE,
596 	.udt_norm_addr = 0x1ff,
597 	.udt_sock = 0,
598 	.udt_die = 0,
599 	.udt_comp = 3,
600 	.udt_dimm_no = 0,
601 	.udt_dimm_col = 0x3f,
602 	.udt_dimm_row = 0,
603 	.udt_dimm_bank = 0,
604 	.udt_dimm_bank_group = 0,
605 	.udt_dimm_subchan = UINT8_MAX,
606 	.udt_dimm_rm = 0,
607 	.udt_dimm_cs = 0
608 }, {
609 	.udt_desc = "COD 4ch (4)",
610 	.udt_umc = &zen_umc_cod_4ch,
611 	.udt_pa = 0x101ff,
612 	.udt_pass = B_TRUE,
613 	.udt_norm_addr = 0x41ff,
614 	.udt_sock = 0,
615 	.udt_die = 0,
616 	.udt_comp = 1,
617 	.udt_dimm_no = 0,
618 	.udt_dimm_col = 0x3f,
619 	.udt_dimm_row = 0,
620 	.udt_dimm_bank = 2,
621 	.udt_dimm_bank_group = 0,
622 	.udt_dimm_subchan = UINT8_MAX,
623 	.udt_dimm_rm = 0,
624 	.udt_dimm_cs = 0
625 }, {
626 	.udt_desc = "COD 4ch (5)",
627 	.udt_umc = &zen_umc_cod_4ch,
628 	.udt_pa = 0x103ff,
629 	.udt_pass = B_TRUE,
630 	.udt_norm_addr = 0x41ff,
631 	.udt_sock = 0,
632 	.udt_die = 0,
633 	.udt_comp = 0,
634 	.udt_dimm_no = 0,
635 	.udt_dimm_col = 0x3f,
636 	.udt_dimm_row = 0,
637 	.udt_dimm_bank = 2,
638 	.udt_dimm_bank_group = 0,
639 	.udt_dimm_subchan = UINT8_MAX,
640 	.udt_dimm_rm = 0,
641 	.udt_dimm_cs = 0
642 }, {
643 	.udt_desc = "COD 4ch (6)",
644 	.udt_umc = &zen_umc_cod_4ch,
645 	.udt_pa = 0x303ff,
646 	.udt_pass = B_TRUE,
647 	.udt_norm_addr = 0xc1ff,
648 	.udt_sock = 0,
649 	.udt_die = 0,
650 	.udt_comp = 2,
651 	.udt_dimm_no = 0,
652 	.udt_dimm_col = 0x3f,
653 	.udt_dimm_row = 0,
654 	.udt_dimm_bank = 2,
655 	.udt_dimm_bank_group = 1,
656 	.udt_dimm_subchan = UINT8_MAX,
657 	.udt_dimm_rm = 0,
658 	.udt_dimm_cs = 0
659 }, {
660 	.udt_desc = "COD 4ch (7)",
661 	.udt_umc = &zen_umc_cod_4ch,
662 	.udt_pa = 0x313ff,
663 	.udt_pass = B_TRUE,
664 	.udt_norm_addr = 0xc1ff,
665 	.udt_sock = 0,
666 	.udt_die = 0,
667 	.udt_comp = 0,
668 	.udt_dimm_no = 0,
669 	.udt_dimm_col = 0x3f,
670 	.udt_dimm_row = 0,
671 	.udt_dimm_bank = 2,
672 	.udt_dimm_bank_group = 1,
673 	.udt_dimm_subchan = UINT8_MAX,
674 	.udt_dimm_rm = 0,
675 	.udt_dimm_cs = 0
676 }, {
677 	.udt_desc = "COD 4ch (8)",
678 	.udt_umc = &zen_umc_cod_4ch,
679 	.udt_pa = 0x311ff,
680 	.udt_pass = B_TRUE,
681 	.udt_norm_addr = 0xc1ff,
682 	.udt_sock = 0,
683 	.udt_die = 0,
684 	.udt_comp = 1,
685 	.udt_dimm_no = 0,
686 	.udt_dimm_col = 0x3f,
687 	.udt_dimm_row = 0,
688 	.udt_dimm_bank = 2,
689 	.udt_dimm_bank_group = 1,
690 	.udt_dimm_subchan = UINT8_MAX,
691 	.udt_dimm_rm = 0,
692 	.udt_dimm_cs = 0
693 }, {
694 	.udt_desc = "COD 4ch (9)",
695 	.udt_umc = &zen_umc_cod_4ch,
696 	.udt_pa = 0x2311ff,
697 	.udt_pass = B_TRUE,
698 	.udt_norm_addr = 0x8c1ff,
699 	.udt_sock = 0,
700 	.udt_die = 0,
701 	.udt_comp = 0,
702 	.udt_dimm_no = 0,
703 	.udt_dimm_col = 0x3f,
704 	.udt_dimm_row = 0x4,
705 	.udt_dimm_bank = 2,
706 	.udt_dimm_bank_group = 1,
707 	.udt_dimm_subchan = UINT8_MAX,
708 	.udt_dimm_rm = 0,
709 	.udt_dimm_cs = 0
710 }, {
711 	.udt_desc = "COD 4ch (10)",
712 	.udt_umc = &zen_umc_cod_4ch,
713 	.udt_pa = 0x6311ff,
714 	.udt_pass = B_TRUE,
715 	.udt_norm_addr = 0x18c1ff,
716 	.udt_sock = 0,
717 	.udt_die = 0,
718 	.udt_comp = 2,
719 	.udt_dimm_no = 0,
720 	.udt_dimm_col = 0x3f,
721 	.udt_dimm_row = 0xc,
722 	.udt_dimm_bank = 2,
723 	.udt_dimm_bank_group = 1,
724 	.udt_dimm_subchan = UINT8_MAX,
725 	.udt_dimm_rm = 0,
726 	.udt_dimm_cs = 0
727 }, {
728 	.udt_desc = "COD 4ch (11)",
729 	.udt_umc = &zen_umc_cod_4ch,
730 	.udt_pa = 0x6313ff,
731 	.udt_pass = B_TRUE,
732 	.udt_norm_addr = 0x18c1ff,
733 	.udt_sock = 0,
734 	.udt_die = 0,
735 	.udt_comp = 3,
736 	.udt_dimm_no = 0,
737 	.udt_dimm_col = 0x3f,
738 	.udt_dimm_row = 0xc,
739 	.udt_dimm_bank = 2,
740 	.udt_dimm_bank_group = 1,
741 	.udt_dimm_subchan = UINT8_MAX,
742 	.udt_dimm_rm = 0,
743 	.udt_dimm_cs = 0
744 }, {
745 	.udt_desc = "COD 4ch (12)",
746 	.udt_umc = &zen_umc_cod_4ch,
747 	.udt_pa = 0x6303ff,
748 	.udt_pass = B_TRUE,
749 	.udt_norm_addr = 0x18c1ff,
750 	.udt_sock = 0,
751 	.udt_die = 0,
752 	.udt_comp = 1,
753 	.udt_dimm_no = 0,
754 	.udt_dimm_col = 0x3f,
755 	.udt_dimm_row = 0xc,
756 	.udt_dimm_bank = 2,
757 	.udt_dimm_bank_group = 1,
758 	.udt_dimm_subchan = UINT8_MAX,
759 	.udt_dimm_rm = 0,
760 	.udt_dimm_cs = 0
761 }, {
762 	.udt_desc = "COD 4ch (13)",
763 	.udt_umc = &zen_umc_cod_4ch,
764 	.udt_pa = 0x6301ff,
765 	.udt_pass = B_TRUE,
766 	.udt_norm_addr = 0x18c1ff,
767 	.udt_sock = 0,
768 	.udt_die = 0,
769 	.udt_comp = 0,
770 	.udt_dimm_no = 0,
771 	.udt_dimm_col = 0x3f,
772 	.udt_dimm_row = 0xc,
773 	.udt_dimm_bank = 2,
774 	.udt_dimm_bank_group = 1,
775 	.udt_dimm_subchan = UINT8_MAX,
776 	.udt_dimm_rm = 0,
777 	.udt_dimm_cs = 0
778 }, {
779 	.udt_desc = "COD 4ch (14)",
780 	.udt_umc = &zen_umc_cod_4ch,
781 	.udt_pa = 0x406301ff,
782 	.udt_pass = B_TRUE,
783 	.udt_norm_addr = 0x1018c1ff,
784 	.udt_sock = 0,
785 	.udt_die = 0,
786 	.udt_comp = 1,
787 	.udt_dimm_no = 0,
788 	.udt_dimm_col = 0x3f,
789 	.udt_dimm_row = 0x80c,
790 	.udt_dimm_bank = 2,
791 	.udt_dimm_bank_group = 1,
792 	.udt_dimm_subchan = UINT8_MAX,
793 	.udt_dimm_rm = 0,
794 	.udt_dimm_cs = 0
795 }, {
796 	.udt_desc = "COD 4ch (15)",
797 	.udt_umc = &zen_umc_cod_4ch,
798 	.udt_pa = 0x406303ff,
799 	.udt_pass = B_TRUE,
800 	.udt_norm_addr = 0x1018c1ff,
801 	.udt_sock = 0,
802 	.udt_die = 0,
803 	.udt_comp = 0,
804 	.udt_dimm_no = 0,
805 	.udt_dimm_col = 0x3f,
806 	.udt_dimm_row = 0x80c,
807 	.udt_dimm_bank = 2,
808 	.udt_dimm_bank_group = 1,
809 	.udt_dimm_subchan = UINT8_MAX,
810 	.udt_dimm_rm = 0,
811 	.udt_dimm_cs = 0
812 }, {
813 	.udt_desc = "COD 4ch (16)",
814 	.udt_umc = &zen_umc_cod_4ch,
815 	.udt_pa = 0x406311ff,
816 	.udt_pass = B_TRUE,
817 	.udt_norm_addr = 0x1018c1ff,
818 	.udt_sock = 0,
819 	.udt_die = 0,
820 	.udt_comp = 3,
821 	.udt_dimm_no = 0,
822 	.udt_dimm_col = 0x3f,
823 	.udt_dimm_row = 0x80c,
824 	.udt_dimm_bank = 2,
825 	.udt_dimm_bank_group = 1,
826 	.udt_dimm_subchan = UINT8_MAX,
827 	.udt_dimm_rm = 0,
828 	.udt_dimm_cs = 0
829 }, {
830 	.udt_desc = "COD 4ch (17)",
831 	.udt_umc = &zen_umc_cod_4ch,
832 	.udt_pa = 0x406313ff,
833 	.udt_pass = B_TRUE,
834 	.udt_norm_addr = 0x1018c1ff,
835 	.udt_sock = 0,
836 	.udt_die = 0,
837 	.udt_comp = 2,
838 	.udt_dimm_no = 0,
839 	.udt_dimm_col = 0x3f,
840 	.udt_dimm_row = 0x80c,
841 	.udt_dimm_bank = 2,
842 	.udt_dimm_bank_group = 1,
843 	.udt_dimm_subchan = UINT8_MAX,
844 	.udt_dimm_rm = 0,
845 	.udt_dimm_cs = 0
846 }, {
847 	.udt_desc = "COD 4ch (18)",
848 	.udt_umc = &zen_umc_cod_4ch,
849 	.udt_pa = 0xc06313ff,
850 	.udt_pass = B_TRUE,
851 	.udt_norm_addr = 0x3018c1ff,
852 	.udt_sock = 0,
853 	.udt_die = 0,
854 	.udt_comp = 0,
855 	.udt_dimm_no = 0,
856 	.udt_dimm_col = 0x3f,
857 	.udt_dimm_row = 0x180c,
858 	.udt_dimm_bank = 2,
859 	.udt_dimm_bank_group = 1,
860 	.udt_dimm_subchan = UINT8_MAX,
861 	.udt_dimm_rm = 0,
862 	.udt_dimm_cs = 0
863 }, {
864 	.udt_desc = "COD 4ch (19)",
865 	.udt_umc = &zen_umc_cod_4ch,
866 	.udt_pa = 0xc06311ff,
867 	.udt_pass = B_TRUE,
868 	.udt_norm_addr = 0x3018c1ff,
869 	.udt_sock = 0,
870 	.udt_die = 0,
871 	.udt_comp = 1,
872 	.udt_dimm_no = 0,
873 	.udt_dimm_col = 0x3f,
874 	.udt_dimm_row = 0x180c,
875 	.udt_dimm_bank = 2,
876 	.udt_dimm_bank_group = 1,
877 	.udt_dimm_subchan = UINT8_MAX,
878 	.udt_dimm_rm = 0,
879 	.udt_dimm_cs = 0
880 }, {
881 	.udt_desc = "COD 4ch (20)",
882 	.udt_umc = &zen_umc_cod_4ch,
883 	.udt_pa = 0xc06301ff,
884 	.udt_pass = B_TRUE,
885 	.udt_norm_addr = 0x3018c1ff,
886 	.udt_sock = 0,
887 	.udt_die = 0,
888 	.udt_comp = 3,
889 	.udt_dimm_no = 0,
890 	.udt_dimm_col = 0x3f,
891 	.udt_dimm_row = 0x180c,
892 	.udt_dimm_bank = 2,
893 	.udt_dimm_bank_group = 1,
894 	.udt_dimm_subchan = UINT8_MAX,
895 	.udt_dimm_rm = 0,
896 	.udt_dimm_cs = 0
897 }, {
898 	.udt_desc = "COD 4ch (21)",
899 	.udt_umc = &zen_umc_cod_4ch,
900 	.udt_pa = 0xc06303ff,
901 	.udt_pass = B_TRUE,
902 	.udt_norm_addr = 0x3018c1ff,
903 	.udt_sock = 0,
904 	.udt_die = 0,
905 	.udt_comp = 2,
906 	.udt_dimm_no = 0,
907 	.udt_dimm_col = 0x3f,
908 	.udt_dimm_row = 0x180c,
909 	.udt_dimm_bank = 2,
910 	.udt_dimm_bank_group = 1,
911 	.udt_dimm_subchan = UINT8_MAX,
912 	.udt_dimm_rm = 0,
913 	.udt_dimm_cs = 0
914 }, {
915 	.udt_desc = "COD 6ch (0)",
916 	.udt_umc = &zen_umc_cod_6ch,
917 	.udt_pa = 0x1ff,
918 	.udt_pass = B_TRUE,
919 	.udt_norm_addr = 0x1ff,
920 	.udt_sock = 0,
921 	.udt_die = 0,
922 	.udt_comp = 0,
923 	.udt_dimm_no = 0,
924 	.udt_dimm_col = 0x3f,
925 	.udt_dimm_row = 0,
926 	.udt_dimm_bank = 0,
927 	.udt_dimm_bank_group = 0,
928 	.udt_dimm_subchan = UINT8_MAX,
929 	.udt_dimm_rm = 0,
930 	.udt_dimm_cs = 0
931 }, {
932 	.udt_desc = "COD 6ch (1)",
933 	.udt_umc = &zen_umc_cod_6ch,
934 	.udt_pa = 0x11ff,
935 	.udt_pass = B_TRUE,
936 	.udt_norm_addr = 0x1ff,
937 	.udt_sock = 0,
938 	.udt_die = 0,
939 	.udt_comp = 1,
940 	.udt_dimm_no = 0,
941 	.udt_dimm_col = 0x3f,
942 	.udt_dimm_row = 0,
943 	.udt_dimm_bank = 0,
944 	.udt_dimm_bank_group = 0,
945 	.udt_dimm_subchan = UINT8_MAX,
946 	.udt_dimm_rm = 0,
947 	.udt_dimm_cs = 0
948 }, {
949 	.udt_desc = "COD 6ch (2)",
950 	.udt_umc = &zen_umc_cod_6ch,
951 	.udt_pa = 0x21ff,
952 	.udt_pass = B_TRUE,
953 	.udt_norm_addr = 0x1ff,
954 	.udt_sock = 0,
955 	.udt_die = 0,
956 	.udt_comp = 2,
957 	.udt_dimm_no = 0,
958 	.udt_dimm_col = 0x3f,
959 	.udt_dimm_row = 0,
960 	.udt_dimm_bank = 0,
961 	.udt_dimm_bank_group = 0,
962 	.udt_dimm_subchan = UINT8_MAX,
963 	.udt_dimm_rm = 0,
964 	.udt_dimm_cs = 0
965 }, {
966 	.udt_desc = "COD 6ch (3)",
967 	.udt_umc = &zen_umc_cod_6ch,
968 	.udt_pa = 0x31ff,
969 	.udt_pass = B_TRUE,
970 	.udt_norm_addr = 0x1ff,
971 	.udt_sock = 0,
972 	.udt_die = 0,
973 	.udt_comp = 3,
974 	.udt_dimm_no = 0,
975 	.udt_dimm_col = 0x3f,
976 	.udt_dimm_row = 0,
977 	.udt_dimm_bank = 0,
978 	.udt_dimm_bank_group = 0,
979 	.udt_dimm_subchan = UINT8_MAX,
980 	.udt_dimm_rm = 0,
981 	.udt_dimm_cs = 0
982 }, {
983 	.udt_desc = "COD 6ch (4)",
984 	.udt_umc = &zen_umc_cod_6ch,
985 	.udt_pa = 0x41ff,
986 	.udt_pass = B_TRUE,
987 	.udt_norm_addr = 0x1ff,
988 	.udt_sock = 0,
989 	.udt_die = 0,
990 	.udt_comp = 4,
991 	.udt_dimm_no = 0,
992 	.udt_dimm_col = 0x3f,
993 	.udt_dimm_row = 0,
994 	.udt_dimm_bank = 0,
995 	.udt_dimm_bank_group = 0,
996 	.udt_dimm_subchan = UINT8_MAX,
997 	.udt_dimm_rm = 0,
998 	.udt_dimm_cs = 0
999 }, {
1000 	.udt_desc = "COD 6ch (5)",
1001 	.udt_umc = &zen_umc_cod_6ch,
1002 	.udt_pa = 0x51ff,
1003 	.udt_pass = B_TRUE,
1004 	.udt_norm_addr = 0x1ff,
1005 	.udt_sock = 0,
1006 	.udt_die = 0,
1007 	.udt_comp = 5,
1008 	.udt_dimm_no = 0,
1009 	.udt_dimm_col = 0x3f,
1010 	.udt_dimm_row = 0,
1011 	.udt_dimm_bank = 0,
1012 	.udt_dimm_bank_group = 0,
1013 	.udt_dimm_subchan = UINT8_MAX,
1014 	.udt_dimm_rm = 0,
1015 	.udt_dimm_cs = 0
1016 }, {
1017 	.udt_desc = "COD 6ch (6)",
1018 	.udt_umc = &zen_umc_cod_6ch,
1019 	.udt_pa = 0x61ff,
1020 	.udt_pass = B_TRUE,
1021 	.udt_norm_addr = 0x3000001ff,
1022 	.udt_sock = 0,
1023 	.udt_die = 0,
1024 	.udt_comp = 0,
1025 	.udt_dimm_no = 0,
1026 	.udt_dimm_col = 0x3f,
1027 	.udt_dimm_row = 0x18000,
1028 	.udt_dimm_bank = 0,
1029 	.udt_dimm_bank_group = 0,
1030 	.udt_dimm_subchan = UINT8_MAX,
1031 	.udt_dimm_rm = 0,
1032 	.udt_dimm_cs = 0
1033 }, {
1034 	.udt_desc = "COD 6ch (7)",
1035 	.udt_umc = &zen_umc_cod_6ch,
1036 	.udt_pa = 0x71ff,
1037 	.udt_pass = B_TRUE,
1038 	.udt_norm_addr = 0x3000001ff,
1039 	.udt_sock = 0,
1040 	.udt_die = 0,
1041 	.udt_comp = 1,
1042 	.udt_dimm_no = 0,
1043 	.udt_dimm_col = 0x3f,
1044 	.udt_dimm_row = 0x18000,
1045 	.udt_dimm_bank = 0,
1046 	.udt_dimm_bank_group = 0,
1047 	.udt_dimm_subchan = UINT8_MAX,
1048 	.udt_dimm_rm = 0,
1049 	.udt_dimm_cs = 0
1050 }, {
1051 	.udt_desc = "COD 6ch (8)",
1052 	.udt_umc = &zen_umc_cod_6ch,
1053 	.udt_pa = 0x81ff,
1054 	.udt_pass = B_TRUE,
1055 	.udt_norm_addr = 0x11ff,
1056 	.udt_sock = 0,
1057 	.udt_die = 0,
1058 	.udt_comp = 1,
1059 	.udt_dimm_no = 0,
1060 	.udt_dimm_col = 0x23f,
1061 	.udt_dimm_row = 0,
1062 	.udt_dimm_bank = 0,
1063 	.udt_dimm_bank_group = 0,
1064 	.udt_dimm_subchan = UINT8_MAX,
1065 	.udt_dimm_rm = 0,
1066 	.udt_dimm_cs = 0
1067 }, {
1068 	.udt_desc = "COD 6ch (9)",
1069 	.udt_umc = &zen_umc_cod_6ch,
1070 	.udt_pa = 0x91ff,
1071 	.udt_pass = B_TRUE,
1072 	.udt_norm_addr = 0x11ff,
1073 	.udt_sock = 0,
1074 	.udt_die = 0,
1075 	.udt_comp = 0,
1076 	.udt_dimm_no = 0,
1077 	.udt_dimm_col = 0x23f,
1078 	.udt_dimm_row = 0,
1079 	.udt_dimm_bank = 0,
1080 	.udt_dimm_bank_group = 0,
1081 	.udt_dimm_subchan = UINT8_MAX,
1082 	.udt_dimm_rm = 0,
1083 	.udt_dimm_cs = 0
1084 }, {
1085 	.udt_desc = "COD 6ch (10)",
1086 	.udt_umc = &zen_umc_cod_6ch,
1087 	.udt_pa = 0xa1ff,
1088 	.udt_pass = B_TRUE,
1089 	.udt_norm_addr = 0x11ff,
1090 	.udt_sock = 0,
1091 	.udt_die = 0,
1092 	.udt_comp = 3,
1093 	.udt_dimm_no = 0,
1094 	.udt_dimm_col = 0x23f,
1095 	.udt_dimm_row = 0,
1096 	.udt_dimm_bank = 0,
1097 	.udt_dimm_bank_group = 0,
1098 	.udt_dimm_subchan = UINT8_MAX,
1099 	.udt_dimm_rm = 0,
1100 	.udt_dimm_cs = 0
1101 }, {
1102 	.udt_desc = "COD 6ch (11)",
1103 	.udt_umc = &zen_umc_cod_6ch,
1104 	.udt_pa = 0xb1ff,
1105 	.udt_pass = B_TRUE,
1106 	.udt_norm_addr = 0x11ff,
1107 	.udt_sock = 0,
1108 	.udt_die = 0,
1109 	.udt_comp = 2,
1110 	.udt_dimm_no = 0,
1111 	.udt_dimm_col = 0x23f,
1112 	.udt_dimm_row = 0,
1113 	.udt_dimm_bank = 0,
1114 	.udt_dimm_bank_group = 0,
1115 	.udt_dimm_subchan = UINT8_MAX,
1116 	.udt_dimm_rm = 0,
1117 	.udt_dimm_cs = 0
1118 }, {
1119 	.udt_desc = "COD 6ch (12)",
1120 	.udt_umc = &zen_umc_cod_6ch,
1121 	.udt_pa = 0xc1ff,
1122 	.udt_pass = B_TRUE,
1123 	.udt_norm_addr = 0x11ff,
1124 	.udt_sock = 0,
1125 	.udt_die = 0,
1126 	.udt_comp = 5,
1127 	.udt_dimm_no = 0,
1128 	.udt_dimm_col = 0x23f,
1129 	.udt_dimm_row = 0,
1130 	.udt_dimm_bank = 0,
1131 	.udt_dimm_bank_group = 0,
1132 	.udt_dimm_subchan = UINT8_MAX,
1133 	.udt_dimm_rm = 0,
1134 	.udt_dimm_cs = 0
1135 }, {
1136 	.udt_desc = "COD 6ch (13)",
1137 	.udt_umc = &zen_umc_cod_6ch,
1138 	.udt_pa = 0xd1ff,
1139 	.udt_pass = B_TRUE,
1140 	.udt_norm_addr = 0x11ff,
1141 	.udt_sock = 0,
1142 	.udt_die = 0,
1143 	.udt_comp = 4,
1144 	.udt_dimm_no = 0,
1145 	.udt_dimm_col = 0x23f,
1146 	.udt_dimm_row = 0,
1147 	.udt_dimm_bank = 0,
1148 	.udt_dimm_bank_group = 0,
1149 	.udt_dimm_subchan = UINT8_MAX,
1150 	.udt_dimm_rm = 0,
1151 	.udt_dimm_cs = 0
1152 }, {
1153 	.udt_desc = "COD 6ch (14)",
1154 	.udt_umc = &zen_umc_cod_6ch,
1155 	.udt_pa = 0xe1ff,
1156 	.udt_pass = B_TRUE,
1157 	.udt_norm_addr = 0x3000011ff,
1158 	.udt_sock = 0,
1159 	.udt_die = 0,
1160 	.udt_comp = 3,
1161 	.udt_dimm_no = 0,
1162 	.udt_dimm_col = 0x23f,
1163 	.udt_dimm_row = 0x18000,
1164 	.udt_dimm_bank = 0,
1165 	.udt_dimm_bank_group = 0,
1166 	.udt_dimm_subchan = UINT8_MAX,
1167 	.udt_dimm_rm = 0,
1168 	.udt_dimm_cs = 0
1169 }, {
1170 	.udt_desc = "COD 6ch (15)",
1171 	.udt_umc = &zen_umc_cod_6ch,
1172 	.udt_pa = 0xf1ff,
1173 	.udt_pass = B_TRUE,
1174 	.udt_norm_addr = 0x3000011ff,
1175 	.udt_sock = 0,
1176 	.udt_die = 0,
1177 	.udt_comp = 2,
1178 	.udt_dimm_no = 0,
1179 	.udt_dimm_col = 0x23f,
1180 	.udt_dimm_row = 0x18000,
1181 	.udt_dimm_bank = 0,
1182 	.udt_dimm_bank_group = 0,
1183 	.udt_dimm_subchan = UINT8_MAX,
1184 	.udt_dimm_rm = 0,
1185 	.udt_dimm_cs = 0
1186 },
1187 /*
1188  * The above went through and showed that we can probably hash things correctly
1189  * and account for our mod-3 case. The ones below try to find the higher level
1190  * addresses that would result in the same normalized address that we have, but
1191  * on different dies to try and complete the set.
1192  */
1193 {
1194 	.udt_desc = "COD 6ch (16)",
1195 	.udt_umc = &zen_umc_cod_6ch,
1196 	.udt_pa = 0x8000061ff,
1197 	.udt_pass = B_TRUE,
1198 	.udt_norm_addr = 0x3000001ff,
1199 	.udt_sock = 0,
1200 	.udt_die = 0,
1201 	.udt_comp = 2,
1202 	.udt_dimm_no = 0,
1203 	.udt_dimm_col = 0x3f,
1204 	.udt_dimm_row = 0x18000,
1205 	.udt_dimm_bank = 0,
1206 	.udt_dimm_bank_group = 0,
1207 	.udt_dimm_subchan = UINT8_MAX,
1208 	.udt_dimm_rm = 0,
1209 	.udt_dimm_cs = 0
1210 }, {
1211 	.udt_desc = "COD 6ch (17)",
1212 	.udt_umc = &zen_umc_cod_6ch,
1213 	.udt_pa = 0x8000071ff,
1214 	.udt_pass = B_TRUE,
1215 	.udt_norm_addr = 0x3000001ff,
1216 	.udt_sock = 0,
1217 	.udt_die = 0,
1218 	.udt_comp = 3,
1219 	.udt_dimm_no = 0,
1220 	.udt_dimm_col = 0x3f,
1221 	.udt_dimm_row = 0x18000,
1222 	.udt_dimm_bank = 0,
1223 	.udt_dimm_bank_group = 0,
1224 	.udt_dimm_subchan = UINT8_MAX,
1225 	.udt_dimm_rm = 0,
1226 	.udt_dimm_cs = 0
1227 }, {
1228 	.udt_desc = "COD 6ch (18)",
1229 	.udt_umc = &zen_umc_cod_6ch,
1230 	.udt_pa = 0x10000061ff,
1231 	.udt_pass = B_TRUE,
1232 	.udt_norm_addr = 0x3000001ff,
1233 	.udt_sock = 0,
1234 	.udt_die = 0,
1235 	.udt_comp = 4,
1236 	.udt_dimm_no = 0,
1237 	.udt_dimm_col = 0x3f,
1238 	.udt_dimm_row = 0x18000,
1239 	.udt_dimm_bank = 0,
1240 	.udt_dimm_bank_group = 0,
1241 	.udt_dimm_subchan = UINT8_MAX,
1242 	.udt_dimm_rm = 0,
1243 	.udt_dimm_cs = 0
1244 }, {
1245 	.udt_desc = "COD 6ch (19)",
1246 	.udt_umc = &zen_umc_cod_6ch,
1247 	.udt_pa = 0x10000071ff,
1248 	.udt_pass = B_TRUE,
1249 	.udt_norm_addr = 0x3000001ff,
1250 	.udt_sock = 0,
1251 	.udt_die = 0,
1252 	.udt_comp = 5,
1253 	.udt_dimm_no = 0,
1254 	.udt_dimm_col = 0x3f,
1255 	.udt_dimm_row = 0x18000,
1256 	.udt_dimm_bank = 0,
1257 	.udt_dimm_bank_group = 0,
1258 	.udt_dimm_subchan = UINT8_MAX,
1259 	.udt_dimm_rm = 0,
1260 	.udt_dimm_cs = 0
1261 },
1262 /*
1263  * Now with that there, we go back and show that hashing actually impacts things
1264  * as we expect. Note, the bit 0 hash was already taken into account.
1265  */
1266 {
1267 	.udt_desc = "COD 6ch (20)",
1268 	.udt_umc = &zen_umc_cod_6ch,
1269 	.udt_pa = 0x8001ff,
1270 	.udt_pass = B_TRUE,
1271 	.udt_norm_addr = 0x1001ff,
1272 	.udt_sock = 0,
1273 	.udt_die = 0,
1274 	.udt_comp = 1,
1275 	.udt_dimm_no = 0,
1276 	.udt_dimm_col = 0x3f,
1277 	.udt_dimm_row = 0x8,
1278 	.udt_dimm_bank = 0,
1279 	.udt_dimm_bank_group = 0,
1280 	.udt_dimm_subchan = UINT8_MAX,
1281 	.udt_dimm_rm = 0,
1282 	.udt_dimm_cs = 0
1283 }, {
1284 	.udt_desc = "COD 6ch (21)",
1285 	.udt_umc = &zen_umc_cod_6ch,
1286 	.udt_pa = 0xa001ff,
1287 	.udt_pass = B_TRUE,
1288 	.udt_norm_addr = 0x1401ff,
1289 	.udt_sock = 0,
1290 	.udt_die = 0,
1291 	.udt_comp = 3,
1292 	.udt_dimm_no = 0,
1293 	.udt_dimm_col = 0x3f,
1294 	.udt_dimm_row = 0xa,
1295 	.udt_dimm_bank = 0,
1296 	.udt_dimm_bank_group = 0,
1297 	.udt_dimm_subchan = UINT8_MAX,
1298 	.udt_dimm_rm = 0,
1299 	.udt_dimm_cs = 0
1300 }, {
1301 	.udt_desc = "COD 6ch (22)",
1302 	.udt_umc = &zen_umc_cod_6ch,
1303 	.udt_pa = 0xe001ff,
1304 	.udt_pass = B_TRUE,
1305 	.udt_norm_addr = 0x3001c01ff,
1306 	.udt_sock = 0,
1307 	.udt_die = 0,
1308 	.udt_comp = 3,
1309 	.udt_dimm_no = 0,
1310 	.udt_dimm_col = 0x3f,
1311 	.udt_dimm_row = 0x1800e,
1312 	.udt_dimm_bank = 0,
1313 	.udt_dimm_bank_group = 0,
1314 	.udt_dimm_subchan = UINT8_MAX,
1315 	.udt_dimm_rm = 0,
1316 	.udt_dimm_cs = 0
1317 }, {
1318 	.udt_desc = "COD 6ch (23)",
1319 	.udt_umc = &zen_umc_cod_6ch,
1320 	.udt_pa = 0x180e001ff,
1321 	.udt_pass = B_TRUE,
1322 	.udt_norm_addr = 0x301c01ff,
1323 	.udt_sock = 0,
1324 	.udt_die = 0,
1325 	.udt_comp = 2,
1326 	.udt_dimm_no = 0,
1327 	.udt_dimm_col = 0x3f,
1328 	.udt_dimm_row = 0x180e,
1329 	.udt_dimm_bank = 0,
1330 	.udt_dimm_bank_group = 0,
1331 	.udt_dimm_subchan = UINT8_MAX,
1332 	.udt_dimm_rm = 0,
1333 	.udt_dimm_cs = 0
1334 }, {
1335 	.udt_desc = "COD 6ch (24)",
1336 	.udt_umc = &zen_umc_cod_6ch,
1337 	.udt_pa = 0x1c0e041ff,
1338 	.udt_pass = B_TRUE,
1339 	.udt_norm_addr = 0x381c01ff,
1340 	.udt_sock = 0,
1341 	.udt_die = 0,
1342 	.udt_comp = 4,
1343 	.udt_dimm_no = 0,
1344 	.udt_dimm_col = 0x3f,
1345 	.udt_dimm_row = 0x1c0e,
1346 	.udt_dimm_bank = 0,
1347 	.udt_dimm_bank_group = 0,
1348 	.udt_dimm_subchan = UINT8_MAX,
1349 	.udt_dimm_rm = 0,
1350 	.udt_dimm_cs = 0
1351 }, {
1352 	.udt_desc = NULL
1353 } };
1354