1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 /*
37 * 3Com 3c90x Etherlink XL PCI NIC driver
38 *
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
41 * the following:
42 *
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
72 *
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
76 */
77 /*
78 * The 3c90x series chips use a bus-master DMA interface for transferring
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
86 *
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
91 *
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
99 */
100
101 #ifdef HAVE_KERNEL_OPTION_HEADERS
102 #include "opt_device_polling.h"
103 #endif
104
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/kernel.h>
110 #include <sys/malloc.h>
111 #include <sys/mbuf.h>
112 #include <sys/module.h>
113 #include <sys/socket.h>
114 #include <sys/taskqueue.h>
115
116 #include <net/if.h>
117 #include <net/if_var.h>
118 #include <net/if_arp.h>
119 #include <net/ethernet.h>
120 #include <net/if_dl.h>
121 #include <net/if_media.h>
122 #include <net/if_types.h>
123
124 #include <net/bpf.h>
125
126 #include <machine/bus.h>
127 #include <machine/resource.h>
128 #include <sys/bus.h>
129 #include <sys/rman.h>
130
131 #include <dev/mii/mii.h>
132 #include <dev/mii/mii_bitbang.h>
133 #include <dev/mii/miivar.h>
134
135 #include <dev/pci/pcireg.h>
136 #include <dev/pci/pcivar.h>
137
138 MODULE_DEPEND(xl, pci, 1, 1, 1);
139 MODULE_DEPEND(xl, ether, 1, 1, 1);
140 MODULE_DEPEND(xl, miibus, 1, 1, 1);
141
142 /* "device miibus" required. See GENERIC if you get errors here. */
143 #include "miibus_if.h"
144
145 #include <dev/xl/if_xlreg.h>
146
147 /*
148 * TX Checksumming is disabled by default for two reasons:
149 * - TX Checksumming will occasionally produce corrupt packets
150 * - TX Checksumming seems to reduce performance
151 *
152 * Only 905B/C cards were reported to have this problem, it is possible
153 * that later chips _may_ be immune.
154 */
155 #define XL905B_TXCSUM_BROKEN 1
156
157 #ifdef XL905B_TXCSUM_BROKEN
158 #define XL905B_CSUM_FEATURES 0
159 #else
160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 #endif
162
163 /*
164 * Various supported device vendors/types and their names.
165 */
166 static const struct xl_type xl_devs[] = {
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
168 "3Com 3c900-TPO Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
170 "3Com 3c900-COMBO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
172 "3Com 3c905-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
174 "3Com 3c905-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
176 "3Com 3c900B-TPO Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
178 "3Com 3c900B-COMBO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
180 "3Com 3c900B-TPC Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
182 "3Com 3c900B-FL Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
184 "3Com 3c905B-TX Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
186 "3Com 3c905B-T4 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
188 "3Com 3c905B-FX/SC Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
190 "3Com 3c905B-COMBO Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
192 "3Com 3c905C-TX Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
198 "3Com 3c980 Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
200 "3Com 3c980C Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
202 "3Com 3cSOHO100-TX OfficeConnect" },
203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
204 "3Com 3c450-TX HomeConnect" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
206 "3Com 3c555 Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
208 "3Com 3c556 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
210 "3Com 3c556B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
212 "3Com 3c575TX Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
214 "3Com 3c575B Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
216 "3Com 3c575C Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
218 "3Com 3c656 Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
220 "3Com 3c656B Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
222 "3Com 3c656C Fast Etherlink XL" },
223 { 0, 0, NULL }
224 };
225
226 static int xl_probe(device_t);
227 static int xl_attach(device_t);
228 static int xl_detach(device_t);
229
230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
231 static void xl_tick(void *);
232 static void xl_stats_update(struct xl_softc *);
233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
234 static int xl_rxeof(struct xl_softc *);
235 static void xl_rxeof_task(void *, int);
236 static int xl_rx_resync(struct xl_softc *);
237 static void xl_txeof(struct xl_softc *);
238 static void xl_txeof_90xB(struct xl_softc *);
239 static void xl_txeoc(struct xl_softc *);
240 static void xl_intr(void *);
241 static void xl_start(if_t);
242 static void xl_start_locked(if_t);
243 static void xl_start_90xB_locked(if_t);
244 static int xl_ioctl(if_t, u_long, caddr_t);
245 static void xl_init(void *);
246 static void xl_init_locked(struct xl_softc *);
247 static void xl_stop(struct xl_softc *);
248 static int xl_watchdog(struct xl_softc *);
249 static int xl_shutdown(device_t);
250 static int xl_suspend(device_t);
251 static int xl_resume(device_t);
252 static void xl_setwol(struct xl_softc *);
253
254 #ifdef DEVICE_POLLING
255 static int xl_poll(if_t ifp, enum poll_cmd cmd, int count);
256 static int xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count);
257 #endif
258
259 static int xl_ifmedia_upd(if_t);
260 static void xl_ifmedia_sts(if_t, struct ifmediareq *);
261
262 static int xl_eeprom_wait(struct xl_softc *);
263 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
264
265 static void xl_rxfilter(struct xl_softc *);
266 static void xl_rxfilter_90x(struct xl_softc *);
267 static void xl_rxfilter_90xB(struct xl_softc *);
268 static void xl_setcfg(struct xl_softc *);
269 static void xl_setmode(struct xl_softc *, int);
270 static void xl_reset(struct xl_softc *);
271 static int xl_list_rx_init(struct xl_softc *);
272 static int xl_list_tx_init(struct xl_softc *);
273 static int xl_list_tx_init_90xB(struct xl_softc *);
274 static void xl_wait(struct xl_softc *);
275 static void xl_mediacheck(struct xl_softc *);
276 static void xl_choose_media(struct xl_softc *sc, int *media);
277 static void xl_choose_xcvr(struct xl_softc *, int);
278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
279 #ifdef notdef
280 static void xl_testpacket(struct xl_softc *);
281 #endif
282
283 static int xl_miibus_readreg(device_t, int, int);
284 static int xl_miibus_writereg(device_t, int, int, int);
285 static void xl_miibus_statchg(device_t);
286 static void xl_miibus_mediainit(device_t);
287
288 /*
289 * MII bit-bang glue
290 */
291 static uint32_t xl_mii_bitbang_read(device_t);
292 static void xl_mii_bitbang_write(device_t, uint32_t);
293
294 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
295 xl_mii_bitbang_read,
296 xl_mii_bitbang_write,
297 {
298 XL_MII_DATA, /* MII_BIT_MDO */
299 XL_MII_DATA, /* MII_BIT_MDI */
300 XL_MII_CLK, /* MII_BIT_MDC */
301 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
302 0, /* MII_BIT_DIR_PHY_HOST */
303 }
304 };
305
306 static device_method_t xl_methods[] = {
307 /* Device interface */
308 DEVMETHOD(device_probe, xl_probe),
309 DEVMETHOD(device_attach, xl_attach),
310 DEVMETHOD(device_detach, xl_detach),
311 DEVMETHOD(device_shutdown, xl_shutdown),
312 DEVMETHOD(device_suspend, xl_suspend),
313 DEVMETHOD(device_resume, xl_resume),
314
315 /* MII interface */
316 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
317 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
318 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
319 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
320
321 DEVMETHOD_END
322 };
323
324 static driver_t xl_driver = {
325 "xl",
326 xl_methods,
327 sizeof(struct xl_softc)
328 };
329
330 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, NULL, NULL, SI_ORDER_ANY);
331 DRIVER_MODULE(miibus, xl, miibus_driver, NULL, NULL);
332 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs,
333 nitems(xl_devs) - 1);
334
335 static void
xl_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)336 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
337 {
338 u_int32_t *paddr;
339
340 paddr = arg;
341 *paddr = segs->ds_addr;
342 }
343
344 /*
345 * Murphy's law says that it's possible the chip can wedge and
346 * the 'command in progress' bit may never clear. Hence, we wait
347 * only a finite amount of time to avoid getting caught in an
348 * infinite loop. Normally this delay routine would be a macro,
349 * but it isn't called during normal operation so we can afford
350 * to make it a function. Suppress warning when card gone.
351 */
352 static void
xl_wait(struct xl_softc * sc)353 xl_wait(struct xl_softc *sc)
354 {
355 int i;
356
357 for (i = 0; i < XL_TIMEOUT; i++) {
358 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
359 break;
360 }
361
362 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
363 device_printf(sc->xl_dev, "command never completed!\n");
364 }
365
366 /*
367 * MII access routines are provided for adapters with external
368 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
369 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
370 * Note: if you don't perform the MDIO operations just right,
371 * it's possible to end up with code that works correctly with
372 * some chips/CPUs/processor speeds/bus speeds/etc but not
373 * with others.
374 */
375
376 /*
377 * Read the MII serial port for the MII bit-bang module.
378 */
379 static uint32_t
xl_mii_bitbang_read(device_t dev)380 xl_mii_bitbang_read(device_t dev)
381 {
382 struct xl_softc *sc;
383 uint32_t val;
384
385 sc = device_get_softc(dev);
386
387 /* We're already in window 4. */
388 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
389 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
391
392 return (val);
393 }
394
395 /*
396 * Write the MII serial port for the MII bit-bang module.
397 */
398 static void
xl_mii_bitbang_write(device_t dev,uint32_t val)399 xl_mii_bitbang_write(device_t dev, uint32_t val)
400 {
401 struct xl_softc *sc;
402
403 sc = device_get_softc(dev);
404
405 /* We're already in window 4. */
406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
407 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
409 }
410
411 static int
xl_miibus_readreg(device_t dev,int phy,int reg)412 xl_miibus_readreg(device_t dev, int phy, int reg)
413 {
414 struct xl_softc *sc;
415
416 sc = device_get_softc(dev);
417
418 /* Select the window 4. */
419 XL_SEL_WIN(4);
420
421 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
422 }
423
424 static int
xl_miibus_writereg(device_t dev,int phy,int reg,int data)425 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
426 {
427 struct xl_softc *sc;
428
429 sc = device_get_softc(dev);
430
431 /* Select the window 4. */
432 XL_SEL_WIN(4);
433
434 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
435
436 return (0);
437 }
438
439 static void
xl_miibus_statchg(device_t dev)440 xl_miibus_statchg(device_t dev)
441 {
442 struct xl_softc *sc;
443 struct mii_data *mii;
444 uint8_t macctl;
445
446 sc = device_get_softc(dev);
447 mii = device_get_softc(sc->xl_miibus);
448
449 xl_setcfg(sc);
450
451 /* Set ASIC's duplex mode to match the PHY. */
452 XL_SEL_WIN(3);
453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
454 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
455 macctl |= XL_MACCTRL_DUPLEX;
456 if (sc->xl_type == XL_TYPE_905B) {
457 if ((IFM_OPTIONS(mii->mii_media_active) &
458 IFM_ETH_RXPAUSE) != 0)
459 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
460 else
461 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
462 }
463 } else {
464 macctl &= ~XL_MACCTRL_DUPLEX;
465 if (sc->xl_type == XL_TYPE_905B)
466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
467 }
468 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
469 }
470
471 /*
472 * Special support for the 3c905B-COMBO. This card has 10/100 support
473 * plus BNC and AUI ports. This means we will have both an miibus attached
474 * plus some non-MII media settings. In order to allow this, we have to
475 * add the extra media to the miibus's ifmedia struct, but we can't do
476 * that during xl_attach() because the miibus hasn't been attached yet.
477 * So instead, we wait until the miibus probe/attach is done, at which
478 * point we will get a callback telling is that it's safe to add our
479 * extra media.
480 */
481 static void
xl_miibus_mediainit(device_t dev)482 xl_miibus_mediainit(device_t dev)
483 {
484 struct xl_softc *sc;
485 struct mii_data *mii;
486 struct ifmedia *ifm;
487
488 sc = device_get_softc(dev);
489 mii = device_get_softc(sc->xl_miibus);
490 ifm = &mii->mii_media;
491
492 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
493 /*
494 * Check for a 10baseFL board in disguise.
495 */
496 if (sc->xl_type == XL_TYPE_905B &&
497 sc->xl_media == XL_MEDIAOPT_10FL) {
498 if (bootverbose)
499 device_printf(sc->xl_dev, "found 10baseFL\n");
500 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
501 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
502 NULL);
503 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
504 ifmedia_add(ifm,
505 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
506 } else {
507 if (bootverbose)
508 device_printf(sc->xl_dev, "found AUI\n");
509 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
510 }
511 }
512
513 if (sc->xl_media & XL_MEDIAOPT_BNC) {
514 if (bootverbose)
515 device_printf(sc->xl_dev, "found BNC\n");
516 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
517 }
518 }
519
520 /*
521 * The EEPROM is slow: give it time to come ready after issuing
522 * it a command.
523 */
524 static int
xl_eeprom_wait(struct xl_softc * sc)525 xl_eeprom_wait(struct xl_softc *sc)
526 {
527 int i;
528
529 for (i = 0; i < 100; i++) {
530 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
531 DELAY(162);
532 else
533 break;
534 }
535
536 if (i == 100) {
537 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
538 return (1);
539 }
540
541 return (0);
542 }
543
544 /*
545 * Read a sequence of words from the EEPROM. Note that ethernet address
546 * data is stored in the EEPROM in network byte order.
547 */
548 static int
xl_read_eeprom(struct xl_softc * sc,caddr_t dest,int off,int cnt,int swap)549 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
550 {
551 int err = 0, i;
552 u_int16_t word = 0, *ptr;
553
554 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
555 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
556 /*
557 * XXX: WARNING! DANGER!
558 * It's easy to accidentally overwrite the rom content!
559 * Note: the 3c575 uses 8bit EEPROM offsets.
560 */
561 XL_SEL_WIN(0);
562
563 if (xl_eeprom_wait(sc))
564 return (1);
565
566 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
567 off += 0x30;
568
569 for (i = 0; i < cnt; i++) {
570 if (sc->xl_flags & XL_FLAG_8BITROM)
571 CSR_WRITE_2(sc, XL_W0_EE_CMD,
572 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
573 else
574 CSR_WRITE_2(sc, XL_W0_EE_CMD,
575 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
576 err = xl_eeprom_wait(sc);
577 if (err)
578 break;
579 word = CSR_READ_2(sc, XL_W0_EE_DATA);
580 ptr = (u_int16_t *)(dest + (i * 2));
581 if (swap)
582 *ptr = ntohs(word);
583 else
584 *ptr = word;
585 }
586
587 return (err ? 1 : 0);
588 }
589
590 static void
xl_rxfilter(struct xl_softc * sc)591 xl_rxfilter(struct xl_softc *sc)
592 {
593
594 if (sc->xl_type == XL_TYPE_905B)
595 xl_rxfilter_90xB(sc);
596 else
597 xl_rxfilter_90x(sc);
598 }
599
600 /*
601 * NICs older than the 3c905B have only one multicast option, which
602 * is to enable reception of all multicast frames.
603 */
604 static u_int
xl_check_maddr_90x(void * arg,struct sockaddr_dl * sdl,u_int cnt)605 xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt)
606 {
607 uint8_t *rxfilt = arg;
608
609 *rxfilt |= XL_RXFILTER_ALLMULTI;
610
611 return (1);
612 }
613
614 static void
xl_rxfilter_90x(struct xl_softc * sc)615 xl_rxfilter_90x(struct xl_softc *sc)
616 {
617 if_t ifp;
618 u_int8_t rxfilt;
619
620 XL_LOCK_ASSERT(sc);
621
622 ifp = sc->xl_ifp;
623
624 XL_SEL_WIN(5);
625 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
626 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
627 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
628
629 /* Set the individual bit to receive frames for this host only. */
630 rxfilt |= XL_RXFILTER_INDIVIDUAL;
631 /* Set capture broadcast bit to capture broadcast frames. */
632 if (if_getflags(ifp) & IFF_BROADCAST)
633 rxfilt |= XL_RXFILTER_BROADCAST;
634
635 /* If we want promiscuous mode, set the allframes bit. */
636 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) {
637 if (if_getflags(ifp) & IFF_PROMISC)
638 rxfilt |= XL_RXFILTER_ALLFRAMES;
639 if (if_getflags(ifp) & IFF_ALLMULTI)
640 rxfilt |= XL_RXFILTER_ALLMULTI;
641 } else
642 if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt);
643
644 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
645 XL_SEL_WIN(7);
646 }
647
648 /*
649 * 3c905B adapters have a hash filter that we can program.
650 * Note: the 3c905B currently only supports a 64-bit
651 * hash table, which means we really only need 6 bits,
652 * but the manual indicates that future chip revisions
653 * will have a 256-bit hash table, hence the routine
654 * is set up to calculate 8 bits of position info in
655 * case we need it some day.
656 * Note II, The Sequel: _CURRENT_ versions of the
657 * 3c905B have a 256 bit hash table. This means we have
658 * to use all 8 bits regardless. On older cards, the
659 * upper 2 bits will be ignored. Grrrr....
660 */
661 static u_int
xl_check_maddr_90xB(void * arg,struct sockaddr_dl * sdl,u_int count)662 xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count)
663 {
664 struct xl_softc *sc = arg;
665 uint16_t h;
666
667 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
668 CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
669
670 return (1);
671 }
672
673 static void
xl_rxfilter_90xB(struct xl_softc * sc)674 xl_rxfilter_90xB(struct xl_softc *sc)
675 {
676 if_t ifp;
677 int i;
678 u_int8_t rxfilt;
679
680 XL_LOCK_ASSERT(sc);
681
682 ifp = sc->xl_ifp;
683
684 XL_SEL_WIN(5);
685 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
686 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
687 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
688 XL_RXFILTER_MULTIHASH);
689
690 /* Set the individual bit to receive frames for this host only. */
691 rxfilt |= XL_RXFILTER_INDIVIDUAL;
692 /* Set capture broadcast bit to capture broadcast frames. */
693 if (if_getflags(ifp) & IFF_BROADCAST)
694 rxfilt |= XL_RXFILTER_BROADCAST;
695
696 /* If we want promiscuous mode, set the allframes bit. */
697 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) {
698 if (if_getflags(ifp) & IFF_PROMISC)
699 rxfilt |= XL_RXFILTER_ALLFRAMES;
700 if (if_getflags(ifp) & IFF_ALLMULTI)
701 rxfilt |= XL_RXFILTER_ALLMULTI;
702 } else {
703 /* First, zot all the existing hash bits. */
704 for (i = 0; i < XL_HASHFILT_SIZE; i++)
705 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
706
707 /* Now program new ones. */
708 if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0)
709 rxfilt |= XL_RXFILTER_MULTIHASH;
710 }
711
712 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
713 XL_SEL_WIN(7);
714 }
715
716 static void
xl_setcfg(struct xl_softc * sc)717 xl_setcfg(struct xl_softc *sc)
718 {
719 u_int32_t icfg;
720
721 /*XL_LOCK_ASSERT(sc);*/
722
723 XL_SEL_WIN(3);
724 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
725 icfg &= ~XL_ICFG_CONNECTOR_MASK;
726 if (sc->xl_media & XL_MEDIAOPT_MII ||
727 sc->xl_media & XL_MEDIAOPT_BT4)
728 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
729 if (sc->xl_media & XL_MEDIAOPT_BTX)
730 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
731
732 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
733 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
734 }
735
736 static void
xl_setmode(struct xl_softc * sc,int media)737 xl_setmode(struct xl_softc *sc, int media)
738 {
739 u_int32_t icfg;
740 u_int16_t mediastat;
741 char *pmsg = "", *dmsg = "";
742
743 XL_LOCK_ASSERT(sc);
744
745 XL_SEL_WIN(4);
746 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
747 XL_SEL_WIN(3);
748 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
749
750 if (sc->xl_media & XL_MEDIAOPT_BT) {
751 if (IFM_SUBTYPE(media) == IFM_10_T) {
752 pmsg = "10baseT transceiver";
753 sc->xl_xcvr = XL_XCVR_10BT;
754 icfg &= ~XL_ICFG_CONNECTOR_MASK;
755 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
756 mediastat |= XL_MEDIASTAT_LINKBEAT |
757 XL_MEDIASTAT_JABGUARD;
758 mediastat &= ~XL_MEDIASTAT_SQEENB;
759 }
760 }
761
762 if (sc->xl_media & XL_MEDIAOPT_BFX) {
763 if (IFM_SUBTYPE(media) == IFM_100_FX) {
764 pmsg = "100baseFX port";
765 sc->xl_xcvr = XL_XCVR_100BFX;
766 icfg &= ~XL_ICFG_CONNECTOR_MASK;
767 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
768 mediastat |= XL_MEDIASTAT_LINKBEAT;
769 mediastat &= ~XL_MEDIASTAT_SQEENB;
770 }
771 }
772
773 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
774 if (IFM_SUBTYPE(media) == IFM_10_5) {
775 pmsg = "AUI port";
776 sc->xl_xcvr = XL_XCVR_AUI;
777 icfg &= ~XL_ICFG_CONNECTOR_MASK;
778 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
779 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
780 XL_MEDIASTAT_JABGUARD);
781 mediastat |= ~XL_MEDIASTAT_SQEENB;
782 }
783 if (IFM_SUBTYPE(media) == IFM_10_FL) {
784 pmsg = "10baseFL transceiver";
785 sc->xl_xcvr = XL_XCVR_AUI;
786 icfg &= ~XL_ICFG_CONNECTOR_MASK;
787 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
788 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
789 XL_MEDIASTAT_JABGUARD);
790 mediastat |= ~XL_MEDIASTAT_SQEENB;
791 }
792 }
793
794 if (sc->xl_media & XL_MEDIAOPT_BNC) {
795 if (IFM_SUBTYPE(media) == IFM_10_2) {
796 pmsg = "AUI port";
797 sc->xl_xcvr = XL_XCVR_COAX;
798 icfg &= ~XL_ICFG_CONNECTOR_MASK;
799 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
800 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
801 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
802 }
803 }
804
805 if ((media & IFM_GMASK) == IFM_FDX ||
806 IFM_SUBTYPE(media) == IFM_100_FX) {
807 dmsg = "full";
808 XL_SEL_WIN(3);
809 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
810 } else {
811 dmsg = "half";
812 XL_SEL_WIN(3);
813 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
814 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
815 }
816
817 if (IFM_SUBTYPE(media) == IFM_10_2)
818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
819 else
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
821
822 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
823 XL_SEL_WIN(4);
824 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
825
826 DELAY(800);
827 XL_SEL_WIN(7);
828
829 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
830 }
831
832 static void
xl_reset(struct xl_softc * sc)833 xl_reset(struct xl_softc *sc)
834 {
835 int i;
836
837 XL_LOCK_ASSERT(sc);
838
839 XL_SEL_WIN(0);
840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
841 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
842 XL_RESETOPT_DISADVFD:0));
843
844 /*
845 * If we're using memory mapped register mode, pause briefly
846 * after issuing the reset command before trying to access any
847 * other registers. With my 3c575C CardBus card, failing to do
848 * this results in the system locking up while trying to poll
849 * the command busy bit in the status register.
850 */
851 if (sc->xl_flags & XL_FLAG_USE_MMIO)
852 DELAY(100000);
853
854 for (i = 0; i < XL_TIMEOUT; i++) {
855 DELAY(10);
856 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
857 break;
858 }
859
860 if (i == XL_TIMEOUT)
861 device_printf(sc->xl_dev, "reset didn't complete\n");
862
863 /* Reset TX and RX. */
864 /* Note: the RX reset takes an absurd amount of time
865 * on newer versions of the Tornado chips such as those
866 * on the 3c905CX and newer 3c908C cards. We wait an
867 * extra amount of time so that xl_wait() doesn't complain
868 * and annoy the users.
869 */
870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
871 DELAY(100000);
872 xl_wait(sc);
873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
874 xl_wait(sc);
875
876 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
877 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
878 XL_SEL_WIN(2);
879 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
880 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
881 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
882 XL_RESETOPT_INVERT_LED : 0) |
883 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
884 XL_RESETOPT_INVERT_MII : 0));
885 }
886
887 /* Wait a little while for the chip to get its brains in order. */
888 DELAY(100000);
889 }
890
891 /*
892 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
893 * IDs against our list and return a device name if we find a match.
894 */
895 static int
xl_probe(device_t dev)896 xl_probe(device_t dev)
897 {
898 const struct xl_type *t;
899
900 t = xl_devs;
901
902 while (t->xl_name != NULL) {
903 if ((pci_get_vendor(dev) == t->xl_vid) &&
904 (pci_get_device(dev) == t->xl_did)) {
905 device_set_desc(dev, t->xl_name);
906 return (BUS_PROBE_DEFAULT);
907 }
908 t++;
909 }
910
911 return (ENXIO);
912 }
913
914 /*
915 * This routine is a kludge to work around possible hardware faults
916 * or manufacturing defects that can cause the media options register
917 * (or reset options register, as it's called for the first generation
918 * 3c90x adapters) to return an incorrect result. I have encountered
919 * one Dell Latitude laptop docking station with an integrated 3c905-TX
920 * which doesn't have any of the 'mediaopt' bits set. This screws up
921 * the attach routine pretty badly because it doesn't know what media
922 * to look for. If we find ourselves in this predicament, this routine
923 * will try to guess the media options values and warn the user of a
924 * possible manufacturing defect with his adapter/system/whatever.
925 */
926 static void
xl_mediacheck(struct xl_softc * sc)927 xl_mediacheck(struct xl_softc *sc)
928 {
929
930 /*
931 * If some of the media options bits are set, assume they are
932 * correct. If not, try to figure it out down below.
933 * XXX I should check for 10baseFL, but I don't have an adapter
934 * to test with.
935 */
936 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
937 /*
938 * Check the XCVR value. If it's not in the normal range
939 * of values, we need to fake it up here.
940 */
941 if (sc->xl_xcvr <= XL_XCVR_AUTO)
942 return;
943 else {
944 device_printf(sc->xl_dev,
945 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
946 device_printf(sc->xl_dev,
947 "choosing new default based on card type\n");
948 }
949 } else {
950 if (sc->xl_type == XL_TYPE_905B &&
951 sc->xl_media & XL_MEDIAOPT_10FL)
952 return;
953 device_printf(sc->xl_dev,
954 "WARNING: no media options bits set in the media options register!!\n");
955 device_printf(sc->xl_dev,
956 "this could be a manufacturing defect in your adapter or system\n");
957 device_printf(sc->xl_dev,
958 "attempting to guess media type; you should probably consult your vendor\n");
959 }
960
961 xl_choose_xcvr(sc, 1);
962 }
963
964 static void
xl_choose_xcvr(struct xl_softc * sc,int verbose)965 xl_choose_xcvr(struct xl_softc *sc, int verbose)
966 {
967 u_int16_t devid;
968
969 /*
970 * Read the device ID from the EEPROM.
971 * This is what's loaded into the PCI device ID register, so it has
972 * to be correct otherwise we wouldn't have gotten this far.
973 */
974 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
975
976 switch (devid) {
977 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
978 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
979 sc->xl_media = XL_MEDIAOPT_BT;
980 sc->xl_xcvr = XL_XCVR_10BT;
981 if (verbose)
982 device_printf(sc->xl_dev,
983 "guessing 10BaseT transceiver\n");
984 break;
985 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
986 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
987 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
988 sc->xl_xcvr = XL_XCVR_10BT;
989 if (verbose)
990 device_printf(sc->xl_dev,
991 "guessing COMBO (AUI/BNC/TP)\n");
992 break;
993 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
994 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
995 sc->xl_xcvr = XL_XCVR_10BT;
996 if (verbose)
997 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
998 break;
999 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1000 sc->xl_media = XL_MEDIAOPT_10FL;
1001 sc->xl_xcvr = XL_XCVR_AUI;
1002 if (verbose)
1003 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1004 break;
1005 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1006 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1007 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1008 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1009 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1010 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1011 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1012 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1013 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1014 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1015 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1016 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1017 sc->xl_media = XL_MEDIAOPT_MII;
1018 sc->xl_xcvr = XL_XCVR_MII;
1019 if (verbose)
1020 device_printf(sc->xl_dev, "guessing MII\n");
1021 break;
1022 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1023 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1024 sc->xl_media = XL_MEDIAOPT_BT4;
1025 sc->xl_xcvr = XL_XCVR_MII;
1026 if (verbose)
1027 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1028 break;
1029 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1030 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1031 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1032 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1033 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1034 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1035 sc->xl_media = XL_MEDIAOPT_BTX;
1036 sc->xl_xcvr = XL_XCVR_AUTO;
1037 if (verbose)
1038 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1039 break;
1040 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1041 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1042 sc->xl_xcvr = XL_XCVR_AUTO;
1043 if (verbose)
1044 device_printf(sc->xl_dev,
1045 "guessing 10/100 plus BNC/AUI\n");
1046 break;
1047 default:
1048 device_printf(sc->xl_dev,
1049 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1050 sc->xl_media = XL_MEDIAOPT_BT;
1051 break;
1052 }
1053 }
1054
1055 /*
1056 * Attach the interface. Allocate softc structures, do ifmedia
1057 * setup and ethernet/BPF attach.
1058 */
1059 static int
xl_attach(device_t dev)1060 xl_attach(device_t dev)
1061 {
1062 u_char eaddr[ETHER_ADDR_LEN];
1063 u_int16_t sinfo2, xcvr[2];
1064 struct xl_softc *sc;
1065 if_t ifp;
1066 int media, pmcap;
1067 int error = 0, phy, rid, res;
1068 uint16_t did;
1069
1070 sc = device_get_softc(dev);
1071 sc->xl_dev = dev;
1072
1073 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1074 MTX_DEF);
1075 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1076
1077 did = pci_get_device(dev);
1078
1079 sc->xl_flags = 0;
1080 if (did == TC_DEVICEID_HURRICANE_555)
1081 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1082 if (did == TC_DEVICEID_HURRICANE_556 ||
1083 did == TC_DEVICEID_HURRICANE_556B)
1084 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1085 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1086 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1087 if (did == TC_DEVICEID_HURRICANE_555 ||
1088 did == TC_DEVICEID_HURRICANE_556)
1089 sc->xl_flags |= XL_FLAG_8BITROM;
1090 if (did == TC_DEVICEID_HURRICANE_556B)
1091 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1092
1093 if (did == TC_DEVICEID_HURRICANE_575B ||
1094 did == TC_DEVICEID_HURRICANE_575C ||
1095 did == TC_DEVICEID_HURRICANE_656B ||
1096 did == TC_DEVICEID_TORNADO_656C)
1097 sc->xl_flags |= XL_FLAG_FUNCREG;
1098 if (did == TC_DEVICEID_HURRICANE_575A ||
1099 did == TC_DEVICEID_HURRICANE_575B ||
1100 did == TC_DEVICEID_HURRICANE_575C ||
1101 did == TC_DEVICEID_HURRICANE_656B ||
1102 did == TC_DEVICEID_TORNADO_656C)
1103 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1104 XL_FLAG_8BITROM;
1105 if (did == TC_DEVICEID_HURRICANE_656)
1106 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1107 if (did == TC_DEVICEID_HURRICANE_575B)
1108 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1109 if (did == TC_DEVICEID_HURRICANE_575C)
1110 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1111 if (did == TC_DEVICEID_TORNADO_656C)
1112 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1113 if (did == TC_DEVICEID_HURRICANE_656 ||
1114 did == TC_DEVICEID_HURRICANE_656B)
1115 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1116 XL_FLAG_INVERT_LED_PWR;
1117 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1118 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1119 sc->xl_flags |= XL_FLAG_PHYOK;
1120
1121 switch (did) {
1122 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1123 case TC_DEVICEID_HURRICANE_575A:
1124 case TC_DEVICEID_HURRICANE_575B:
1125 case TC_DEVICEID_HURRICANE_575C:
1126 sc->xl_flags |= XL_FLAG_NO_MMIO;
1127 break;
1128 default:
1129 break;
1130 }
1131
1132 /*
1133 * Map control/status registers.
1134 */
1135 pci_enable_busmaster(dev);
1136
1137 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1138 rid = XL_PCI_LOMEM;
1139 res = SYS_RES_MEMORY;
1140
1141 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1142 }
1143
1144 if (sc->xl_res != NULL) {
1145 sc->xl_flags |= XL_FLAG_USE_MMIO;
1146 if (bootverbose)
1147 device_printf(dev, "using memory mapped I/O\n");
1148 } else {
1149 rid = XL_PCI_LOIO;
1150 res = SYS_RES_IOPORT;
1151 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1152 if (sc->xl_res == NULL) {
1153 device_printf(dev, "couldn't map ports/memory\n");
1154 error = ENXIO;
1155 goto fail;
1156 }
1157 if (bootverbose)
1158 device_printf(dev, "using port I/O\n");
1159 }
1160
1161 sc->xl_btag = rman_get_bustag(sc->xl_res);
1162 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1163
1164 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1165 rid = XL_PCI_FUNCMEM;
1166 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1167 RF_ACTIVE);
1168
1169 if (sc->xl_fres == NULL) {
1170 device_printf(dev, "couldn't map funcreg memory\n");
1171 error = ENXIO;
1172 goto fail;
1173 }
1174
1175 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1176 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1177 }
1178
1179 /* Allocate interrupt */
1180 rid = 0;
1181 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1182 RF_SHAREABLE | RF_ACTIVE);
1183 if (sc->xl_irq == NULL) {
1184 device_printf(dev, "couldn't map interrupt\n");
1185 error = ENXIO;
1186 goto fail;
1187 }
1188
1189 /* Initialize interface name. */
1190 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1191 if_setsoftc(ifp, sc);
1192 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1193
1194 /* Reset the adapter. */
1195 XL_LOCK(sc);
1196 xl_reset(sc);
1197 XL_UNLOCK(sc);
1198
1199 /*
1200 * Get station address from the EEPROM.
1201 */
1202 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1203 device_printf(dev, "failed to read station address\n");
1204 error = ENXIO;
1205 goto fail;
1206 }
1207
1208 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1209 NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1210
1211 /*
1212 * Now allocate a tag for the DMA descriptor lists and a chunk
1213 * of DMA-able memory based on the tag. Also obtain the DMA
1214 * addresses of the RX and TX ring, which we'll need later.
1215 * All of our lists are allocated as a contiguous block
1216 * of memory.
1217 */
1218 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1219 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1220 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1221 &sc->xl_ldata.xl_rx_tag);
1222 if (error) {
1223 device_printf(dev, "failed to allocate rx dma tag\n");
1224 goto fail;
1225 }
1226
1227 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1228 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1229 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1230 if (error) {
1231 device_printf(dev, "no memory for rx list buffers!\n");
1232 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1233 sc->xl_ldata.xl_rx_tag = NULL;
1234 goto fail;
1235 }
1236
1237 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1238 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1239 XL_RX_LIST_SZ, xl_dma_map_addr,
1240 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1241 if (error) {
1242 device_printf(dev, "cannot get dma address of the rx ring!\n");
1243 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1244 sc->xl_ldata.xl_rx_dmamap);
1245 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1246 sc->xl_ldata.xl_rx_tag = NULL;
1247 goto fail;
1248 }
1249
1250 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1251 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1252 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1253 &sc->xl_ldata.xl_tx_tag);
1254 if (error) {
1255 device_printf(dev, "failed to allocate tx dma tag\n");
1256 goto fail;
1257 }
1258
1259 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1260 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1261 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1262 if (error) {
1263 device_printf(dev, "no memory for list buffers!\n");
1264 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1265 sc->xl_ldata.xl_tx_tag = NULL;
1266 goto fail;
1267 }
1268
1269 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1270 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1271 XL_TX_LIST_SZ, xl_dma_map_addr,
1272 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1273 if (error) {
1274 device_printf(dev, "cannot get dma address of the tx ring!\n");
1275 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1276 sc->xl_ldata.xl_tx_dmamap);
1277 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1278 sc->xl_ldata.xl_tx_tag = NULL;
1279 goto fail;
1280 }
1281
1282 /*
1283 * Allocate a DMA tag for the mapping of mbufs.
1284 */
1285 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1286 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1287 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1288 NULL, &sc->xl_mtag);
1289 if (error) {
1290 device_printf(dev, "failed to allocate mbuf dma tag\n");
1291 goto fail;
1292 }
1293
1294 /* We need a spare DMA map for the RX ring. */
1295 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1296 if (error)
1297 goto fail;
1298
1299 /*
1300 * Figure out the card type. 3c905B adapters have the
1301 * 'supportsNoTxLength' bit set in the capabilities
1302 * word in the EEPROM.
1303 * Note: my 3c575C CardBus card lies. It returns a value
1304 * of 0x1578 for its capabilities word, which is somewhat
1305 * nonsensical. Another way to distinguish a 3c90x chip
1306 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1307 * bit. This will only be set for 3c90x boomerage chips.
1308 */
1309 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1310 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1311 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1312 sc->xl_type = XL_TYPE_905B;
1313 else
1314 sc->xl_type = XL_TYPE_90X;
1315
1316 /* Check availability of WOL. */
1317 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1318 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1319 sc->xl_pmcap = pmcap;
1320 sc->xl_flags |= XL_FLAG_WOL;
1321 sinfo2 = 0;
1322 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1323 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1324 device_printf(dev,
1325 "No auxiliary remote wakeup connector!\n");
1326 }
1327
1328 /* Set the TX start threshold for best performance. */
1329 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1330
1331 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1332 if_setioctlfn(ifp, xl_ioctl);
1333 if_setcapabilities(ifp, IFCAP_VLAN_MTU);
1334 if (sc->xl_type == XL_TYPE_905B) {
1335 if_sethwassist(ifp, XL905B_CSUM_FEATURES);
1336 #ifdef XL905B_TXCSUM_BROKEN
1337 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
1338 #else
1339 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0);
1340 #endif
1341 }
1342 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1343 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
1344 if_setcapenable(ifp, if_getcapabilities(ifp));
1345 #ifdef DEVICE_POLLING
1346 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
1347 #endif
1348 if_setstartfn(ifp, xl_start);
1349 if_setinitfn(ifp, xl_init);
1350 if_setsendqlen(ifp, XL_TX_LIST_CNT - 1);
1351 if_setsendqready(ifp);
1352
1353 /*
1354 * Now we have to see what sort of media we have.
1355 * This includes probing for an MII interace and a
1356 * possible PHY.
1357 */
1358 XL_SEL_WIN(3);
1359 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1360 if (bootverbose)
1361 device_printf(dev, "media options word: %x\n", sc->xl_media);
1362
1363 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1364 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1365 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1366 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1367
1368 xl_mediacheck(sc);
1369
1370 if (sc->xl_media & XL_MEDIAOPT_MII ||
1371 sc->xl_media & XL_MEDIAOPT_BTX ||
1372 sc->xl_media & XL_MEDIAOPT_BT4) {
1373 if (bootverbose)
1374 device_printf(dev, "found MII/AUTO\n");
1375 xl_setcfg(sc);
1376 /*
1377 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1378 * This is to guard against problems with certain 3Com ASIC
1379 * revisions that incorrectly map the internal transceiver
1380 * control registers at all MII addresses.
1381 */
1382 phy = MII_PHY_ANY;
1383 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1384 phy = 24;
1385 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1386 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1387 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1388 if (error != 0) {
1389 device_printf(dev, "attaching PHYs failed\n");
1390 goto fail;
1391 }
1392 goto done;
1393 }
1394
1395 /*
1396 * Sanity check. If the user has selected "auto" and this isn't
1397 * a 10/100 card of some kind, we need to force the transceiver
1398 * type to something sane.
1399 */
1400 if (sc->xl_xcvr == XL_XCVR_AUTO)
1401 xl_choose_xcvr(sc, bootverbose);
1402
1403 /*
1404 * Do ifmedia setup.
1405 */
1406 if (sc->xl_media & XL_MEDIAOPT_BT) {
1407 if (bootverbose)
1408 device_printf(dev, "found 10baseT\n");
1409 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1410 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1411 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1412 ifmedia_add(&sc->ifmedia,
1413 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1414 }
1415
1416 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1417 /*
1418 * Check for a 10baseFL board in disguise.
1419 */
1420 if (sc->xl_type == XL_TYPE_905B &&
1421 sc->xl_media == XL_MEDIAOPT_10FL) {
1422 if (bootverbose)
1423 device_printf(dev, "found 10baseFL\n");
1424 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1425 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1426 0, NULL);
1427 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1428 ifmedia_add(&sc->ifmedia,
1429 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1430 } else {
1431 if (bootverbose)
1432 device_printf(dev, "found AUI\n");
1433 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1434 }
1435 }
1436
1437 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1438 if (bootverbose)
1439 device_printf(dev, "found BNC\n");
1440 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1441 }
1442
1443 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1444 if (bootverbose)
1445 device_printf(dev, "found 100baseFX\n");
1446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1447 }
1448
1449 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1450 xl_choose_media(sc, &media);
1451
1452 if (sc->xl_miibus == NULL)
1453 ifmedia_set(&sc->ifmedia, media);
1454
1455 done:
1456 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1457 XL_SEL_WIN(0);
1458 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1459 }
1460
1461 /*
1462 * Call MI attach routine.
1463 */
1464 ether_ifattach(ifp, eaddr);
1465
1466 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1467 NULL, xl_intr, sc, &sc->xl_intrhand);
1468 if (error) {
1469 device_printf(dev, "couldn't set up irq\n");
1470 ether_ifdetach(ifp);
1471 goto fail;
1472 }
1473
1474 fail:
1475 if (error)
1476 xl_detach(dev);
1477
1478 return (error);
1479 }
1480
1481 /*
1482 * Choose a default media.
1483 * XXX This is a leaf function only called by xl_attach() and
1484 * acquires/releases the non-recursible driver mutex to
1485 * satisfy lock assertions.
1486 */
1487 static void
xl_choose_media(struct xl_softc * sc,int * media)1488 xl_choose_media(struct xl_softc *sc, int *media)
1489 {
1490
1491 XL_LOCK(sc);
1492
1493 switch (sc->xl_xcvr) {
1494 case XL_XCVR_10BT:
1495 *media = IFM_ETHER|IFM_10_T;
1496 xl_setmode(sc, *media);
1497 break;
1498 case XL_XCVR_AUI:
1499 if (sc->xl_type == XL_TYPE_905B &&
1500 sc->xl_media == XL_MEDIAOPT_10FL) {
1501 *media = IFM_ETHER|IFM_10_FL;
1502 xl_setmode(sc, *media);
1503 } else {
1504 *media = IFM_ETHER|IFM_10_5;
1505 xl_setmode(sc, *media);
1506 }
1507 break;
1508 case XL_XCVR_COAX:
1509 *media = IFM_ETHER|IFM_10_2;
1510 xl_setmode(sc, *media);
1511 break;
1512 case XL_XCVR_AUTO:
1513 case XL_XCVR_100BTX:
1514 case XL_XCVR_MII:
1515 /* Chosen by miibus */
1516 break;
1517 case XL_XCVR_100BFX:
1518 *media = IFM_ETHER|IFM_100_FX;
1519 break;
1520 default:
1521 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1522 sc->xl_xcvr);
1523 /*
1524 * This will probably be wrong, but it prevents
1525 * the ifmedia code from panicking.
1526 */
1527 *media = IFM_ETHER|IFM_10_T;
1528 break;
1529 }
1530
1531 XL_UNLOCK(sc);
1532 }
1533
1534 /*
1535 * Shutdown hardware and free up resources. This can be called any
1536 * time after the mutex has been initialized. It is called in both
1537 * the error case in attach and the normal detach case so it needs
1538 * to be careful about only freeing resources that have actually been
1539 * allocated.
1540 */
1541 static int
xl_detach(device_t dev)1542 xl_detach(device_t dev)
1543 {
1544 struct xl_softc *sc;
1545 if_t ifp;
1546 int rid, res;
1547
1548 sc = device_get_softc(dev);
1549 ifp = sc->xl_ifp;
1550
1551 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1552
1553 #ifdef DEVICE_POLLING
1554 if (ifp && if_getcapenable(ifp) & IFCAP_POLLING)
1555 ether_poll_deregister(ifp);
1556 #endif
1557
1558 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1559 rid = XL_PCI_LOMEM;
1560 res = SYS_RES_MEMORY;
1561 } else {
1562 rid = XL_PCI_LOIO;
1563 res = SYS_RES_IOPORT;
1564 }
1565
1566 /* These should only be active if attach succeeded */
1567 if (device_is_attached(dev)) {
1568 XL_LOCK(sc);
1569 xl_stop(sc);
1570 XL_UNLOCK(sc);
1571 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1572 callout_drain(&sc->xl_tick_callout);
1573 ether_ifdetach(ifp);
1574 }
1575 bus_generic_detach(dev);
1576 ifmedia_removeall(&sc->ifmedia);
1577
1578 if (sc->xl_intrhand)
1579 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1580 if (sc->xl_irq)
1581 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1582 if (sc->xl_fres != NULL)
1583 bus_release_resource(dev, SYS_RES_MEMORY,
1584 XL_PCI_FUNCMEM, sc->xl_fres);
1585 if (sc->xl_res)
1586 bus_release_resource(dev, res, rid, sc->xl_res);
1587
1588 if (ifp)
1589 if_free(ifp);
1590
1591 if (sc->xl_mtag) {
1592 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1593 bus_dma_tag_destroy(sc->xl_mtag);
1594 }
1595 if (sc->xl_ldata.xl_rx_tag) {
1596 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1597 sc->xl_ldata.xl_rx_dmamap);
1598 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1599 sc->xl_ldata.xl_rx_dmamap);
1600 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1601 }
1602 if (sc->xl_ldata.xl_tx_tag) {
1603 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1604 sc->xl_ldata.xl_tx_dmamap);
1605 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1606 sc->xl_ldata.xl_tx_dmamap);
1607 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1608 }
1609
1610 mtx_destroy(&sc->xl_mtx);
1611
1612 return (0);
1613 }
1614
1615 /*
1616 * Initialize the transmit descriptors.
1617 */
1618 static int
xl_list_tx_init(struct xl_softc * sc)1619 xl_list_tx_init(struct xl_softc *sc)
1620 {
1621 struct xl_chain_data *cd;
1622 struct xl_list_data *ld;
1623 int error, i;
1624
1625 XL_LOCK_ASSERT(sc);
1626
1627 cd = &sc->xl_cdata;
1628 ld = &sc->xl_ldata;
1629 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1630 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1631 error = bus_dmamap_create(sc->xl_mtag, 0,
1632 &cd->xl_tx_chain[i].xl_map);
1633 if (error)
1634 return (error);
1635 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1636 i * sizeof(struct xl_list);
1637 if (i == (XL_TX_LIST_CNT - 1))
1638 cd->xl_tx_chain[i].xl_next = NULL;
1639 else
1640 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1641 }
1642
1643 cd->xl_tx_free = &cd->xl_tx_chain[0];
1644 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1645
1646 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1647 return (0);
1648 }
1649
1650 /*
1651 * Initialize the transmit descriptors.
1652 */
1653 static int
xl_list_tx_init_90xB(struct xl_softc * sc)1654 xl_list_tx_init_90xB(struct xl_softc *sc)
1655 {
1656 struct xl_chain_data *cd;
1657 struct xl_list_data *ld;
1658 int error, i;
1659
1660 XL_LOCK_ASSERT(sc);
1661
1662 cd = &sc->xl_cdata;
1663 ld = &sc->xl_ldata;
1664 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1665 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1666 error = bus_dmamap_create(sc->xl_mtag, 0,
1667 &cd->xl_tx_chain[i].xl_map);
1668 if (error)
1669 return (error);
1670 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1671 i * sizeof(struct xl_list);
1672 if (i == (XL_TX_LIST_CNT - 1))
1673 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1674 else
1675 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1676 if (i == 0)
1677 cd->xl_tx_chain[i].xl_prev =
1678 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1679 else
1680 cd->xl_tx_chain[i].xl_prev =
1681 &cd->xl_tx_chain[i - 1];
1682 }
1683
1684 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1685 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1686
1687 cd->xl_tx_prod = 1;
1688 cd->xl_tx_cons = 1;
1689 cd->xl_tx_cnt = 0;
1690
1691 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1692 return (0);
1693 }
1694
1695 /*
1696 * Initialize the RX descriptors and allocate mbufs for them. Note that
1697 * we arrange the descriptors in a closed ring, so that the last descriptor
1698 * points back to the first.
1699 */
1700 static int
xl_list_rx_init(struct xl_softc * sc)1701 xl_list_rx_init(struct xl_softc *sc)
1702 {
1703 struct xl_chain_data *cd;
1704 struct xl_list_data *ld;
1705 int error, i, next;
1706 u_int32_t nextptr;
1707
1708 XL_LOCK_ASSERT(sc);
1709
1710 cd = &sc->xl_cdata;
1711 ld = &sc->xl_ldata;
1712
1713 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1714 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1715 error = bus_dmamap_create(sc->xl_mtag, 0,
1716 &cd->xl_rx_chain[i].xl_map);
1717 if (error)
1718 return (error);
1719 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1720 if (error)
1721 return (error);
1722 if (i == (XL_RX_LIST_CNT - 1))
1723 next = 0;
1724 else
1725 next = i + 1;
1726 nextptr = ld->xl_rx_dmaaddr +
1727 next * sizeof(struct xl_list_onefrag);
1728 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1729 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1730 }
1731
1732 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1733 cd->xl_rx_head = &cd->xl_rx_chain[0];
1734
1735 return (0);
1736 }
1737
1738 /*
1739 * Initialize an RX descriptor and attach an MBUF cluster.
1740 * If we fail to do so, we need to leave the old mbuf and
1741 * the old DMA map untouched so that it can be reused.
1742 */
1743 static int
xl_newbuf(struct xl_softc * sc,struct xl_chain_onefrag * c)1744 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1745 {
1746 struct mbuf *m_new = NULL;
1747 bus_dmamap_t map;
1748 bus_dma_segment_t segs[1];
1749 int error, nseg;
1750
1751 XL_LOCK_ASSERT(sc);
1752
1753 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1754 if (m_new == NULL)
1755 return (ENOBUFS);
1756
1757 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1758
1759 /* Force longword alignment for packet payload. */
1760 m_adj(m_new, ETHER_ALIGN);
1761
1762 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1763 segs, &nseg, BUS_DMA_NOWAIT);
1764 if (error) {
1765 m_freem(m_new);
1766 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1767 error);
1768 return (error);
1769 }
1770 KASSERT(nseg == 1,
1771 ("%s: too many DMA segments (%d)", __func__, nseg));
1772
1773 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1774 map = c->xl_map;
1775 c->xl_map = sc->xl_tmpmap;
1776 sc->xl_tmpmap = map;
1777 c->xl_mbuf = m_new;
1778 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1779 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1780 c->xl_ptr->xl_status = 0;
1781 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1782 return (0);
1783 }
1784
1785 static int
xl_rx_resync(struct xl_softc * sc)1786 xl_rx_resync(struct xl_softc *sc)
1787 {
1788 struct xl_chain_onefrag *pos;
1789 int i;
1790
1791 XL_LOCK_ASSERT(sc);
1792
1793 pos = sc->xl_cdata.xl_rx_head;
1794
1795 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1796 if (pos->xl_ptr->xl_status)
1797 break;
1798 pos = pos->xl_next;
1799 }
1800
1801 if (i == XL_RX_LIST_CNT)
1802 return (0);
1803
1804 sc->xl_cdata.xl_rx_head = pos;
1805
1806 return (EAGAIN);
1807 }
1808
1809 /*
1810 * A frame has been uploaded: pass the resulting mbuf chain up to
1811 * the higher level protocols.
1812 */
1813 static int
xl_rxeof(struct xl_softc * sc)1814 xl_rxeof(struct xl_softc *sc)
1815 {
1816 struct mbuf *m;
1817 if_t ifp = sc->xl_ifp;
1818 struct xl_chain_onefrag *cur_rx;
1819 int total_len;
1820 int rx_npkts = 0;
1821 u_int32_t rxstat;
1822
1823 XL_LOCK_ASSERT(sc);
1824 again:
1825 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1826 BUS_DMASYNC_POSTREAD);
1827 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1828 #ifdef DEVICE_POLLING
1829 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1830 if (sc->rxcycles <= 0)
1831 break;
1832 sc->rxcycles--;
1833 }
1834 #endif
1835 cur_rx = sc->xl_cdata.xl_rx_head;
1836 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1837 total_len = rxstat & XL_RXSTAT_LENMASK;
1838 rx_npkts++;
1839
1840 /*
1841 * Since we have told the chip to allow large frames,
1842 * we need to trap giant frame errors in software. We allow
1843 * a little more than the normal frame size to account for
1844 * frames with VLAN tags.
1845 */
1846 if (total_len > XL_MAX_FRAMELEN)
1847 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1848
1849 /*
1850 * If an error occurs, update stats, clear the
1851 * status word and leave the mbuf cluster in place:
1852 * it should simply get re-used next time this descriptor
1853 * comes up in the ring.
1854 */
1855 if (rxstat & XL_RXSTAT_UP_ERROR) {
1856 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1857 cur_rx->xl_ptr->xl_status = 0;
1858 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1859 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1860 continue;
1861 }
1862
1863 /*
1864 * If the error bit was not set, the upload complete
1865 * bit should be set which means we have a valid packet.
1866 * If not, something truly strange has happened.
1867 */
1868 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1869 device_printf(sc->xl_dev,
1870 "bad receive status -- packet dropped\n");
1871 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1872 cur_rx->xl_ptr->xl_status = 0;
1873 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1874 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1875 continue;
1876 }
1877
1878 /* No errors; receive the packet. */
1879 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1880 BUS_DMASYNC_POSTREAD);
1881 m = cur_rx->xl_mbuf;
1882
1883 /*
1884 * Try to conjure up a new mbuf cluster. If that
1885 * fails, it means we have an out of memory condition and
1886 * should leave the buffer in place and continue. This will
1887 * result in a lost packet, but there's little else we
1888 * can do in this situation.
1889 */
1890 if (xl_newbuf(sc, cur_rx)) {
1891 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1892 cur_rx->xl_ptr->xl_status = 0;
1893 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1894 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1895 continue;
1896 }
1897 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1898 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1899
1900 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1901 m->m_pkthdr.rcvif = ifp;
1902 m->m_pkthdr.len = m->m_len = total_len;
1903
1904 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
1905 /* Do IP checksum checking. */
1906 if (rxstat & XL_RXSTAT_IPCKOK)
1907 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1908 if (!(rxstat & XL_RXSTAT_IPCKERR))
1909 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1910 if ((rxstat & XL_RXSTAT_TCPCOK &&
1911 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1912 (rxstat & XL_RXSTAT_UDPCKOK &&
1913 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1914 m->m_pkthdr.csum_flags |=
1915 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1916 m->m_pkthdr.csum_data = 0xffff;
1917 }
1918 }
1919
1920 XL_UNLOCK(sc);
1921 if_input(ifp, m);
1922 XL_LOCK(sc);
1923
1924 /*
1925 * If we are running from the taskqueue, the interface
1926 * might have been stopped while we were passing the last
1927 * packet up the network stack.
1928 */
1929 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
1930 return (rx_npkts);
1931 }
1932
1933 /*
1934 * Handle the 'end of channel' condition. When the upload
1935 * engine hits the end of the RX ring, it will stall. This
1936 * is our cue to flush the RX ring, reload the uplist pointer
1937 * register and unstall the engine.
1938 * XXX This is actually a little goofy. With the ThunderLAN
1939 * chip, you get an interrupt when the receiver hits the end
1940 * of the receive ring, which tells you exactly when you
1941 * you need to reload the ring pointer. Here we have to
1942 * fake it. I'm mad at myself for not being clever enough
1943 * to avoid the use of a goto here.
1944 */
1945 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1946 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1948 xl_wait(sc);
1949 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1950 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1952 goto again;
1953 }
1954 return (rx_npkts);
1955 }
1956
1957 /*
1958 * Taskqueue wrapper for xl_rxeof().
1959 */
1960 static void
xl_rxeof_task(void * arg,int pending)1961 xl_rxeof_task(void *arg, int pending)
1962 {
1963 struct xl_softc *sc = (struct xl_softc *)arg;
1964
1965 XL_LOCK(sc);
1966 if (if_getdrvflags(sc->xl_ifp) & IFF_DRV_RUNNING)
1967 xl_rxeof(sc);
1968 XL_UNLOCK(sc);
1969 }
1970
1971 /*
1972 * A frame was downloaded to the chip. It's safe for us to clean up
1973 * the list buffers.
1974 */
1975 static void
xl_txeof(struct xl_softc * sc)1976 xl_txeof(struct xl_softc *sc)
1977 {
1978 struct xl_chain *cur_tx;
1979 if_t ifp = sc->xl_ifp;
1980
1981 XL_LOCK_ASSERT(sc);
1982
1983 /*
1984 * Go through our tx list and free mbufs for those
1985 * frames that have been uploaded. Note: the 3c905B
1986 * sets a special bit in the status word to let us
1987 * know that a frame has been downloaded, but the
1988 * original 3c900/3c905 adapters don't do that.
1989 * Consequently, we have to use a different test if
1990 * xl_type != XL_TYPE_905B.
1991 */
1992 while (sc->xl_cdata.xl_tx_head != NULL) {
1993 cur_tx = sc->xl_cdata.xl_tx_head;
1994
1995 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1996 break;
1997
1998 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1999 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2000 BUS_DMASYNC_POSTWRITE);
2001 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2002 m_freem(cur_tx->xl_mbuf);
2003 cur_tx->xl_mbuf = NULL;
2004 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2005 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2006
2007 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2008 sc->xl_cdata.xl_tx_free = cur_tx;
2009 }
2010
2011 if (sc->xl_cdata.xl_tx_head == NULL) {
2012 sc->xl_wdog_timer = 0;
2013 sc->xl_cdata.xl_tx_tail = NULL;
2014 } else {
2015 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2016 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2017 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2018 sc->xl_cdata.xl_tx_head->xl_phys);
2019 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2020 }
2021 }
2022 }
2023
2024 static void
xl_txeof_90xB(struct xl_softc * sc)2025 xl_txeof_90xB(struct xl_softc *sc)
2026 {
2027 struct xl_chain *cur_tx = NULL;
2028 if_t ifp = sc->xl_ifp;
2029 int idx;
2030
2031 XL_LOCK_ASSERT(sc);
2032
2033 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2034 BUS_DMASYNC_POSTREAD);
2035 idx = sc->xl_cdata.xl_tx_cons;
2036 while (idx != sc->xl_cdata.xl_tx_prod) {
2037 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2038
2039 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2040 XL_TXSTAT_DL_COMPLETE))
2041 break;
2042
2043 if (cur_tx->xl_mbuf != NULL) {
2044 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2045 BUS_DMASYNC_POSTWRITE);
2046 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2047 m_freem(cur_tx->xl_mbuf);
2048 cur_tx->xl_mbuf = NULL;
2049 }
2050
2051 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2052
2053 sc->xl_cdata.xl_tx_cnt--;
2054 XL_INC(idx, XL_TX_LIST_CNT);
2055 }
2056
2057 if (sc->xl_cdata.xl_tx_cnt == 0)
2058 sc->xl_wdog_timer = 0;
2059 sc->xl_cdata.xl_tx_cons = idx;
2060
2061 if (cur_tx != NULL)
2062 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2063 }
2064
2065 /*
2066 * TX 'end of channel' interrupt handler. Actually, we should
2067 * only get a 'TX complete' interrupt if there's a transmit error,
2068 * so this is really TX error handler.
2069 */
2070 static void
xl_txeoc(struct xl_softc * sc)2071 xl_txeoc(struct xl_softc *sc)
2072 {
2073 u_int8_t txstat;
2074
2075 XL_LOCK_ASSERT(sc);
2076
2077 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2078 if (txstat & XL_TXSTATUS_UNDERRUN ||
2079 txstat & XL_TXSTATUS_JABBER ||
2080 txstat & XL_TXSTATUS_RECLAIM) {
2081 device_printf(sc->xl_dev,
2082 "transmission error: 0x%02x\n", txstat);
2083 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2084 xl_wait(sc);
2085 if (sc->xl_type == XL_TYPE_905B) {
2086 if (sc->xl_cdata.xl_tx_cnt) {
2087 int i;
2088 struct xl_chain *c;
2089
2090 i = sc->xl_cdata.xl_tx_cons;
2091 c = &sc->xl_cdata.xl_tx_chain[i];
2092 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2093 c->xl_phys);
2094 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2095 sc->xl_wdog_timer = 5;
2096 }
2097 } else {
2098 if (sc->xl_cdata.xl_tx_head != NULL) {
2099 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2100 sc->xl_cdata.xl_tx_head->xl_phys);
2101 sc->xl_wdog_timer = 5;
2102 }
2103 }
2104 /*
2105 * Remember to set this for the
2106 * first generation 3c90X chips.
2107 */
2108 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2109 if (txstat & XL_TXSTATUS_UNDERRUN &&
2110 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2111 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2112 device_printf(sc->xl_dev,
2113 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2114 }
2115 CSR_WRITE_2(sc, XL_COMMAND,
2116 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2117 if (sc->xl_type == XL_TYPE_905B) {
2118 CSR_WRITE_2(sc, XL_COMMAND,
2119 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2120 }
2121 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2122 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2123 } else {
2124 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2125 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2126 }
2127 /*
2128 * Write an arbitrary byte to the TX_STATUS register
2129 * to clear this interrupt/error and advance to the next.
2130 */
2131 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2132 }
2133 }
2134
2135 static void
xl_intr(void * arg)2136 xl_intr(void *arg)
2137 {
2138 struct xl_softc *sc = arg;
2139 if_t ifp = sc->xl_ifp;
2140 u_int16_t status;
2141
2142 XL_LOCK(sc);
2143
2144 #ifdef DEVICE_POLLING
2145 if (if_getcapenable(ifp) & IFCAP_POLLING) {
2146 XL_UNLOCK(sc);
2147 return;
2148 }
2149 #endif
2150
2151 for (;;) {
2152 status = CSR_READ_2(sc, XL_STATUS);
2153 if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2154 break;
2155 CSR_WRITE_2(sc, XL_COMMAND,
2156 XL_CMD_INTR_ACK|(status & XL_INTRS));
2157 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2158 break;
2159
2160 if (status & XL_STAT_UP_COMPLETE) {
2161 if (xl_rxeof(sc) == 0) {
2162 while (xl_rx_resync(sc))
2163 xl_rxeof(sc);
2164 }
2165 }
2166
2167 if (status & XL_STAT_DOWN_COMPLETE) {
2168 if (sc->xl_type == XL_TYPE_905B)
2169 xl_txeof_90xB(sc);
2170 else
2171 xl_txeof(sc);
2172 }
2173
2174 if (status & XL_STAT_TX_COMPLETE) {
2175 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2176 xl_txeoc(sc);
2177 }
2178
2179 if (status & XL_STAT_ADFAIL) {
2180 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2181 xl_init_locked(sc);
2182 break;
2183 }
2184
2185 if (status & XL_STAT_STATSOFLOW)
2186 xl_stats_update(sc);
2187 }
2188
2189 if (!if_sendq_empty(ifp) &&
2190 if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2191 if (sc->xl_type == XL_TYPE_905B)
2192 xl_start_90xB_locked(ifp);
2193 else
2194 xl_start_locked(ifp);
2195 }
2196
2197 XL_UNLOCK(sc);
2198 }
2199
2200 #ifdef DEVICE_POLLING
2201 static int
xl_poll(if_t ifp,enum poll_cmd cmd,int count)2202 xl_poll(if_t ifp, enum poll_cmd cmd, int count)
2203 {
2204 struct xl_softc *sc = if_getsoftc(ifp);
2205 int rx_npkts = 0;
2206
2207 XL_LOCK(sc);
2208 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2209 rx_npkts = xl_poll_locked(ifp, cmd, count);
2210 XL_UNLOCK(sc);
2211 return (rx_npkts);
2212 }
2213
2214 static int
xl_poll_locked(if_t ifp,enum poll_cmd cmd,int count)2215 xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count)
2216 {
2217 struct xl_softc *sc = if_getsoftc(ifp);
2218 int rx_npkts;
2219
2220 XL_LOCK_ASSERT(sc);
2221
2222 sc->rxcycles = count;
2223 rx_npkts = xl_rxeof(sc);
2224 if (sc->xl_type == XL_TYPE_905B)
2225 xl_txeof_90xB(sc);
2226 else
2227 xl_txeof(sc);
2228
2229 if (!if_sendq_empty(ifp)) {
2230 if (sc->xl_type == XL_TYPE_905B)
2231 xl_start_90xB_locked(ifp);
2232 else
2233 xl_start_locked(ifp);
2234 }
2235
2236 if (cmd == POLL_AND_CHECK_STATUS) {
2237 u_int16_t status;
2238
2239 status = CSR_READ_2(sc, XL_STATUS);
2240 if (status & XL_INTRS && status != 0xFFFF) {
2241 CSR_WRITE_2(sc, XL_COMMAND,
2242 XL_CMD_INTR_ACK|(status & XL_INTRS));
2243
2244 if (status & XL_STAT_TX_COMPLETE) {
2245 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2246 xl_txeoc(sc);
2247 }
2248
2249 if (status & XL_STAT_ADFAIL) {
2250 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2251 xl_init_locked(sc);
2252 }
2253
2254 if (status & XL_STAT_STATSOFLOW)
2255 xl_stats_update(sc);
2256 }
2257 }
2258 return (rx_npkts);
2259 }
2260 #endif /* DEVICE_POLLING */
2261
2262 static void
xl_tick(void * xsc)2263 xl_tick(void *xsc)
2264 {
2265 struct xl_softc *sc = xsc;
2266 struct mii_data *mii;
2267
2268 XL_LOCK_ASSERT(sc);
2269
2270 if (sc->xl_miibus != NULL) {
2271 mii = device_get_softc(sc->xl_miibus);
2272 mii_tick(mii);
2273 }
2274
2275 xl_stats_update(sc);
2276 if (xl_watchdog(sc) == EJUSTRETURN)
2277 return;
2278
2279 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2280 }
2281
2282 static void
xl_stats_update(struct xl_softc * sc)2283 xl_stats_update(struct xl_softc *sc)
2284 {
2285 if_t ifp = sc->xl_ifp;
2286 struct xl_stats xl_stats;
2287 u_int8_t *p;
2288 int i;
2289
2290 XL_LOCK_ASSERT(sc);
2291
2292 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2293
2294 p = (u_int8_t *)&xl_stats;
2295
2296 /* Read all the stats registers. */
2297 XL_SEL_WIN(6);
2298
2299 for (i = 0; i < 16; i++)
2300 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2301
2302 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2303
2304 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2305 xl_stats.xl_tx_multi_collision +
2306 xl_stats.xl_tx_single_collision +
2307 xl_stats.xl_tx_late_collision);
2308
2309 /*
2310 * Boomerang and cyclone chips have an extra stats counter
2311 * in window 4 (BadSSD). We have to read this too in order
2312 * to clear out all the stats registers and avoid a statsoflow
2313 * interrupt.
2314 */
2315 XL_SEL_WIN(4);
2316 CSR_READ_1(sc, XL_W4_BADSSD);
2317 XL_SEL_WIN(7);
2318 }
2319
2320 /*
2321 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2322 * pointers to the fragment pointers.
2323 */
2324 static int
xl_encap(struct xl_softc * sc,struct xl_chain * c,struct mbuf ** m_head)2325 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2326 {
2327 struct mbuf *m_new;
2328 if_t ifp = sc->xl_ifp;
2329 int error, i, nseg, total_len;
2330 u_int32_t status;
2331
2332 XL_LOCK_ASSERT(sc);
2333
2334 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2335 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2336
2337 if (error && error != EFBIG) {
2338 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2339 return (error);
2340 }
2341
2342 /*
2343 * Handle special case: we used up all 63 fragments,
2344 * but we have more mbufs left in the chain. Copy the
2345 * data into an mbuf cluster. Note that we don't
2346 * bother clearing the values in the other fragment
2347 * pointers/counters; it wouldn't gain us anything,
2348 * and would waste cycles.
2349 */
2350 if (error) {
2351 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2352 if (m_new == NULL) {
2353 m_freem(*m_head);
2354 *m_head = NULL;
2355 return (ENOBUFS);
2356 }
2357 *m_head = m_new;
2358
2359 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2360 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2361 if (error) {
2362 m_freem(*m_head);
2363 *m_head = NULL;
2364 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2365 return (error);
2366 }
2367 }
2368
2369 KASSERT(nseg <= XL_MAXFRAGS,
2370 ("%s: too many DMA segments (%d)", __func__, nseg));
2371 if (nseg == 0) {
2372 m_freem(*m_head);
2373 *m_head = NULL;
2374 return (EIO);
2375 }
2376 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2377
2378 total_len = 0;
2379 for (i = 0; i < nseg; i++) {
2380 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2381 ("segment size too large"));
2382 c->xl_ptr->xl_frag[i].xl_addr =
2383 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2384 c->xl_ptr->xl_frag[i].xl_len =
2385 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2386 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2387 }
2388 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2389
2390 if (sc->xl_type == XL_TYPE_905B) {
2391 status = XL_TXSTAT_RND_DEFEAT;
2392
2393 #ifndef XL905B_TXCSUM_BROKEN
2394 if ((*m_head)->m_pkthdr.csum_flags) {
2395 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2396 status |= XL_TXSTAT_IPCKSUM;
2397 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2398 status |= XL_TXSTAT_TCPCKSUM;
2399 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2400 status |= XL_TXSTAT_UDPCKSUM;
2401 }
2402 #endif
2403 } else
2404 status = total_len;
2405 c->xl_ptr->xl_status = htole32(status);
2406 c->xl_ptr->xl_next = 0;
2407
2408 c->xl_mbuf = *m_head;
2409 return (0);
2410 }
2411
2412 /*
2413 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2414 * to the mbuf data regions directly in the transmit lists. We also save a
2415 * copy of the pointers since the transmit list fragment pointers are
2416 * physical addresses.
2417 */
2418
2419 static void
xl_start(if_t ifp)2420 xl_start(if_t ifp)
2421 {
2422 struct xl_softc *sc = if_getsoftc(ifp);
2423
2424 XL_LOCK(sc);
2425
2426 if (sc->xl_type == XL_TYPE_905B)
2427 xl_start_90xB_locked(ifp);
2428 else
2429 xl_start_locked(ifp);
2430
2431 XL_UNLOCK(sc);
2432 }
2433
2434 static void
xl_start_locked(if_t ifp)2435 xl_start_locked(if_t ifp)
2436 {
2437 struct xl_softc *sc = if_getsoftc(ifp);
2438 struct mbuf *m_head;
2439 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2440 struct xl_chain *prev_tx;
2441 int error;
2442
2443 XL_LOCK_ASSERT(sc);
2444
2445 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2446 IFF_DRV_RUNNING)
2447 return;
2448 /*
2449 * Check for an available queue slot. If there are none,
2450 * punt.
2451 */
2452 if (sc->xl_cdata.xl_tx_free == NULL) {
2453 xl_txeoc(sc);
2454 xl_txeof(sc);
2455 if (sc->xl_cdata.xl_tx_free == NULL) {
2456 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2457 return;
2458 }
2459 }
2460
2461 start_tx = sc->xl_cdata.xl_tx_free;
2462
2463 for (; !if_sendq_empty(ifp) &&
2464 sc->xl_cdata.xl_tx_free != NULL;) {
2465 m_head = if_dequeue(ifp);
2466 if (m_head == NULL)
2467 break;
2468
2469 /* Pick a descriptor off the free list. */
2470 prev_tx = cur_tx;
2471 cur_tx = sc->xl_cdata.xl_tx_free;
2472
2473 /* Pack the data into the descriptor. */
2474 error = xl_encap(sc, cur_tx, &m_head);
2475 if (error) {
2476 cur_tx = prev_tx;
2477 if (m_head == NULL)
2478 break;
2479 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2480 if_sendq_prepend(ifp, m_head);
2481 break;
2482 }
2483
2484 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2485 cur_tx->xl_next = NULL;
2486
2487 /* Chain it together. */
2488 if (prev != NULL) {
2489 prev->xl_next = cur_tx;
2490 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2491 }
2492 prev = cur_tx;
2493
2494 /*
2495 * If there's a BPF listener, bounce a copy of this frame
2496 * to him.
2497 */
2498 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2499 }
2500
2501 /*
2502 * If there are no packets queued, bail.
2503 */
2504 if (cur_tx == NULL)
2505 return;
2506
2507 /*
2508 * Place the request for the upload interrupt
2509 * in the last descriptor in the chain. This way, if
2510 * we're chaining several packets at once, we'll only
2511 * get an interrupt once for the whole chain rather than
2512 * once for each packet.
2513 */
2514 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2515
2516 /*
2517 * Queue the packets. If the TX channel is clear, update
2518 * the downlist pointer register.
2519 */
2520 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2521 xl_wait(sc);
2522
2523 if (sc->xl_cdata.xl_tx_head != NULL) {
2524 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2525 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2526 htole32(start_tx->xl_phys);
2527 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2528 htole32(~XL_TXSTAT_DL_INTR);
2529 sc->xl_cdata.xl_tx_tail = cur_tx;
2530 } else {
2531 sc->xl_cdata.xl_tx_head = start_tx;
2532 sc->xl_cdata.xl_tx_tail = cur_tx;
2533 }
2534 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2535 BUS_DMASYNC_PREWRITE);
2536 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2537 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2538
2539 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2540
2541 XL_SEL_WIN(7);
2542
2543 /*
2544 * Set a timeout in case the chip goes out to lunch.
2545 */
2546 sc->xl_wdog_timer = 5;
2547
2548 /*
2549 * XXX Under certain conditions, usually on slower machines
2550 * where interrupts may be dropped, it's possible for the
2551 * adapter to chew up all the buffers in the receive ring
2552 * and stall, without us being able to do anything about it.
2553 * To guard against this, we need to make a pass over the
2554 * RX queue to make sure there aren't any packets pending.
2555 * Doing it here means we can flush the receive ring at the
2556 * same time the chip is DMAing the transmit descriptors we
2557 * just gave it.
2558 *
2559 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2560 * nature of their chips in all their marketing literature;
2561 * we may as well take advantage of it. :)
2562 */
2563 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2564 }
2565
2566 static void
xl_start_90xB_locked(if_t ifp)2567 xl_start_90xB_locked(if_t ifp)
2568 {
2569 struct xl_softc *sc = if_getsoftc(ifp);
2570 struct mbuf *m_head;
2571 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2572 struct xl_chain *prev_tx;
2573 int error, idx;
2574
2575 XL_LOCK_ASSERT(sc);
2576
2577 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2578 IFF_DRV_RUNNING)
2579 return;
2580
2581 idx = sc->xl_cdata.xl_tx_prod;
2582 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2583
2584 for (; !if_sendq_empty(ifp) &&
2585 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2586 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2587 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2588 break;
2589 }
2590
2591 m_head = if_dequeue(ifp);
2592 if (m_head == NULL)
2593 break;
2594
2595 prev_tx = cur_tx;
2596 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2597
2598 /* Pack the data into the descriptor. */
2599 error = xl_encap(sc, cur_tx, &m_head);
2600 if (error) {
2601 cur_tx = prev_tx;
2602 if (m_head == NULL)
2603 break;
2604 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2605 if_sendq_prepend(ifp, m_head);
2606 break;
2607 }
2608
2609 /* Chain it together. */
2610 if (prev != NULL)
2611 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2612 prev = cur_tx;
2613
2614 /*
2615 * If there's a BPF listener, bounce a copy of this frame
2616 * to him.
2617 */
2618 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2619
2620 XL_INC(idx, XL_TX_LIST_CNT);
2621 sc->xl_cdata.xl_tx_cnt++;
2622 }
2623
2624 /*
2625 * If there are no packets queued, bail.
2626 */
2627 if (cur_tx == NULL)
2628 return;
2629
2630 /*
2631 * Place the request for the upload interrupt
2632 * in the last descriptor in the chain. This way, if
2633 * we're chaining several packets at once, we'll only
2634 * get an interrupt once for the whole chain rather than
2635 * once for each packet.
2636 */
2637 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2638
2639 /* Start transmission */
2640 sc->xl_cdata.xl_tx_prod = idx;
2641 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2642 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2643 BUS_DMASYNC_PREWRITE);
2644
2645 /*
2646 * Set a timeout in case the chip goes out to lunch.
2647 */
2648 sc->xl_wdog_timer = 5;
2649 }
2650
2651 static void
xl_init(void * xsc)2652 xl_init(void *xsc)
2653 {
2654 struct xl_softc *sc = xsc;
2655
2656 XL_LOCK(sc);
2657 xl_init_locked(sc);
2658 XL_UNLOCK(sc);
2659 }
2660
2661 static void
xl_init_locked(struct xl_softc * sc)2662 xl_init_locked(struct xl_softc *sc)
2663 {
2664 if_t ifp = sc->xl_ifp;
2665 int error, i;
2666 struct mii_data *mii = NULL;
2667
2668 XL_LOCK_ASSERT(sc);
2669
2670 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2671 return;
2672 /*
2673 * Cancel pending I/O and free all RX/TX buffers.
2674 */
2675 xl_stop(sc);
2676
2677 /* Reset the chip to a known state. */
2678 xl_reset(sc);
2679
2680 if (sc->xl_miibus == NULL) {
2681 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2682 xl_wait(sc);
2683 }
2684 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2685 xl_wait(sc);
2686 DELAY(10000);
2687
2688 if (sc->xl_miibus != NULL)
2689 mii = device_get_softc(sc->xl_miibus);
2690
2691 /*
2692 * Clear WOL status and disable all WOL feature as WOL
2693 * would interfere Rx operation under normal environments.
2694 */
2695 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2696 XL_SEL_WIN(7);
2697 CSR_READ_2(sc, XL_W7_BM_PME);
2698 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2699 }
2700 /* Init our MAC address */
2701 XL_SEL_WIN(2);
2702 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2703 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2704 if_getlladdr(sc->xl_ifp)[i]);
2705 }
2706
2707 /* Clear the station mask. */
2708 for (i = 0; i < 3; i++)
2709 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2710 #ifdef notdef
2711 /* Reset TX and RX. */
2712 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2713 xl_wait(sc);
2714 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2715 xl_wait(sc);
2716 #endif
2717 /* Init circular RX list. */
2718 error = xl_list_rx_init(sc);
2719 if (error) {
2720 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2721 error);
2722 xl_stop(sc);
2723 return;
2724 }
2725
2726 /* Init TX descriptors. */
2727 if (sc->xl_type == XL_TYPE_905B)
2728 error = xl_list_tx_init_90xB(sc);
2729 else
2730 error = xl_list_tx_init(sc);
2731 if (error) {
2732 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2733 error);
2734 xl_stop(sc);
2735 return;
2736 }
2737
2738 /*
2739 * Set the TX freethresh value.
2740 * Note that this has no effect on 3c905B "cyclone"
2741 * cards but is required for 3c900/3c905 "boomerang"
2742 * cards in order to enable the download engine.
2743 */
2744 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2745
2746 /* Set the TX start threshold for best performance. */
2747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2748
2749 /*
2750 * If this is a 3c905B, also set the tx reclaim threshold.
2751 * This helps cut down on the number of tx reclaim errors
2752 * that could happen on a busy network. The chip multiplies
2753 * the register value by 16 to obtain the actual threshold
2754 * in bytes, so we divide by 16 when setting the value here.
2755 * The existing threshold value can be examined by reading
2756 * the register at offset 9 in window 5.
2757 */
2758 if (sc->xl_type == XL_TYPE_905B) {
2759 CSR_WRITE_2(sc, XL_COMMAND,
2760 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2761 }
2762
2763 /* Set RX filter bits. */
2764 xl_rxfilter(sc);
2765
2766 /*
2767 * Load the address of the RX list. We have to
2768 * stall the upload engine before we can manipulate
2769 * the uplist pointer register, then unstall it when
2770 * we're finished. We also have to wait for the
2771 * stall command to complete before proceeding.
2772 * Note that we have to do this after any RX resets
2773 * have completed since the uplist register is cleared
2774 * by a reset.
2775 */
2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2777 xl_wait(sc);
2778 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2780 xl_wait(sc);
2781
2782 if (sc->xl_type == XL_TYPE_905B) {
2783 /* Set polling interval */
2784 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2785 /* Load the address of the TX list */
2786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2787 xl_wait(sc);
2788 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2789 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2790 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2791 xl_wait(sc);
2792 }
2793
2794 /*
2795 * If the coax transceiver is on, make sure to enable
2796 * the DC-DC converter.
2797 */
2798 XL_SEL_WIN(3);
2799 if (sc->xl_xcvr == XL_XCVR_COAX)
2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2801 else
2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2803
2804 /*
2805 * increase packet size to allow reception of 802.1q or ISL packets.
2806 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2807 * control register. For 3c90xB/C chips, use the RX packet size
2808 * register.
2809 */
2810
2811 if (sc->xl_type == XL_TYPE_905B)
2812 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2813 else {
2814 u_int8_t macctl;
2815 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2816 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2817 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2818 }
2819
2820 /* Clear out the stats counters. */
2821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2822 xl_stats_update(sc);
2823 XL_SEL_WIN(4);
2824 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2826
2827 /*
2828 * Enable interrupts.
2829 */
2830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2832 #ifdef DEVICE_POLLING
2833 /* Disable interrupts if we are polling. */
2834 if (if_getcapenable(ifp) & IFCAP_POLLING)
2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2836 else
2837 #endif
2838 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2839 if (sc->xl_flags & XL_FLAG_FUNCREG)
2840 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2841
2842 /* Set the RX early threshold */
2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2844 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2845
2846 /* Enable receiver and transmitter. */
2847 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2848 xl_wait(sc);
2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2850 xl_wait(sc);
2851
2852 /* XXX Downcall to miibus. */
2853 if (mii != NULL)
2854 mii_mediachg(mii);
2855
2856 /* Select window 7 for normal operations. */
2857 XL_SEL_WIN(7);
2858
2859 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2860 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2861
2862 sc->xl_wdog_timer = 0;
2863 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2864 }
2865
2866 /*
2867 * Set media options.
2868 */
2869 static int
xl_ifmedia_upd(if_t ifp)2870 xl_ifmedia_upd(if_t ifp)
2871 {
2872 struct xl_softc *sc = if_getsoftc(ifp);
2873 struct ifmedia *ifm = NULL;
2874 struct mii_data *mii = NULL;
2875
2876 XL_LOCK(sc);
2877
2878 if (sc->xl_miibus != NULL)
2879 mii = device_get_softc(sc->xl_miibus);
2880 if (mii == NULL)
2881 ifm = &sc->ifmedia;
2882 else
2883 ifm = &mii->mii_media;
2884
2885 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2886 case IFM_100_FX:
2887 case IFM_10_FL:
2888 case IFM_10_2:
2889 case IFM_10_5:
2890 xl_setmode(sc, ifm->ifm_media);
2891 XL_UNLOCK(sc);
2892 return (0);
2893 }
2894
2895 if (sc->xl_media & XL_MEDIAOPT_MII ||
2896 sc->xl_media & XL_MEDIAOPT_BTX ||
2897 sc->xl_media & XL_MEDIAOPT_BT4) {
2898 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2899 xl_init_locked(sc);
2900 } else {
2901 xl_setmode(sc, ifm->ifm_media);
2902 }
2903
2904 XL_UNLOCK(sc);
2905
2906 return (0);
2907 }
2908
2909 /*
2910 * Report current media status.
2911 */
2912 static void
xl_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2913 xl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2914 {
2915 struct xl_softc *sc = if_getsoftc(ifp);
2916 u_int32_t icfg;
2917 u_int16_t status = 0;
2918 struct mii_data *mii = NULL;
2919
2920 XL_LOCK(sc);
2921
2922 if (sc->xl_miibus != NULL)
2923 mii = device_get_softc(sc->xl_miibus);
2924
2925 XL_SEL_WIN(4);
2926 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2927
2928 XL_SEL_WIN(3);
2929 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2930 icfg >>= XL_ICFG_CONNECTOR_BITS;
2931
2932 ifmr->ifm_active = IFM_ETHER;
2933 ifmr->ifm_status = IFM_AVALID;
2934
2935 if ((status & XL_MEDIASTAT_CARRIER) == 0)
2936 ifmr->ifm_status |= IFM_ACTIVE;
2937
2938 switch (icfg) {
2939 case XL_XCVR_10BT:
2940 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2941 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2942 ifmr->ifm_active |= IFM_FDX;
2943 else
2944 ifmr->ifm_active |= IFM_HDX;
2945 break;
2946 case XL_XCVR_AUI:
2947 if (sc->xl_type == XL_TYPE_905B &&
2948 sc->xl_media == XL_MEDIAOPT_10FL) {
2949 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2950 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2951 ifmr->ifm_active |= IFM_FDX;
2952 else
2953 ifmr->ifm_active |= IFM_HDX;
2954 } else
2955 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2956 break;
2957 case XL_XCVR_COAX:
2958 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2959 break;
2960 /*
2961 * XXX MII and BTX/AUTO should be separate cases.
2962 */
2963
2964 case XL_XCVR_100BTX:
2965 case XL_XCVR_AUTO:
2966 case XL_XCVR_MII:
2967 if (mii != NULL) {
2968 mii_pollstat(mii);
2969 ifmr->ifm_active = mii->mii_media_active;
2970 ifmr->ifm_status = mii->mii_media_status;
2971 }
2972 break;
2973 case XL_XCVR_100BFX:
2974 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2975 break;
2976 default:
2977 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
2978 break;
2979 }
2980
2981 XL_UNLOCK(sc);
2982 }
2983
2984 static int
xl_ioctl(if_t ifp,u_long command,caddr_t data)2985 xl_ioctl(if_t ifp, u_long command, caddr_t data)
2986 {
2987 struct xl_softc *sc = if_getsoftc(ifp);
2988 struct ifreq *ifr = (struct ifreq *) data;
2989 int error = 0, mask;
2990 struct mii_data *mii = NULL;
2991
2992 switch (command) {
2993 case SIOCSIFFLAGS:
2994 XL_LOCK(sc);
2995 if (if_getflags(ifp) & IFF_UP) {
2996 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
2997 (if_getflags(ifp) ^ sc->xl_if_flags) &
2998 (IFF_PROMISC | IFF_ALLMULTI))
2999 xl_rxfilter(sc);
3000 else
3001 xl_init_locked(sc);
3002 } else {
3003 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3004 xl_stop(sc);
3005 }
3006 sc->xl_if_flags = if_getflags(ifp);
3007 XL_UNLOCK(sc);
3008 break;
3009 case SIOCADDMULTI:
3010 case SIOCDELMULTI:
3011 /* XXX Downcall from if_addmulti() possibly with locks held. */
3012 XL_LOCK(sc);
3013 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3014 xl_rxfilter(sc);
3015 XL_UNLOCK(sc);
3016 break;
3017 case SIOCGIFMEDIA:
3018 case SIOCSIFMEDIA:
3019 if (sc->xl_miibus != NULL)
3020 mii = device_get_softc(sc->xl_miibus);
3021 if (mii == NULL)
3022 error = ifmedia_ioctl(ifp, ifr,
3023 &sc->ifmedia, command);
3024 else
3025 error = ifmedia_ioctl(ifp, ifr,
3026 &mii->mii_media, command);
3027 break;
3028 case SIOCSIFCAP:
3029 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3030 #ifdef DEVICE_POLLING
3031 if ((mask & IFCAP_POLLING) != 0 &&
3032 (if_getcapabilities(ifp) & IFCAP_POLLING) != 0) {
3033 if_togglecapenable(ifp, IFCAP_POLLING);
3034 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) {
3035 error = ether_poll_register(xl_poll, ifp);
3036 if (error)
3037 break;
3038 XL_LOCK(sc);
3039 /* Disable interrupts */
3040 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3041 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
3042 XL_UNLOCK(sc);
3043 } else {
3044 error = ether_poll_deregister(ifp);
3045 /* Enable interrupts. */
3046 XL_LOCK(sc);
3047 CSR_WRITE_2(sc, XL_COMMAND,
3048 XL_CMD_INTR_ACK | 0xFF);
3049 CSR_WRITE_2(sc, XL_COMMAND,
3050 XL_CMD_INTR_ENB | XL_INTRS);
3051 if (sc->xl_flags & XL_FLAG_FUNCREG)
3052 bus_space_write_4(sc->xl_ftag,
3053 sc->xl_fhandle, 4, 0x8000);
3054 XL_UNLOCK(sc);
3055 }
3056 }
3057 #endif /* DEVICE_POLLING */
3058 XL_LOCK(sc);
3059 if ((mask & IFCAP_TXCSUM) != 0 &&
3060 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
3061 if_togglecapenable(ifp, IFCAP_TXCSUM);
3062 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
3063 if_sethwassistbits(ifp, XL905B_CSUM_FEATURES, 0);
3064 else
3065 if_sethwassistbits(ifp, 0, XL905B_CSUM_FEATURES);
3066 }
3067 if ((mask & IFCAP_RXCSUM) != 0 &&
3068 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
3069 if_togglecapenable(ifp, IFCAP_RXCSUM);
3070 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3071 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
3072 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
3073 XL_UNLOCK(sc);
3074 break;
3075 default:
3076 error = ether_ioctl(ifp, command, data);
3077 break;
3078 }
3079
3080 return (error);
3081 }
3082
3083 static int
xl_watchdog(struct xl_softc * sc)3084 xl_watchdog(struct xl_softc *sc)
3085 {
3086 if_t ifp = sc->xl_ifp;
3087 u_int16_t status = 0;
3088 int misintr;
3089
3090 XL_LOCK_ASSERT(sc);
3091
3092 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3093 return (0);
3094
3095 xl_rxeof(sc);
3096 xl_txeoc(sc);
3097 misintr = 0;
3098 if (sc->xl_type == XL_TYPE_905B) {
3099 xl_txeof_90xB(sc);
3100 if (sc->xl_cdata.xl_tx_cnt == 0)
3101 misintr++;
3102 } else {
3103 xl_txeof(sc);
3104 if (sc->xl_cdata.xl_tx_head == NULL)
3105 misintr++;
3106 }
3107 if (misintr != 0) {
3108 device_printf(sc->xl_dev,
3109 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3110 return (0);
3111 }
3112
3113 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3114 XL_SEL_WIN(4);
3115 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3116 device_printf(sc->xl_dev, "watchdog timeout\n");
3117
3118 if (status & XL_MEDIASTAT_CARRIER)
3119 device_printf(sc->xl_dev,
3120 "no carrier - transceiver cable problem?\n");
3121
3122 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3123 xl_init_locked(sc);
3124
3125 if (!if_sendq_empty(ifp)) {
3126 if (sc->xl_type == XL_TYPE_905B)
3127 xl_start_90xB_locked(ifp);
3128 else
3129 xl_start_locked(ifp);
3130 }
3131
3132 return (EJUSTRETURN);
3133 }
3134
3135 /*
3136 * Stop the adapter and free any mbufs allocated to the
3137 * RX and TX lists.
3138 */
3139 static void
xl_stop(struct xl_softc * sc)3140 xl_stop(struct xl_softc *sc)
3141 {
3142 int i;
3143 if_t ifp = sc->xl_ifp;
3144
3145 XL_LOCK_ASSERT(sc);
3146
3147 sc->xl_wdog_timer = 0;
3148
3149 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3152 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3153 xl_wait(sc);
3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3156 DELAY(800);
3157
3158 #ifdef foo
3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3160 xl_wait(sc);
3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3162 xl_wait(sc);
3163 #endif
3164
3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3168 if (sc->xl_flags & XL_FLAG_FUNCREG)
3169 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3170
3171 /* Stop the stats updater. */
3172 callout_stop(&sc->xl_tick_callout);
3173
3174 /*
3175 * Free data in the RX lists.
3176 */
3177 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3178 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3179 bus_dmamap_unload(sc->xl_mtag,
3180 sc->xl_cdata.xl_rx_chain[i].xl_map);
3181 bus_dmamap_destroy(sc->xl_mtag,
3182 sc->xl_cdata.xl_rx_chain[i].xl_map);
3183 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3184 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3185 }
3186 }
3187 if (sc->xl_ldata.xl_rx_list != NULL)
3188 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3189 /*
3190 * Free the TX list buffers.
3191 */
3192 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3193 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3194 bus_dmamap_unload(sc->xl_mtag,
3195 sc->xl_cdata.xl_tx_chain[i].xl_map);
3196 bus_dmamap_destroy(sc->xl_mtag,
3197 sc->xl_cdata.xl_tx_chain[i].xl_map);
3198 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3199 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3200 }
3201 }
3202 if (sc->xl_ldata.xl_tx_list != NULL)
3203 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3204
3205 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
3206 }
3207
3208 /*
3209 * Stop all chip I/O so that the kernel's probe routines don't
3210 * get confused by errant DMAs when rebooting.
3211 */
3212 static int
xl_shutdown(device_t dev)3213 xl_shutdown(device_t dev)
3214 {
3215
3216 return (xl_suspend(dev));
3217 }
3218
3219 static int
xl_suspend(device_t dev)3220 xl_suspend(device_t dev)
3221 {
3222 struct xl_softc *sc;
3223
3224 sc = device_get_softc(dev);
3225
3226 XL_LOCK(sc);
3227 xl_stop(sc);
3228 xl_setwol(sc);
3229 XL_UNLOCK(sc);
3230
3231 return (0);
3232 }
3233
3234 static int
xl_resume(device_t dev)3235 xl_resume(device_t dev)
3236 {
3237 struct xl_softc *sc;
3238 if_t ifp;
3239
3240 sc = device_get_softc(dev);
3241 ifp = sc->xl_ifp;
3242
3243 XL_LOCK(sc);
3244
3245 if (if_getflags(ifp) & IFF_UP) {
3246 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3247 xl_init_locked(sc);
3248 }
3249
3250 XL_UNLOCK(sc);
3251
3252 return (0);
3253 }
3254
3255 static void
xl_setwol(struct xl_softc * sc)3256 xl_setwol(struct xl_softc *sc)
3257 {
3258 if_t ifp;
3259 u_int16_t cfg, pmstat;
3260
3261 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3262 return;
3263
3264 ifp = sc->xl_ifp;
3265 XL_SEL_WIN(7);
3266 /* Clear any pending PME events. */
3267 CSR_READ_2(sc, XL_W7_BM_PME);
3268 cfg = 0;
3269 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
3270 cfg |= XL_BM_PME_MAGIC;
3271 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3272 /* Enable RX. */
3273 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3275 /* Request PME. */
3276 pmstat = pci_read_config(sc->xl_dev,
3277 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3278 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
3279 pmstat |= PCIM_PSTAT_PMEENABLE;
3280 else
3281 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3282 pci_write_config(sc->xl_dev,
3283 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);
3284 }
3285