1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright (c) 2018, Joyent, Inc. 14 * Copyright (c) 2019 by Western Digital Corporation 15 * Copyright 2024 Oxide Computer Company 16 */ 17 18 #ifndef _SYS_USB_XHCI_XHCI_H 19 #define _SYS_USB_XHCI_XHCI_H 20 21 /* 22 * Extensible Host Controller Interface (xHCI) USB Driver 23 */ 24 25 #include <sys/conf.h> 26 #include <sys/ddi.h> 27 #include <sys/sunddi.h> 28 #include <sys/taskq_impl.h> 29 #include <sys/sysmacros.h> 30 #include <sys/usb/hcd/xhci/xhcireg.h> 31 32 #include <sys/usb/usba.h> 33 #include <sys/usb/usba/hcdi.h> 34 #include <sys/usb/hubd/hub.h> 35 #include <sys/usb/usba/hubdi.h> 36 #include <sys/usb/hubd/hubdvar.h> 37 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * The base segment for DMA attributes was determined to be 4k based on xHCI 1.1 45 * / table 54: Data Structure Max Size, Boundary, and Alignment Requirement 46 * Summary. This indicates that the required alignment for most things is 47 * PAGESIZE, which in our current implementation is required to be 4K. We 48 * provide the ring segment value below for the things which need 64K alignment 49 * 50 * Similarly, in the same table, the maximum required alignment is 64 bytes, 51 * hence we use that for everything. 52 * 53 * Next is the scatter/gather lengths. For most of the data structures, we only 54 * want to have a single SGL entry, e.g. just a simple flat mapping. For many of 55 * our transfers, we use the same logic to simplify the implementation of the 56 * driver. However, for bulk transfers, which are the largest by far, we want to 57 * be able to leverage SGLs to give us more DMA flexibility. 58 * 59 * We can transfer up to 64K in one transfer request block (TRB) which 60 * corresponds to a single SGL entry. Each ring we create is a single page in 61 * size and will support at most 256 TRBs. To try and give the operating system 62 * flexibility when allocating DMA transfers, we've opted to allow up to 63 63 * SGLs. Because there isn't a good way to support DMA windows with the xHCI 64 * controller design, if this number is too small then DMA allocations and 65 * binding might fail. If the DMA binding fails, the transfer will fail. 66 * 67 * The reason that we use 63 SGLs and not the expected 64 is that we always need 68 * to allocate an additional TRB for the event data. This leaves us with a 69 * nicely divisible number of entries. 70 * 71 * The final piece of this is the maximum sized transfer that the driver 72 * advertises to the broader framework. This is currently sized at 512 KiB. For 73 * reference the ehci driver sized this value at 640 KiB. It's important to 74 * understand that this isn't reflected in the DMA attribute limitation, because 75 * it's not an attribute of the hardware. Experimentally, this has proven to be 76 * sufficient for most of the drivers that we support today. When considering 77 * increasing this number, please note the impact that might have on the 78 * required number of DMA SGL entries required to satisfy the allocation. 79 * 80 * The value of 512 KiB was originally based on the number of SGLs we supported 81 * multiplied by the maximum transfer size. The original number of 82 * XHCI_TRANSFER_DMA_SGL was 8. The 512 KiB value was based upon taking the 83 * number of SGLs and assuming that each TRB used its maximum transfer size of 84 * 64 KiB. 85 */ 86 #define XHCI_TRB_MAX_TRANSFER 65536 /* 64 KiB */ 87 #define XHCI_DMA_ALIGN 64 88 #define XHCI_DEF_DMA_SGL 1 89 #define XHCI_TRANSFER_DMA_SGL 63 90 #define XHCI_MAX_TRANSFER 524288 /* 512 KiB */ 91 92 /* 93 * Properties and values for rerouting ehci ports to xhci. 94 */ 95 #define XHCI_PROP_REROUTE_DISABLE 0 96 #define XHCI_PROP_REROUTE_DEFAULT 1 97 98 /* 99 * This number is a bit made up. Truthfully, the API here isn't the most useful 100 * for what we need to define as it should really be based on the endpoint that 101 * we're interested in rather than the device as a whole. 102 * 103 * We're basically being asked how many TRBs we're willing to schedule in one 104 * go. There's no great way to come up with this number, so we basically are 105 * making up something such that we use up a good portion of a ring, but not too 106 * much of it. 107 */ 108 #define XHCI_ISOC_MAX_TRB 64 109 110 #ifdef DEBUG 111 #define XHCI_DMA_SYNC(dma, flag) VERIFY0(ddi_dma_sync( \ 112 (dma).xdb_dma_handle, 0, 0, \ 113 (flag))) 114 #else 115 #define XHCI_DMA_SYNC(dma, flag) ((void) ddi_dma_sync( \ 116 (dma).xdb_dma_handle, 0, 0, \ 117 (flag))) 118 #endif 119 120 /* 121 * TRBs need to indicate the number of remaining USB packets in the overall 122 * transfer. This is a 5-bit value, which means that the maximum value we can 123 * store in that TRD field is 31. 124 */ 125 #define XHCI_MAX_TDSIZE 31 126 127 /* 128 * This defines a time in 2-ms ticks that is required to wait for the controller 129 * to be ready to go. Section 5.4.8 of the XHCI specification in the description 130 * of the PORTSC register indicates that the upper bound is 20 ms. Therefore the 131 * number of ticks is 10. 132 */ 133 #define XHCI_POWER_GOOD 10 134 135 /* 136 * Definitions to determine the default number of interrupts. Note that we only 137 * bother with a single interrupt at this time, though we've arranged the driver 138 * to make it possible to request more if, for some unlikely reason, it becomes 139 * necessary. 140 */ 141 #define XHCI_NINTR 1 142 143 /* 144 * Default interrupt modulation value. This enables us to have 4000 interrupts / 145 * second. This is supposed to be the default value of the controller. See xHCI 146 * 1.1 / 4.17.2 for more information. 147 */ 148 #define XHCI_IMOD_DEFAULT 0x000003F8U 149 150 /* 151 * Definitions that surround the default values used in various contexts. These 152 * come from various parts of the xHCI specification. In general, see xHCI 1.1 / 153 * 4.8.2. Note that the MPS_MASK is used for ISOCH and INTR endpoints which have 154 * different sizes. 155 * 156 * The burst member is a bit more complicated. By default for USB 2 devices, it 157 * only matters for ISOCH and INTR endpoints and so we use the macros below to 158 * pull it out of the endpoint description's max packet field. For USB 3, it 159 * matters for non-control endpoints. However, it comes out of a companion 160 * description. 161 * 162 * By default the mult member is zero for all cases except for super speed 163 * ISOCH endpoints, where it comes from the companion descriptor. 164 */ 165 #define XHCI_CONTEXT_DEF_CERR 3 166 #define XHCI_CONTEXT_ISOCH_CERR 0 167 #define XHCI_CONTEXT_MPS_MASK 0x07ff 168 #define XHCI_CONTEXT_BURST_MASK 0x1800 169 #define XHCI_CONTEXT_BURST_SHIFT 11 170 #define XHCI_CONTEXT_DEF_MULT 0 171 #define XHCI_CONTEXT_DEF_MAX_ESIT 0 172 #define XHCI_CONTEXT_DEF_CTRL_ATL 8 173 174 /* 175 * This number represents the number of transfers that we'll set up for a given 176 * interrupt transfer. Note that the idea here is that we'll want to allocate a 177 * certain number of transfers to basically ensure that we'll always be able to 178 * have a transfer available, even if the system is a bit caught up in trying to 179 * process it and for some reason we can't fire the interrupt. As such, we 180 * basically want to have enough available that at the fastest interval (125 us) 181 * that we have enough. So in this case we choose 8, with the assumption that we 182 * should be able to process at least one in a given millisecond. Note that this 183 * is not based in fact and is really just as much a guess and a hope. 184 * 185 * While we could then use less resources for other interrupt transfers that are 186 * slower, starting with uniform resource usage will make things a bit easier. 187 */ 188 #define XHCI_INTR_IN_NTRANSFERS 8 189 190 /* 191 * This number represents the number of xhci_transfer_t structures that we'll 192 * set up for a given isochronous transfer polling request. A given isochronous 193 * transfer may actually have multiple units of time associated with it. As 194 * such, we basically want to treat this like a case of classic double 195 * buffering. We have one ready to go while the other is being filled up. This 196 * will compensate for additional latency in the system. This is smaller than 197 * the Interrupt IN transfer case above as many callers may ask for multiple 198 * intervals in a single request. 199 */ 200 #define XHCI_ISOC_IN_NTRANSFERS 2 201 202 #define XHCI_PERIODIC_IN_NTRANSFERS \ 203 MAX(XHCI_ISOC_IN_NTRANSFERS, XHCI_INTR_IN_NTRANSFERS) 204 205 /* 206 * Mask for a route string which is a 20-bit value. 207 */ 208 #define XHCI_ROUTE_MASK(x) ((x) & 0xfffff) 209 210 /* 211 * This is the default tick that we use for timeouts while endpoints have 212 * outstanding, active, non-periodic transfers. We choose one second as the USBA 213 * specifies timeouts in units of seconds. Note that this is in microseconds, so 214 * it can be fed into drv_usectohz(). 215 */ 216 #define XHCI_TICK_TIMEOUT_US (MICROSEC) 217 218 /* 219 * Set of bits that we need one of to indicate that this port has something 220 * interesting on it. 221 */ 222 #define XHCI_HUB_INTR_CHANGE_MASK (XHCI_PS_CSC | XHCI_PS_PEC | \ 223 XHCI_PS_WRC | XHCI_PS_OCC | XHCI_PS_PRC | XHCI_PS_PLC | XHCI_PS_CEC) 224 225 /* 226 * These represent known issues with various xHCI controllers. 227 * 228 * XHCI_QUIRK_NO_MSI MSI support on this controller is known to be 229 * broken. 230 * 231 * XHCI_QUIRK_32_ONLY Only use 32-bit DMA addreses with this 232 * controller. 233 * 234 * XHCI_QUIRK_INTC_EHCI This is an Intel platform which supports 235 * rerouting ports between EHCI and xHCI 236 * controllers on the platform. 237 */ 238 typedef enum xhci_quirk { 239 XHCI_QUIRK_NO_MSI = 0x01, 240 XHCI_QUIRK_32_ONLY = 0x02, 241 XHCI_QUIRK_INTC_EHCI = 0x04 242 } xhci_quirk_t; 243 244 /* 245 * xHCI capability parameter flags. These are documented in xHCI 1.1 / 5.3.6. 246 */ 247 typedef enum xhci_cap_flags { 248 XCAP_AC64 = 0x001, 249 XCAP_BNC = 0x002, 250 XCAP_CSZ = 0x004, 251 XCAP_PPC = 0x008, 252 XCAP_PIND = 0x010, 253 XCAP_LHRC = 0x020, 254 XCAP_LTC = 0x040, 255 XCAP_NSS = 0x080, 256 XCAP_PAE = 0x100, 257 XCAP_SPC = 0x200, 258 XCAP_SEC = 0x400, 259 XCAP_CFC = 0x800 260 } xchi_cap_flags_t; 261 262 /* 263 * Second set of capabilities, these are documented in xHCI 1.1 / 5.3.9. 264 */ 265 typedef enum xhci_cap2_flags { 266 XCAP2_U3C = 0x01, 267 XCAP2_CMC = 0x02, 268 XCAP2_FMC = 0x04, 269 XCAP2_CTC = 0x08, 270 XCAP2_LEC = 0x10, 271 XCAP2_CIC = 0x20 272 } xhci_cap2_flags_t; 273 274 /* 275 * These represent and store the various capability registers that we'll need to 276 * use. In addition, we stash a few other versioning related bits here. Note 277 * that we cache more information than we might need so that we have it for 278 * debugging purposes. 279 */ 280 typedef struct xhci_capability { 281 uint8_t xcap_usb_vers; 282 uint16_t xcap_hci_vers; 283 uint32_t xcap_pagesize; 284 uint8_t xcap_max_slots; 285 uint16_t xcap_max_intrs; 286 uint8_t xcap_max_ports; 287 boolean_t xcap_ist_micro; 288 uint8_t xcap_ist; 289 uint16_t xcap_max_esrt; 290 boolean_t xcap_scratch_restore; 291 uint16_t xcap_max_scratch; 292 uint8_t xcap_u1_lat; 293 uint16_t xcap_u2_lat; 294 xchi_cap_flags_t xcap_flags; 295 uint8_t xcap_max_psa; 296 uint16_t xcap_xecp_off; 297 xhci_cap2_flags_t xcap_flags2; 298 int xcap_intr_types; 299 } xhci_capability_t; 300 301 /* 302 * This represents a single logical DMA allocation. For the vast majority of 303 * non-transfer cases, it only represents a single DMA buffer and not a 304 * scatter-gather list. 305 */ 306 typedef struct xhci_dma_buffer { 307 caddr_t xdb_va; /* Buffer VA */ 308 size_t xdb_len; /* Buffer logical len */ 309 ddi_acc_handle_t xdb_acc_handle; /* Access handle */ 310 ddi_dma_handle_t xdb_dma_handle; /* DMA handle */ 311 int xdb_ncookies; /* Number of actual cookies */ 312 ddi_dma_cookie_t xdb_cookies[XHCI_TRANSFER_DMA_SGL]; 313 } xhci_dma_buffer_t; 314 315 /* 316 * This is a single transfer descriptor. It's packed to match the hardware 317 * layout. 318 */ 319 #pragma pack(1) 320 typedef struct xhci_trb { 321 uint64_t trb_addr; 322 uint32_t trb_status; 323 uint32_t trb_flags; 324 } xhci_trb_t; 325 #pragma pack() 326 327 /* 328 * This represents a single transfer that we want to allocate and perform. 329 */ 330 typedef struct xhci_transfer { 331 list_node_t xt_link; 332 hrtime_t xt_sched_time; 333 xhci_dma_buffer_t xt_buffer; 334 uint_t xt_ntrbs; 335 uint_t xt_short; 336 uint_t xt_timeout; 337 usb_cr_t xt_cr; 338 boolean_t xt_data_tohost; 339 xhci_trb_t *xt_trbs; 340 uint64_t *xt_trbs_pa; 341 usb_isoc_pkt_descr_t *xt_isoc; 342 usb_opaque_t xt_usba_req; 343 } xhci_transfer_t; 344 345 /* 346 * A transfer on a periodic endpoint does not generally have an associated USB 347 * request, except in the case of a oneshot Interrupt IN transfer. 348 */ 349 #define XHCI_IS_ONESHOT_XFER(xt) ((xt)->xt_usba_req != NULL) 350 351 /* 352 * This represents a ring in xHCI, upon which event, transfer, and command TRBs 353 * are scheduled. 354 */ 355 typedef struct xhci_ring { 356 xhci_dma_buffer_t xr_dma; 357 uint_t xr_ntrb; 358 xhci_trb_t *xr_trb; 359 uint_t xr_head; 360 uint_t xr_tail; 361 uint8_t xr_cycle; 362 } xhci_ring_t; 363 364 /* 365 * This structure is used to represent the xHCI Device Context Base Address 366 * Array. It's defined in section 6.1 of the specification and is required for 367 * the controller to start. 368 * 369 * The maximum number of slots supported is always 256, therefore we size this 370 * structure at its maximum. 371 */ 372 #define XHCI_MAX_SLOTS 256 373 #define XHCI_DCBAA_SCRATCHPAD_INDEX 0 374 375 typedef struct xhci_dcbaa { 376 uint64_t *xdc_base_addrs; 377 xhci_dma_buffer_t xdc_dma; 378 } xhci_dcbaa_t; 379 380 typedef struct xhci_scratchpad { 381 uint64_t *xsp_addrs; 382 xhci_dma_buffer_t xsp_addr_dma; 383 xhci_dma_buffer_t *xsp_scratch_dma; 384 } xhci_scratchpad_t; 385 386 /* 387 * Contexts. These structures are inserted into the DCBAA above and are used for 388 * describing the state of the system. Note, that while many of these are 389 * 32-bytes in size, the xHCI specification defines that they'll be extended to 390 * 64-bytes with all the extra bytes as zeros if the CSZ flag is set in the 391 * HCCPARAMS1 register, e.g. we have the flag XCAP_CSZ set. 392 * 393 * The device context covers the slot context and 31 endpoints. 394 */ 395 #define XHCI_DEVICE_CONTEXT_32 1024 396 #define XHCI_DEVICE_CONTEXT_64 2048 397 #define XHCI_NUM_ENDPOINTS 31 398 #define XHCI_DEFAULT_ENDPOINT 0 399 400 #pragma pack(1) 401 typedef struct xhci_slot_context { 402 uint32_t xsc_info; 403 uint32_t xsc_info2; 404 uint32_t xsc_tt; 405 uint32_t xsc_state; 406 uint32_t xsc_reserved[4]; 407 } xhci_slot_context_t; 408 409 typedef struct xhci_endpoint_context { 410 uint32_t xec_info; 411 uint32_t xec_info2; 412 uint64_t xec_dequeue; 413 uint32_t xec_txinfo; 414 uint32_t xec_reserved[3]; 415 } xhci_endpoint_context_t; 416 417 typedef struct xhci_input_context { 418 uint32_t xic_drop_flags; 419 uint32_t xic_add_flags; 420 uint32_t xic_reserved[6]; 421 } xhci_input_context_t; 422 #pragma pack() 423 424 /* 425 * Definitions and structures for maintaining the event ring. 426 */ 427 #define XHCI_EVENT_NSEGS 1 428 429 #pragma pack(1) 430 typedef struct xhci_event_segment { 431 uint64_t xes_addr; 432 uint16_t xes_size; 433 uint16_t xes_rsvd0; 434 uint32_t xes_rsvd1; 435 } xhci_event_segment_t; 436 #pragma pack() 437 438 typedef struct xhci_event_ring { 439 xhci_event_segment_t *xev_segs; 440 xhci_dma_buffer_t xev_dma; 441 xhci_ring_t xev_ring; 442 } xhci_event_ring_t; 443 444 typedef enum xhci_command_ring_state { 445 XHCI_COMMAND_RING_IDLE = 0x00, 446 XHCI_COMMAND_RING_RUNNING = 0x01, 447 XHCI_COMMAND_RING_ABORTING = 0x02, 448 XHCI_COMMAND_RING_ABORT_DONE = 0x03 449 } xhci_command_ring_state_t; 450 451 typedef struct xhci_command_ring { 452 xhci_ring_t xcr_ring; 453 kmutex_t xcr_lock; 454 kcondvar_t xcr_cv; 455 list_t xcr_commands; 456 timeout_id_t xcr_timeout; 457 xhci_command_ring_state_t xcr_state; 458 } xhci_command_ring_t; 459 460 /* 461 * Individual command states. 462 * 463 * XHCI_COMMAND_S_INIT The command has yet to be inserted into the 464 * command ring. 465 * 466 * XHCI_COMMAND_S_QUEUED The command is queued in the command ring. 467 * 468 * XHCI_COMMAND_S_RECEIVED A command completion for this was received. 469 * 470 * XHCI_COMMAND_S_DONE The command has been executed. Note that it may 471 * have been aborted. 472 * 473 * XHCI_COMMAND_S_RESET The ring is being reset due to a fatal error and 474 * this command has been removed from the ring. 475 * This means it has been aborted, but it was not 476 * the cause of the abort. 477 * 478 * Note, when adding states, anything after XHCI_COMMAND_S_DONE implies that 479 * upon reaching this state, it is no longer in the ring. 480 */ 481 typedef enum xhci_command_state { 482 XHCI_COMMAND_S_INIT = 0x00, 483 XHCI_COMMAND_S_QUEUED = 0x01, 484 XHCI_COMMAND_S_RECEIVED = 0x02, 485 XHCI_COMMAND_S_DONE = 0x03, 486 XHCI_COMMAND_S_RESET = 0x04 487 } xhci_command_state_t; 488 489 /* 490 * The TRB contents here are always kept in host byte order and are transformed 491 * to little endian when actually scheduled on the ring. 492 */ 493 typedef struct xhci_command { 494 list_node_t xco_link; 495 kcondvar_t xco_cv; 496 xhci_trb_t xco_req; 497 xhci_trb_t xco_res; 498 xhci_command_state_t xco_state; 499 } xhci_command_t; 500 501 typedef enum xhci_endpoint_state { 502 XHCI_ENDPOINT_PERIODIC = 0x01, 503 XHCI_ENDPOINT_HALTED = 0x02, 504 XHCI_ENDPOINT_QUIESCE = 0x04, 505 XHCI_ENDPOINT_TIMED_OUT = 0x08, 506 /* 507 * This enpdoint is being torn down and should make sure it de-schedules 508 * itself. 509 */ 510 XHCI_ENDPOINT_TEARDOWN = 0x10, 511 /* 512 * This endpoint is currently used in polled I/O mode by the 513 * kernel debugger. 514 */ 515 XHCI_ENDPOINT_POLLED = 0x20, 516 /* 517 * This endpoint is open and in use by a pipe. 518 */ 519 XHCI_ENDPOINT_OPEN = 0x40, 520 } xhci_endpoint_state_t; 521 522 /* 523 * This is a composite of states that we need to watch for. We don't 524 * want to allow ourselves to set one of these flags while one of them 525 * is currently active. 526 */ 527 #define XHCI_ENDPOINT_SERIALIZE (XHCI_ENDPOINT_QUIESCE | \ 528 XHCI_ENDPOINT_TIMED_OUT) 529 530 /* 531 * This is a composite of states that we need to make sure that if set, we do 532 * not schedule activity on the ring. 533 */ 534 #define XHCI_ENDPOINT_DONT_SCHEDULE (XHCI_ENDPOINT_HALTED | \ 535 XHCI_ENDPOINT_QUIESCE | \ 536 XHCI_ENDPOINT_TIMED_OUT) 537 538 /* 539 * Forwards required for the endpoint 540 */ 541 struct xhci_device; 542 struct xhci; 543 544 typedef struct xhci_endpoint_params { 545 boolean_t xepp_configured; 546 uint_t xepp_eptype; 547 uint_t xepp_burst; 548 uint_t xepp_ival; 549 uint_t xepp_max_esit; 550 uint_t xepp_avgtrb; 551 uint_t xepp_mps; 552 uint_t xepp_mult; 553 uint_t xepp_cerr; 554 } xhci_endpoint_params_t; 555 556 typedef struct xhci_endpoint { 557 struct xhci *xep_xhci; 558 struct xhci_device *xep_xd; 559 uint_t xep_num; 560 uint_t xep_type; 561 xhci_endpoint_state_t xep_state; 562 kcondvar_t xep_state_cv; 563 timeout_id_t xep_timeout; 564 list_t xep_transfers; 565 usba_pipe_handle_data_t *xep_pipe; 566 xhci_ring_t xep_ring; 567 xhci_endpoint_params_t xep_params; 568 } xhci_endpoint_t; 569 570 typedef struct xhci_device { 571 list_node_t xd_link; 572 usb_port_t xd_port; 573 uint8_t xd_slot; 574 boolean_t xd_addressed; 575 usba_device_t *xd_usbdev; 576 xhci_dma_buffer_t xd_ictx; 577 kmutex_t xd_imtx; /* Protects input contexts */ 578 xhci_input_context_t *xd_input; 579 xhci_slot_context_t *xd_slotin; 580 xhci_endpoint_context_t *xd_endin[XHCI_NUM_ENDPOINTS]; 581 xhci_dma_buffer_t xd_octx; 582 xhci_slot_context_t *xd_slotout; 583 xhci_endpoint_context_t *xd_endout[XHCI_NUM_ENDPOINTS]; 584 xhci_endpoint_t *xd_endpoints[XHCI_NUM_ENDPOINTS]; 585 } xhci_device_t; 586 587 typedef enum xhci_periodic_state { 588 XHCI_PERIODIC_POLL_IDLE = 0x0, 589 XHCI_PERIODIC_POLL_ACTIVE, 590 XHCI_PERIODIC_POLL_NOMEM, 591 XHCI_PERIODIC_POLL_STOPPING 592 } xhci_periodic_state_t; 593 594 typedef struct xhci_periodic_pipe { 595 xhci_periodic_state_t xpp_poll_state; 596 usb_opaque_t xpp_usb_req; 597 size_t xpp_tsize; 598 uint_t xpp_ntransfers; 599 xhci_transfer_t *xpp_transfers[XHCI_PERIODIC_IN_NTRANSFERS]; 600 } xhci_periodic_pipe_t; 601 602 typedef struct xhci_pipe { 603 list_node_t xp_link; 604 hrtime_t xp_opentime; 605 usba_pipe_handle_data_t *xp_pipe; 606 xhci_endpoint_t *xp_ep; 607 xhci_periodic_pipe_t xp_periodic; 608 } xhci_pipe_t; 609 610 typedef struct xhci_usba { 611 usba_hcdi_ops_t *xa_ops; 612 ddi_dma_attr_t xa_dma_attr; 613 usb_dev_descr_t xa_dev_descr; 614 usb_ss_hub_descr_t xa_hub_descr; 615 usba_pipe_handle_data_t *xa_intr_cb_ph; 616 usb_intr_req_t *xa_intr_cb_req; 617 list_t xa_devices; 618 list_t xa_pipes; 619 } xhci_usba_t; 620 621 typedef enum xhci_attach_seq { 622 XHCI_ATTACH_FM = 0x1 << 0, 623 XHCI_ATTACH_PCI_CONFIG = 0x1 << 1, 624 XHCI_ATTACH_REGS_MAP = 0x1 << 2, 625 XHCI_ATTACH_INTR_ALLOC = 0x1 << 3, 626 XHCI_ATTACH_INTR_ADD = 0x1 << 4, 627 XHCI_ATTACH_SYNCH = 0x1 << 5, 628 XHCI_ATTACH_INTR_ENABLE = 0x1 << 6, 629 XHCI_ATTACH_STARTED = 0x1 << 7, 630 XHCI_ATTACH_USBA = 0x1 << 8, 631 XHCI_ATTACH_ROOT_HUB = 0x1 << 9 632 } xhci_attach_seq_t; 633 634 typedef enum xhci_state_flags { 635 XHCI_S_ERROR = 0x1 << 0 636 } xhci_state_flags_t; 637 638 typedef struct xhci { 639 dev_info_t *xhci_dip; 640 xhci_attach_seq_t xhci_seq; 641 int xhci_fm_caps; 642 ddi_acc_handle_t xhci_cfg_handle; 643 uint16_t xhci_vendor_id; 644 uint16_t xhci_device_id; 645 caddr_t xhci_regs_base; 646 ddi_acc_handle_t xhci_regs_handle; 647 uint_t xhci_regs_capoff; 648 uint_t xhci_regs_operoff; 649 uint_t xhci_regs_runoff; 650 uint_t xhci_regs_dooroff; 651 xhci_capability_t xhci_caps; 652 xhci_quirk_t xhci_quirks; 653 ddi_intr_handle_t xhci_intr_hdl; 654 int xhci_intr_num; 655 int xhci_intr_type; 656 uint_t xhci_intr_pri; 657 int xhci_intr_caps; 658 xhci_dcbaa_t xhci_dcbaa; 659 xhci_scratchpad_t xhci_scratchpad; 660 xhci_command_ring_t xhci_command; 661 xhci_event_ring_t xhci_event; 662 taskq_ent_t xhci_tqe; 663 kmutex_t xhci_lock; 664 kcondvar_t xhci_statecv; 665 xhci_state_flags_t xhci_state; 666 xhci_usba_t xhci_usba; 667 } xhci_t; 668 669 /* 670 * The xHCI memory mapped registers come in four different categories. The 671 * offset to them is variable. These represent the given register set that we're 672 * after. 673 */ 674 typedef enum xhci_reg_type { 675 XHCI_R_CAP, 676 XHCI_R_OPER, 677 XHCI_R_RUN, 678 XHCI_R_DOOR 679 } xhci_reg_type_t; 680 681 /* 682 * Polled I/O data structure 683 */ 684 typedef struct xhci_polled { 685 /* 686 * Pointer to the xhcip structure for the device that is to be 687 * used as input in polled mode. 688 */ 689 xhci_t *xhci_polled_xhci; 690 691 /* 692 * Pipe handle for the pipe that is to be used as input device 693 * in POLLED mode. 694 */ 695 usba_pipe_handle_data_t *xhci_polled_input_pipe_handle; 696 697 /* Endpoint for the above */ 698 xhci_endpoint_t *xhci_polled_endpoint; 699 700 /* 701 * The buffer that the USB HDI scan codes are copied into. 702 * A USB keyboard will report up to 8 bytes consisting of the 703 * modifier status, a reserved byte and up to 6 key presses. 704 * This buffer is sized to be large enough for one such report. 705 */ 706 uchar_t xhci_polled_buf[8]; 707 708 /* 709 * Track how many times xhci_polled_input_enter() and 710 * xhci_polled_input_exit() have been called so that the host 711 * controller isn't switched back to OS mode prematurely. 712 */ 713 uint_t xhci_polled_entry; 714 715 /* 716 * Remember persistent errors that will prevent us from reading 717 * further input to avoid repeatedly polling to no avail 718 */ 719 int xhci_polled_persistent_error; 720 } xhci_polled_t; 721 722 /* 723 * Helper functions 724 */ 725 extern xhci_t *xhci_hcdi_get_xhcip_from_dev(usba_device_t *); 726 extern xhci_device_t *xhci_device_lookup_by_slot(xhci_t *, int); 727 728 /* 729 * Quirks related functions 730 */ 731 extern void xhci_quirks_populate(xhci_t *); 732 extern void xhci_reroute_intel(xhci_t *); 733 734 /* 735 * Interrupt related functions 736 */ 737 extern uint_t xhci_intr(caddr_t, caddr_t); 738 extern boolean_t xhci_ddi_intr_disable(xhci_t *); 739 extern boolean_t xhci_ddi_intr_enable(xhci_t *); 740 extern int xhci_intr_conf(xhci_t *); 741 742 /* 743 * DMA related functions 744 */ 745 extern int xhci_check_dma_handle(xhci_t *, xhci_dma_buffer_t *); 746 extern void xhci_dma_acc_attr(xhci_t *, ddi_device_acc_attr_t *); 747 extern void xhci_dma_dma_attr(xhci_t *, ddi_dma_attr_t *); 748 extern void xhci_dma_scratchpad_attr(xhci_t *, ddi_dma_attr_t *); 749 extern void xhci_dma_transfer_attr(xhci_t *, ddi_dma_attr_t *, uint_t); 750 extern void xhci_dma_free(xhci_dma_buffer_t *); 751 extern boolean_t xhci_dma_alloc(xhci_t *, xhci_dma_buffer_t *, ddi_dma_attr_t *, 752 ddi_device_acc_attr_t *, boolean_t, size_t, boolean_t); 753 extern uint64_t xhci_dma_pa(xhci_dma_buffer_t *); 754 755 /* 756 * DMA Transfer Ring functions 757 */ 758 extern xhci_transfer_t *xhci_transfer_alloc(xhci_t *, xhci_endpoint_t *, size_t, 759 uint_t, int); 760 extern void xhci_transfer_free(xhci_t *, xhci_transfer_t *); 761 extern void xhci_transfer_copy(xhci_transfer_t *, void *, size_t, boolean_t); 762 extern int xhci_transfer_sync(xhci_t *, xhci_transfer_t *, uint_t); 763 extern void xhci_transfer_trb_fill_data(xhci_endpoint_t *, xhci_transfer_t *, 764 int, boolean_t); 765 extern void xhci_transfer_calculate_isoc(xhci_device_t *, xhci_endpoint_t *, 766 uint_t, uint_t *, uint_t *); 767 768 /* 769 * Context (DCBAA, Scratchpad, Slot) functions 770 */ 771 extern int xhci_context_init(xhci_t *); 772 extern void xhci_context_fini(xhci_t *); 773 extern boolean_t xhci_context_slot_output_init(xhci_t *, xhci_device_t *); 774 extern void xhci_context_slot_output_fini(xhci_t *, xhci_device_t *); 775 776 /* 777 * Command Ring Functions 778 */ 779 extern int xhci_command_ring_init(xhci_t *); 780 extern void xhci_command_ring_fini(xhci_t *); 781 extern boolean_t xhci_command_event_callback(xhci_t *, xhci_trb_t *trb); 782 783 extern void xhci_command_init(xhci_command_t *); 784 extern void xhci_command_fini(xhci_command_t *); 785 786 extern int xhci_command_enable_slot(xhci_t *, uint8_t *); 787 extern int xhci_command_disable_slot(xhci_t *, uint8_t); 788 extern int xhci_command_set_address(xhci_t *, xhci_device_t *, boolean_t); 789 extern int xhci_command_configure_endpoint(xhci_t *, xhci_device_t *); 790 extern int xhci_command_evaluate_context(xhci_t *, xhci_device_t *); 791 extern int xhci_command_reset_endpoint(xhci_t *, xhci_device_t *, 792 xhci_endpoint_t *); 793 extern int xhci_command_set_tr_dequeue(xhci_t *, xhci_device_t *, 794 xhci_endpoint_t *); 795 extern int xhci_command_stop_endpoint(xhci_t *, xhci_device_t *, 796 xhci_endpoint_t *); 797 798 /* 799 * Event Ring Functions 800 */ 801 extern int xhci_event_init(xhci_t *); 802 extern void xhci_event_fini(xhci_t *); 803 extern boolean_t xhci_event_process_trb(xhci_t *, xhci_trb_t *); 804 extern boolean_t xhci_event_process(xhci_t *); 805 806 /* 807 * General Ring functions 808 */ 809 extern void xhci_ring_free(xhci_ring_t *); 810 extern int xhci_ring_reset(xhci_t *, xhci_ring_t *); 811 extern int xhci_ring_alloc(xhci_t *, xhci_ring_t *); 812 813 /* 814 * Event Ring (Consumer) oriented functions. 815 */ 816 extern xhci_trb_t *xhci_ring_event_advance(xhci_ring_t *); 817 818 819 /* 820 * Command and Transfer Ring (Producer) oriented functions. 821 */ 822 extern boolean_t xhci_ring_trb_tail_valid(xhci_ring_t *, uint64_t); 823 extern int xhci_ring_trb_valid_range(xhci_ring_t *, uint64_t, uint_t); 824 825 extern boolean_t xhci_ring_trb_space(xhci_ring_t *, uint_t); 826 extern void xhci_ring_trb_fill(xhci_ring_t *, uint_t, xhci_trb_t *, uint64_t *, 827 boolean_t); 828 extern void xhci_ring_trb_produce(xhci_ring_t *, uint_t); 829 extern boolean_t xhci_ring_trb_consumed(xhci_ring_t *, uint64_t); 830 extern void xhci_ring_trb_put(xhci_ring_t *, xhci_trb_t *); 831 extern void xhci_ring_skip(xhci_ring_t *); 832 extern void xhci_ring_skip_transfer(xhci_ring_t *, xhci_transfer_t *); 833 834 /* 835 * MMIO related functions. Note callers are responsible for checking with FM 836 * after accessing registers. 837 */ 838 extern int xhci_check_regs_acc(xhci_t *); 839 840 extern uint8_t xhci_get8(xhci_t *, xhci_reg_type_t, uintptr_t); 841 extern uint16_t xhci_get16(xhci_t *, xhci_reg_type_t, uintptr_t); 842 extern uint32_t xhci_get32(xhci_t *, xhci_reg_type_t, uintptr_t); 843 extern uint64_t xhci_get64(xhci_t *, xhci_reg_type_t, uintptr_t); 844 845 extern void xhci_put8(xhci_t *, xhci_reg_type_t, uintptr_t, uint8_t); 846 extern void xhci_put16(xhci_t *, xhci_reg_type_t, uintptr_t, uint16_t); 847 extern void xhci_put32(xhci_t *, xhci_reg_type_t, uintptr_t, uint32_t); 848 extern void xhci_put64(xhci_t *, xhci_reg_type_t, uintptr_t, uint64_t); 849 850 /* 851 * Runtime FM related functions 852 */ 853 extern void xhci_fm_runtime_reset(xhci_t *); 854 855 /* 856 * Endpoint related functions 857 */ 858 extern int xhci_endpoint_init(xhci_t *, xhci_device_t *, 859 usba_pipe_handle_data_t *); 860 extern int xhci_endpoint_reinit(xhci_t *, xhci_device_t *, 861 xhci_endpoint_t *, usba_pipe_handle_data_t *); 862 extern void xhci_endpoint_release(xhci_t *, xhci_endpoint_t *); 863 extern void xhci_endpoint_fini(xhci_device_t *, int); 864 extern int xhci_endpoint_update_default(xhci_t *, xhci_device_t *, 865 xhci_endpoint_t *); 866 extern void xhci_endpoint_timeout_cancel(xhci_t *, xhci_endpoint_t *); 867 868 extern int xhci_endpoint_setup_default_context(xhci_t *, xhci_device_t *, 869 xhci_endpoint_t *); 870 871 extern uint_t xhci_endpoint_pipe_to_epid(usba_pipe_handle_data_t *); 872 extern boolean_t xhci_endpoint_is_periodic_in(xhci_endpoint_t *); 873 874 extern void xhci_endpoint_serialize(xhci_t *, xhci_endpoint_t *); 875 extern int xhci_endpoint_quiesce(xhci_t *, xhci_device_t *, xhci_endpoint_t *); 876 extern int xhci_endpoint_schedule(xhci_t *, xhci_device_t *, xhci_endpoint_t *, 877 xhci_transfer_t *, boolean_t); 878 extern int xhci_endpoint_ring(xhci_t *, xhci_device_t *, xhci_endpoint_t *); 879 extern boolean_t xhci_endpoint_transfer_callback(xhci_t *, xhci_trb_t *); 880 881 extern xhci_transfer_t *xhci_endpoint_determine_transfer(xhci_t *, 882 xhci_endpoint_t *, xhci_trb_t *, uint_t *); 883 884 /* 885 * USB Framework related functions 886 */ 887 extern int xhci_hcd_init(xhci_t *); 888 extern void xhci_hcd_fini(xhci_t *); 889 890 /* 891 * Root hub related functions 892 */ 893 extern int xhci_root_hub_init(xhci_t *); 894 extern int xhci_root_hub_fini(xhci_t *); 895 extern int xhci_root_hub_ctrl_req(xhci_t *, usba_pipe_handle_data_t *, 896 usb_ctrl_req_t *); 897 extern void xhci_root_hub_psc_callback(xhci_t *); 898 extern int xhci_root_hub_intr_root_enable(xhci_t *, usba_pipe_handle_data_t *, 899 usb_intr_req_t *); 900 extern void xhci_root_hub_intr_root_disable(xhci_t *); 901 902 /* 903 * Polled I/O functions 904 */ 905 extern int xhci_hcdi_console_input_init(usba_pipe_handle_data_t *, uchar_t **, 906 usb_console_info_impl_t *); 907 extern int xhci_hcdi_console_input_fini(usb_console_info_impl_t *); 908 extern int xhci_hcdi_console_input_enter(usb_console_info_impl_t *); 909 extern int xhci_hcdi_console_read(usb_console_info_impl_t *, uint_t *); 910 extern int xhci_hcdi_console_input_exit(usb_console_info_impl_t *); 911 extern int xhci_hcdi_console_output_init(usba_pipe_handle_data_t *, 912 usb_console_info_impl_t *); 913 extern int xhci_hcdi_console_output_fini(usb_console_info_impl_t *); 914 extern int xhci_hcdi_console_output_enter(usb_console_info_impl_t *); 915 extern int xhci_hcdi_console_write(usb_console_info_impl_t *, uchar_t *, 916 uint_t, uint_t *); 917 extern int xhci_hcdi_console_output_exit(usb_console_info_impl_t *); 918 919 /* 920 * Logging functions 921 */ 922 extern void xhci_log(xhci_t *xhcip, const char *fmt, ...) __KPRINTFLIKE(2); 923 extern void xhci_error(xhci_t *xhcip, const char *fmt, ...) __KPRINTFLIKE(2); 924 925 /* 926 * Misc. data 927 */ 928 extern void *xhci_soft_state; 929 930 #ifdef __cplusplus 931 } 932 #endif 933 934 #endif /* _SYS_USB_XHCI_XHCI_H */ 935