1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/module.h>
9 #include <linux/device.h>
10 #include <linux/kmod.h>
11 #include <linux/mdio.h>
12 #include <linux/phy.h>
13 #include <linux/ethtool.h>
14
15 #include "xgbe.h"
16 #include "xgbe-common.h"
17
18 #define XGBE_PHY_PORT_SPEED_10 BIT(0)
19 #define XGBE_PHY_PORT_SPEED_100 BIT(1)
20 #define XGBE_PHY_PORT_SPEED_1000 BIT(2)
21 #define XGBE_PHY_PORT_SPEED_2500 BIT(3)
22 #define XGBE_PHY_PORT_SPEED_10000 BIT(4)
23
24 #define XGBE_MUTEX_RELEASE 0x80000000
25
26 #define XGBE_SFP_DIRECT 7
27
28 /* I2C target addresses */
29 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
30 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
31 #define XGBE_SFP_PHY_ADDRESS 0x56
32 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
33
34 /* SFP sideband signal indicators */
35 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
36 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
37 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
38 #define XGBE_GPIO_NO_RX_LOS BIT(3)
39
40 /* Rate-change complete wait/retry count */
41 #define XGBE_RATECHANGE_COUNT 500
42
43 /* CDR delay values for KR support (in usec) */
44 #define XGBE_CDR_DELAY_INIT 10000
45 #define XGBE_CDR_DELAY_INC 10000
46 #define XGBE_CDR_DELAY_MAX 100000
47
48 /* RRC frequency during link status check */
49 #define XGBE_RRC_FREQUENCY 10
50
51 enum xgbe_port_mode {
52 XGBE_PORT_MODE_RSVD = 0,
53 XGBE_PORT_MODE_BACKPLANE,
54 XGBE_PORT_MODE_BACKPLANE_2500,
55 XGBE_PORT_MODE_1000BASE_T,
56 XGBE_PORT_MODE_1000BASE_X,
57 XGBE_PORT_MODE_NBASE_T,
58 XGBE_PORT_MODE_10GBASE_T,
59 XGBE_PORT_MODE_10GBASE_R,
60 XGBE_PORT_MODE_SFP,
61 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
62 XGBE_PORT_MODE_MAX,
63 };
64
65 enum xgbe_conn_type {
66 XGBE_CONN_TYPE_NONE = 0,
67 XGBE_CONN_TYPE_SFP,
68 XGBE_CONN_TYPE_MDIO,
69 XGBE_CONN_TYPE_RSVD1,
70 XGBE_CONN_TYPE_BACKPLANE,
71 XGBE_CONN_TYPE_MAX,
72 };
73
74 /* SFP/SFP+ related definitions */
75 enum xgbe_sfp_comm {
76 XGBE_SFP_COMM_DIRECT = 0,
77 XGBE_SFP_COMM_PCA9545,
78 };
79
80 enum xgbe_sfp_cable {
81 XGBE_SFP_CABLE_UNKNOWN = 0,
82 XGBE_SFP_CABLE_ACTIVE,
83 XGBE_SFP_CABLE_PASSIVE,
84 XGBE_SFP_CABLE_FIBER,
85 };
86
87 enum xgbe_sfp_base {
88 XGBE_SFP_BASE_UNKNOWN = 0,
89 XGBE_SFP_BASE_1000_T,
90 XGBE_SFP_BASE_1000_SX,
91 XGBE_SFP_BASE_1000_LX,
92 XGBE_SFP_BASE_1000_CX,
93 XGBE_SFP_BASE_10000_SR,
94 XGBE_SFP_BASE_10000_LR,
95 XGBE_SFP_BASE_10000_LRM,
96 XGBE_SFP_BASE_10000_ER,
97 XGBE_SFP_BASE_10000_CR,
98 };
99
100 enum xgbe_sfp_speed {
101 XGBE_SFP_SPEED_UNKNOWN = 0,
102 XGBE_SFP_SPEED_100_1000,
103 XGBE_SFP_SPEED_1000,
104 XGBE_SFP_SPEED_10000,
105 };
106
107 /* SFP Serial ID Base ID values relative to an offset of 0 */
108 #define XGBE_SFP_BASE_ID 0
109 #define XGBE_SFP_ID_SFP 0x03
110
111 #define XGBE_SFP_BASE_EXT_ID 1
112 #define XGBE_SFP_EXT_ID_SFP 0x04
113
114 #define XGBE_SFP_BASE_10GBE_CC 3
115 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
116 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
117 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
118 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
119
120 #define XGBE_SFP_BASE_1GBE_CC 6
121 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
122 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
123 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
124 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
125
126 #define XGBE_SFP_BASE_CABLE 8
127 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
128 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
129
130 #define XGBE_SFP_BASE_BR 12
131 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
132 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
133
134 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
135
136 #define XGBE_SFP_BASE_VENDOR_NAME 20
137 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
138 #define XGBE_SFP_BASE_VENDOR_PN 40
139 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
140 #define XGBE_SFP_BASE_VENDOR_REV 56
141 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
142
143 #define XGBE_SFP_BASE_CC 63
144
145 /* SFP Serial ID Extended ID values relative to an offset of 64 */
146 #define XGBE_SFP_BASE_VENDOR_SN 4
147 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
148
149 #define XGBE_SFP_EXTD_OPT1 1
150 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
151 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
152
153 #define XGBE_SFP_EXTD_DIAG 28
154 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
155
156 #define XGBE_SFP_EXTD_SFF_8472 30
157
158 #define XGBE_SFP_EXTD_CC 31
159
160 struct xgbe_sfp_eeprom {
161 u8 base[64];
162 u8 extd[32];
163 u8 vendor[32];
164 };
165
166 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
167 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
168 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
169
170 #define XGBE_SFP_EEPROM_BASE_LEN 256
171 #define XGBE_SFP_EEPROM_DIAG_LEN 256
172 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
173 XGBE_SFP_EEPROM_DIAG_LEN)
174
175 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
176 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
177
178 #define XGBE_MOLEX_VENDOR "Molex Inc. "
179
180 struct xgbe_sfp_ascii {
181 union {
182 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
183 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
184 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
185 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
186 } u;
187 };
188
189 /* MDIO PHY reset types */
190 enum xgbe_mdio_reset {
191 XGBE_MDIO_RESET_NONE = 0,
192 XGBE_MDIO_RESET_I2C_GPIO,
193 XGBE_MDIO_RESET_INT_GPIO,
194 XGBE_MDIO_RESET_MAX,
195 };
196
197 /* Re-driver related definitions */
198 enum xgbe_phy_redrv_if {
199 XGBE_PHY_REDRV_IF_MDIO = 0,
200 XGBE_PHY_REDRV_IF_I2C,
201 XGBE_PHY_REDRV_IF_MAX,
202 };
203
204 enum xgbe_phy_redrv_model {
205 XGBE_PHY_REDRV_MODEL_4223 = 0,
206 XGBE_PHY_REDRV_MODEL_4227,
207 XGBE_PHY_REDRV_MODEL_MAX,
208 };
209
210 enum xgbe_phy_redrv_mode {
211 XGBE_PHY_REDRV_MODE_CX = 5,
212 XGBE_PHY_REDRV_MODE_SR = 9,
213 };
214
215 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
216
217 /* PHY related configuration information */
218 struct xgbe_phy_data {
219 enum xgbe_port_mode port_mode;
220
221 unsigned int port_id;
222
223 unsigned int port_speeds;
224
225 enum xgbe_conn_type conn_type;
226
227 enum xgbe_mode cur_mode;
228 enum xgbe_mode start_mode;
229
230 unsigned int rrc_count;
231
232 unsigned int mdio_addr;
233
234 /* SFP Support */
235 enum xgbe_sfp_comm sfp_comm;
236 unsigned int sfp_mux_address;
237 unsigned int sfp_mux_channel;
238
239 unsigned int sfp_gpio_address;
240 unsigned int sfp_gpio_mask;
241 unsigned int sfp_gpio_inputs;
242 unsigned int sfp_gpio_rx_los;
243 unsigned int sfp_gpio_tx_fault;
244 unsigned int sfp_gpio_mod_absent;
245 unsigned int sfp_gpio_rate_select;
246
247 unsigned int sfp_rx_los;
248 unsigned int sfp_tx_fault;
249 unsigned int sfp_mod_absent;
250 unsigned int sfp_changed;
251 unsigned int sfp_phy_avail;
252 unsigned int sfp_cable_len;
253 enum xgbe_sfp_base sfp_base;
254 enum xgbe_sfp_cable sfp_cable;
255 enum xgbe_sfp_speed sfp_speed;
256 struct xgbe_sfp_eeprom sfp_eeprom;
257
258 /* External PHY support */
259 enum xgbe_mdio_mode phydev_mode;
260 struct mii_bus *mii;
261 struct phy_device *phydev;
262 enum xgbe_mdio_reset mdio_reset;
263 unsigned int mdio_reset_addr;
264 unsigned int mdio_reset_gpio;
265
266 /* Re-driver support */
267 unsigned int redrv;
268 unsigned int redrv_if;
269 unsigned int redrv_addr;
270 unsigned int redrv_lane;
271 unsigned int redrv_model;
272
273 /* KR AN support */
274 unsigned int phy_cdr_notrack;
275 unsigned int phy_cdr_delay;
276 };
277
278 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
279 static DEFINE_MUTEX(xgbe_phy_comm_lock);
280
281 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
282 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata);
283 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
284 enum xgbe_mb_cmd cmd,
285 enum xgbe_mb_subcmd sub_cmd);
286
xgbe_phy_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * i2c_op)287 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
288 struct xgbe_i2c_op *i2c_op)
289 {
290 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
291 }
292
xgbe_phy_redrv_write(struct xgbe_prv_data * pdata,unsigned int reg,unsigned int val)293 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
294 unsigned int val)
295 {
296 struct xgbe_phy_data *phy_data = pdata->phy_data;
297 struct xgbe_i2c_op i2c_op;
298 __be16 *redrv_val;
299 u8 redrv_data[5], csum;
300 unsigned int i, retry;
301 int ret;
302
303 /* High byte of register contains read/write indicator */
304 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
305 redrv_data[1] = reg & 0xff;
306 redrv_val = (__be16 *)&redrv_data[2];
307 *redrv_val = cpu_to_be16(val);
308
309 /* Calculate 1 byte checksum */
310 csum = 0;
311 for (i = 0; i < 4; i++) {
312 csum += redrv_data[i];
313 if (redrv_data[i] > csum)
314 csum++;
315 }
316 redrv_data[4] = ~csum;
317
318 retry = 1;
319 again1:
320 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
321 i2c_op.target = phy_data->redrv_addr;
322 i2c_op.len = sizeof(redrv_data);
323 i2c_op.buf = redrv_data;
324 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
325 if (ret) {
326 if ((ret == -EAGAIN) && retry--)
327 goto again1;
328
329 return ret;
330 }
331
332 retry = 1;
333 again2:
334 i2c_op.cmd = XGBE_I2C_CMD_READ;
335 i2c_op.target = phy_data->redrv_addr;
336 i2c_op.len = 1;
337 i2c_op.buf = redrv_data;
338 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
339 if (ret) {
340 if ((ret == -EAGAIN) && retry--)
341 goto again2;
342
343 return ret;
344 }
345
346 if (redrv_data[0] != 0xff) {
347 netif_dbg(pdata, drv, pdata->netdev,
348 "Redriver write checksum error\n");
349 ret = -EIO;
350 }
351
352 return ret;
353 }
354
xgbe_phy_i2c_write(struct xgbe_prv_data * pdata,unsigned int target,void * val,unsigned int val_len)355 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
356 void *val, unsigned int val_len)
357 {
358 struct xgbe_i2c_op i2c_op;
359 int retry, ret;
360
361 retry = 1;
362 again:
363 /* Write the specfied register */
364 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
365 i2c_op.target = target;
366 i2c_op.len = val_len;
367 i2c_op.buf = val;
368 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
369 if ((ret == -EAGAIN) && retry--)
370 goto again;
371
372 return ret;
373 }
374
xgbe_phy_i2c_read(struct xgbe_prv_data * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)375 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
376 void *reg, unsigned int reg_len,
377 void *val, unsigned int val_len)
378 {
379 struct xgbe_i2c_op i2c_op;
380 int retry, ret;
381
382 retry = 1;
383 again1:
384 /* Set the specified register to read */
385 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
386 i2c_op.target = target;
387 i2c_op.len = reg_len;
388 i2c_op.buf = reg;
389 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
390 if (ret) {
391 if ((ret == -EAGAIN) && retry--)
392 goto again1;
393
394 return ret;
395 }
396
397 retry = 1;
398 again2:
399 /* Read the specfied register */
400 i2c_op.cmd = XGBE_I2C_CMD_READ;
401 i2c_op.target = target;
402 i2c_op.len = val_len;
403 i2c_op.buf = val;
404 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
405 if ((ret == -EAGAIN) && retry--)
406 goto again2;
407
408 return ret;
409 }
410
xgbe_phy_sfp_put_mux(struct xgbe_prv_data * pdata)411 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
412 {
413 struct xgbe_phy_data *phy_data = pdata->phy_data;
414 struct xgbe_i2c_op i2c_op;
415 u8 mux_channel;
416
417 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
418 return 0;
419
420 /* Select no mux channels */
421 mux_channel = 0;
422 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
423 i2c_op.target = phy_data->sfp_mux_address;
424 i2c_op.len = sizeof(mux_channel);
425 i2c_op.buf = &mux_channel;
426
427 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
428 }
429
xgbe_phy_sfp_get_mux(struct xgbe_prv_data * pdata)430 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
431 {
432 struct xgbe_phy_data *phy_data = pdata->phy_data;
433 struct xgbe_i2c_op i2c_op;
434 u8 mux_channel;
435
436 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
437 return 0;
438
439 /* Select desired mux channel */
440 mux_channel = 1 << phy_data->sfp_mux_channel;
441 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
442 i2c_op.target = phy_data->sfp_mux_address;
443 i2c_op.len = sizeof(mux_channel);
444 i2c_op.buf = &mux_channel;
445
446 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
447 }
448
xgbe_phy_put_comm_ownership(struct xgbe_prv_data * pdata)449 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
450 {
451 mutex_unlock(&xgbe_phy_comm_lock);
452 }
453
xgbe_phy_get_comm_ownership(struct xgbe_prv_data * pdata)454 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
455 {
456 struct xgbe_phy_data *phy_data = pdata->phy_data;
457 unsigned long timeout;
458 unsigned int mutex_id;
459
460 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
461 * the driver needs to take the software mutex and then the hardware
462 * mutexes before being able to use the busses.
463 */
464 mutex_lock(&xgbe_phy_comm_lock);
465
466 /* Clear the mutexes */
467 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
468 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
469
470 /* Mutex formats are the same for I2C and MDIO/GPIO */
471 mutex_id = 0;
472 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
473 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
474
475 timeout = jiffies + (5 * HZ);
476 while (time_before(jiffies, timeout)) {
477 /* Must be all zeroes in order to obtain the mutex */
478 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
479 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
480 usleep_range(100, 200);
481 continue;
482 }
483
484 /* Obtain the mutex */
485 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
486 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
487
488 return 0;
489 }
490
491 mutex_unlock(&xgbe_phy_comm_lock);
492
493 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
494
495 return -ETIMEDOUT;
496 }
497
xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data * pdata,int addr,int reg,u16 val)498 static int xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data *pdata, int addr,
499 int reg, u16 val)
500 {
501 struct xgbe_phy_data *phy_data = pdata->phy_data;
502
503 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
504 return -EOPNOTSUPP;
505
506 return pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val);
507 }
508
xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data * pdata,int addr,int devad,int reg,u16 val)509 static int xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data *pdata, int addr,
510 int devad, int reg, u16 val)
511 {
512 struct xgbe_phy_data *phy_data = pdata->phy_data;
513
514 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
515 return -EOPNOTSUPP;
516
517 return pdata->hw_if.write_ext_mii_regs_c45(pdata, addr, devad,
518 reg, val);
519 }
520
xgbe_phy_i2c_mii_write(struct xgbe_prv_data * pdata,int reg,u16 val)521 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
522 {
523 __be16 *mii_val;
524 u8 mii_data[3];
525 int ret;
526
527 ret = xgbe_phy_sfp_get_mux(pdata);
528 if (ret)
529 return ret;
530
531 mii_data[0] = reg & 0xff;
532 mii_val = (__be16 *)&mii_data[1];
533 *mii_val = cpu_to_be16(val);
534
535 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
536 mii_data, sizeof(mii_data));
537
538 xgbe_phy_sfp_put_mux(pdata);
539
540 return ret;
541 }
542
xgbe_phy_mii_write_c22(struct mii_bus * mii,int addr,int reg,u16 val)543 static int xgbe_phy_mii_write_c22(struct mii_bus *mii, int addr, int reg,
544 u16 val)
545 {
546 struct xgbe_prv_data *pdata = mii->priv;
547 struct xgbe_phy_data *phy_data = pdata->phy_data;
548 int ret;
549
550 ret = xgbe_phy_get_comm_ownership(pdata);
551 if (ret)
552 return ret;
553
554 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
555 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
556 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
557 ret = xgbe_phy_mdio_mii_write_c22(pdata, addr, reg, val);
558 else
559 ret = -EOPNOTSUPP;
560
561 xgbe_phy_put_comm_ownership(pdata);
562
563 return ret;
564 }
565
xgbe_phy_mii_write_c45(struct mii_bus * mii,int addr,int devad,int reg,u16 val)566 static int xgbe_phy_mii_write_c45(struct mii_bus *mii, int addr, int devad,
567 int reg, u16 val)
568 {
569 struct xgbe_prv_data *pdata = mii->priv;
570 struct xgbe_phy_data *phy_data = pdata->phy_data;
571 int ret;
572
573 ret = xgbe_phy_get_comm_ownership(pdata);
574 if (ret)
575 return ret;
576
577 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
578 ret = -EOPNOTSUPP;
579 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
580 ret = xgbe_phy_mdio_mii_write_c45(pdata, addr, devad, reg, val);
581 else
582 ret = -EOPNOTSUPP;
583
584 xgbe_phy_put_comm_ownership(pdata);
585
586 return ret;
587 }
588
xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data * pdata,int addr,int reg)589 static int xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data *pdata, int addr,
590 int reg)
591 {
592 struct xgbe_phy_data *phy_data = pdata->phy_data;
593
594 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
595 return -EOPNOTSUPP;
596
597 return pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg);
598 }
599
xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data * pdata,int addr,int devad,int reg)600 static int xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data *pdata, int addr,
601 int devad, int reg)
602 {
603 struct xgbe_phy_data *phy_data = pdata->phy_data;
604
605 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
606 return -EOPNOTSUPP;
607
608 return pdata->hw_if.read_ext_mii_regs_c45(pdata, addr, devad, reg);
609 }
610
xgbe_phy_i2c_mii_read(struct xgbe_prv_data * pdata,int reg)611 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
612 {
613 __be16 mii_val;
614 u8 mii_reg;
615 int ret;
616
617 ret = xgbe_phy_sfp_get_mux(pdata);
618 if (ret)
619 return ret;
620
621 mii_reg = reg;
622 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
623 &mii_reg, sizeof(mii_reg),
624 &mii_val, sizeof(mii_val));
625 if (!ret)
626 ret = be16_to_cpu(mii_val);
627
628 xgbe_phy_sfp_put_mux(pdata);
629
630 return ret;
631 }
632
xgbe_phy_mii_read_c22(struct mii_bus * mii,int addr,int reg)633 static int xgbe_phy_mii_read_c22(struct mii_bus *mii, int addr, int reg)
634 {
635 struct xgbe_prv_data *pdata = mii->priv;
636 struct xgbe_phy_data *phy_data = pdata->phy_data;
637 int ret;
638
639 ret = xgbe_phy_get_comm_ownership(pdata);
640 if (ret)
641 return ret;
642
643 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
644 ret = xgbe_phy_i2c_mii_read(pdata, reg);
645 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
646 ret = xgbe_phy_mdio_mii_read_c22(pdata, addr, reg);
647 else
648 ret = -EOPNOTSUPP;
649
650 xgbe_phy_put_comm_ownership(pdata);
651
652 return ret;
653 }
654
xgbe_phy_mii_read_c45(struct mii_bus * mii,int addr,int devad,int reg)655 static int xgbe_phy_mii_read_c45(struct mii_bus *mii, int addr, int devad,
656 int reg)
657 {
658 struct xgbe_prv_data *pdata = mii->priv;
659 struct xgbe_phy_data *phy_data = pdata->phy_data;
660 int ret;
661
662 ret = xgbe_phy_get_comm_ownership(pdata);
663 if (ret)
664 return ret;
665
666 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
667 ret = -EOPNOTSUPP;
668 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
669 ret = xgbe_phy_mdio_mii_read_c45(pdata, addr, devad, reg);
670 else
671 ret = -ENOTSUPP;
672
673 xgbe_phy_put_comm_ownership(pdata);
674
675 return ret;
676 }
677
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data * pdata)678 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
679 {
680 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
681 struct xgbe_phy_data *phy_data = pdata->phy_data;
682
683 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
684 return;
685
686 XGBE_ZERO_SUP(lks);
687
688 if (phy_data->sfp_mod_absent) {
689 pdata->phy.speed = SPEED_UNKNOWN;
690 pdata->phy.duplex = DUPLEX_UNKNOWN;
691 pdata->phy.autoneg = AUTONEG_ENABLE;
692 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
693
694 XGBE_SET_SUP(lks, Autoneg);
695 XGBE_SET_SUP(lks, Pause);
696 XGBE_SET_SUP(lks, Asym_Pause);
697 XGBE_SET_SUP(lks, TP);
698 XGBE_SET_SUP(lks, FIBRE);
699
700 XGBE_LM_COPY(lks, advertising, lks, supported);
701
702 return;
703 }
704
705 switch (phy_data->sfp_base) {
706 case XGBE_SFP_BASE_1000_T:
707 case XGBE_SFP_BASE_1000_SX:
708 case XGBE_SFP_BASE_1000_LX:
709 case XGBE_SFP_BASE_1000_CX:
710 pdata->phy.speed = SPEED_UNKNOWN;
711 pdata->phy.duplex = DUPLEX_UNKNOWN;
712 pdata->phy.autoneg = AUTONEG_ENABLE;
713 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
714 XGBE_SET_SUP(lks, Autoneg);
715 XGBE_SET_SUP(lks, Pause);
716 XGBE_SET_SUP(lks, Asym_Pause);
717 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
718 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
719 XGBE_SET_SUP(lks, 10baseT_Full);
720 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
721 XGBE_SET_SUP(lks, 100baseT_Full);
722 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
723 XGBE_SET_SUP(lks, 1000baseT_Full);
724 } else {
725 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
726 XGBE_SET_SUP(lks, 1000baseX_Full);
727 }
728 break;
729 case XGBE_SFP_BASE_10000_SR:
730 case XGBE_SFP_BASE_10000_LR:
731 case XGBE_SFP_BASE_10000_LRM:
732 case XGBE_SFP_BASE_10000_ER:
733 case XGBE_SFP_BASE_10000_CR:
734 pdata->phy.speed = SPEED_10000;
735 pdata->phy.duplex = DUPLEX_FULL;
736 pdata->phy.autoneg = AUTONEG_DISABLE;
737 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
738 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
739 switch (phy_data->sfp_base) {
740 case XGBE_SFP_BASE_10000_SR:
741 XGBE_SET_SUP(lks, 10000baseSR_Full);
742 break;
743 case XGBE_SFP_BASE_10000_LR:
744 XGBE_SET_SUP(lks, 10000baseLR_Full);
745 break;
746 case XGBE_SFP_BASE_10000_LRM:
747 XGBE_SET_SUP(lks, 10000baseLRM_Full);
748 break;
749 case XGBE_SFP_BASE_10000_ER:
750 XGBE_SET_SUP(lks, 10000baseER_Full);
751 break;
752 case XGBE_SFP_BASE_10000_CR:
753 XGBE_SET_SUP(lks, 10000baseCR_Full);
754 break;
755 default:
756 break;
757 }
758 }
759 break;
760 default:
761 pdata->phy.speed = SPEED_UNKNOWN;
762 pdata->phy.duplex = DUPLEX_UNKNOWN;
763 pdata->phy.autoneg = AUTONEG_DISABLE;
764 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
765 break;
766 }
767
768 switch (phy_data->sfp_base) {
769 case XGBE_SFP_BASE_1000_T:
770 case XGBE_SFP_BASE_1000_CX:
771 case XGBE_SFP_BASE_10000_CR:
772 XGBE_SET_SUP(lks, TP);
773 break;
774 default:
775 XGBE_SET_SUP(lks, FIBRE);
776 break;
777 }
778
779 XGBE_LM_COPY(lks, advertising, lks, supported);
780 }
781
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom * sfp_eeprom,enum xgbe_sfp_speed sfp_speed)782 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
783 enum xgbe_sfp_speed sfp_speed)
784 {
785 u8 *sfp_base, min;
786
787 sfp_base = sfp_eeprom->base;
788
789 switch (sfp_speed) {
790 case XGBE_SFP_SPEED_1000:
791 min = XGBE_SFP_BASE_BR_1GBE_MIN;
792 break;
793 case XGBE_SFP_SPEED_10000:
794 min = XGBE_SFP_BASE_BR_10GBE_MIN;
795 break;
796 default:
797 return false;
798 }
799
800 return sfp_base[XGBE_SFP_BASE_BR] >= min;
801 }
802
xgbe_phy_free_phy_device(struct xgbe_prv_data * pdata)803 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
804 {
805 struct xgbe_phy_data *phy_data = pdata->phy_data;
806
807 if (phy_data->phydev) {
808 phy_detach(phy_data->phydev);
809 phy_device_remove(phy_data->phydev);
810 phy_device_free(phy_data->phydev);
811 phy_data->phydev = NULL;
812 }
813 }
814
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data * pdata)815 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
816 {
817 struct xgbe_phy_data *phy_data = pdata->phy_data;
818 unsigned int phy_id = phy_data->phydev->phy_id;
819
820 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
821 return false;
822
823 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
824 return false;
825
826 /* Enable Base-T AN */
827 phy_write(phy_data->phydev, 0x16, 0x0001);
828 phy_write(phy_data->phydev, 0x00, 0x9140);
829 phy_write(phy_data->phydev, 0x16, 0x0000);
830
831 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
832 phy_write(phy_data->phydev, 0x1b, 0x9084);
833 phy_write(phy_data->phydev, 0x09, 0x0e00);
834 phy_write(phy_data->phydev, 0x00, 0x8140);
835 phy_write(phy_data->phydev, 0x04, 0x0d01);
836 phy_write(phy_data->phydev, 0x00, 0x9140);
837
838 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES);
839
840 phy_support_asym_pause(phy_data->phydev);
841
842 netif_dbg(pdata, drv, pdata->netdev,
843 "Finisar PHY quirk in place\n");
844
845 return true;
846 }
847
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data * pdata)848 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
849 {
850 struct xgbe_phy_data *phy_data = pdata->phy_data;
851 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
852 unsigned int phy_id = phy_data->phydev->phy_id;
853 int reg;
854
855 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
856 return false;
857
858 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
859 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
860 return false;
861
862 /* For Bel-Fuse, use the extra AN flag */
863 pdata->an_again = 1;
864
865 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
866 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
867 return false;
868
869 if ((phy_id & 0xfffffff0) != 0x03625d10)
870 return false;
871
872 /* Reset PHY - wait for self-clearing reset bit to clear */
873 genphy_soft_reset(phy_data->phydev);
874
875 /* Disable RGMII mode */
876 phy_write(phy_data->phydev, 0x18, 0x7007);
877 reg = phy_read(phy_data->phydev, 0x18);
878 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
879
880 /* Enable fiber register bank */
881 phy_write(phy_data->phydev, 0x1c, 0x7c00);
882 reg = phy_read(phy_data->phydev, 0x1c);
883 reg &= 0x03ff;
884 reg &= ~0x0001;
885 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
886
887 /* Power down SerDes */
888 reg = phy_read(phy_data->phydev, 0x00);
889 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
890
891 /* Configure SGMII-to-Copper mode */
892 phy_write(phy_data->phydev, 0x1c, 0x7c00);
893 reg = phy_read(phy_data->phydev, 0x1c);
894 reg &= 0x03ff;
895 reg &= ~0x0006;
896 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
897
898 /* Power up SerDes */
899 reg = phy_read(phy_data->phydev, 0x00);
900 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
901
902 /* Enable copper register bank */
903 phy_write(phy_data->phydev, 0x1c, 0x7c00);
904 reg = phy_read(phy_data->phydev, 0x1c);
905 reg &= 0x03ff;
906 reg &= ~0x0001;
907 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
908
909 /* Power up SerDes */
910 reg = phy_read(phy_data->phydev, 0x00);
911 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
912
913 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES);
914 phy_support_asym_pause(phy_data->phydev);
915
916 netif_dbg(pdata, drv, pdata->netdev,
917 "BelFuse PHY quirk in place\n");
918
919 return true;
920 }
921
xgbe_phy_external_phy_quirks(struct xgbe_prv_data * pdata)922 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
923 {
924 if (xgbe_phy_belfuse_phy_quirks(pdata))
925 return;
926
927 if (xgbe_phy_finisar_phy_quirks(pdata))
928 return;
929 }
930
xgbe_phy_find_phy_device(struct xgbe_prv_data * pdata)931 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
932 {
933 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
934 struct xgbe_phy_data *phy_data = pdata->phy_data;
935 struct phy_device *phydev;
936 int ret;
937
938 /* If we already have a PHY, just return */
939 if (phy_data->phydev)
940 return 0;
941
942 /* Clear the extra AN flag */
943 pdata->an_again = 0;
944
945 /* Check for the use of an external PHY */
946 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
947 return 0;
948
949 /* For SFP, only use an external PHY if available */
950 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
951 !phy_data->sfp_phy_avail)
952 return 0;
953
954 /* Set the proper MDIO mode for the PHY */
955 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
956 phy_data->phydev_mode);
957 if (ret) {
958 netdev_err(pdata->netdev,
959 "mdio port/clause not compatible (%u/%u)\n",
960 phy_data->mdio_addr, phy_data->phydev_mode);
961 return ret;
962 }
963
964 /* Create and connect to the PHY device */
965 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
966 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
967 if (IS_ERR(phydev)) {
968 netdev_err(pdata->netdev, "get_phy_device failed\n");
969 return -ENODEV;
970 }
971 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
972 phydev->phy_id);
973
974 /*TODO: If c45, add request_module based on one of the MMD ids? */
975
976 ret = phy_device_register(phydev);
977 if (ret) {
978 netdev_err(pdata->netdev, "phy_device_register failed\n");
979 phy_device_free(phydev);
980 return ret;
981 }
982
983 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
984 PHY_INTERFACE_MODE_SGMII);
985 if (ret) {
986 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
987 phy_device_remove(phydev);
988 phy_device_free(phydev);
989 return ret;
990 }
991 phy_data->phydev = phydev;
992
993 xgbe_phy_external_phy_quirks(pdata);
994
995 linkmode_and(phydev->advertising, phydev->advertising,
996 lks->link_modes.advertising);
997
998 phy_start_aneg(phy_data->phydev);
999
1000 return 0;
1001 }
1002
xgbe_phy_sfp_external_phy(struct xgbe_prv_data * pdata)1003 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1004 {
1005 struct xgbe_phy_data *phy_data = pdata->phy_data;
1006 int ret;
1007
1008 if (!phy_data->sfp_changed)
1009 return;
1010
1011 phy_data->sfp_phy_avail = 0;
1012
1013 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1014 return;
1015
1016 /* Check access to the PHY by reading CTRL1 */
1017 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1018 if (ret < 0)
1019 return;
1020
1021 /* Successfully accessed the PHY */
1022 phy_data->sfp_phy_avail = 1;
1023 }
1024
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data * phy_data)1025 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1026 {
1027 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1028
1029 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1030 return false;
1031
1032 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1033 return false;
1034
1035 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1036 return true;
1037
1038 return false;
1039 }
1040
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data * phy_data)1041 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1042 {
1043 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1044
1045 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1046 return false;
1047
1048 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1049 return false;
1050
1051 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1052 return true;
1053
1054 return false;
1055 }
1056
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data * phy_data)1057 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1058 {
1059 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1060 return false;
1061
1062 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1063 return true;
1064
1065 return false;
1066 }
1067
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data * pdata)1068 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1069 {
1070 struct xgbe_phy_data *phy_data = pdata->phy_data;
1071 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1072 u8 *sfp_base;
1073
1074 sfp_base = sfp_eeprom->base;
1075
1076 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1077 return;
1078
1079 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1080 return;
1081
1082 /* Update transceiver signals (eeprom extd/options) */
1083 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1084 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1085
1086 /* Assume FIBER cable unless told otherwise */
1087 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1088 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1089 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1090 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) {
1091 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1092 } else {
1093 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER;
1094 }
1095
1096 /* Determine the type of SFP */
1097 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER &&
1098 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1099 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1100 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1101 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1102 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1103 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1104 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1105 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1106 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1107 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1108 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1109 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1110 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1111 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1112 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1113 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1114 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1115 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1116
1117 switch (phy_data->sfp_base) {
1118 case XGBE_SFP_BASE_1000_T:
1119 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1120 break;
1121 case XGBE_SFP_BASE_1000_SX:
1122 case XGBE_SFP_BASE_1000_LX:
1123 case XGBE_SFP_BASE_1000_CX:
1124 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1125 break;
1126 case XGBE_SFP_BASE_10000_SR:
1127 case XGBE_SFP_BASE_10000_LR:
1128 case XGBE_SFP_BASE_10000_LRM:
1129 case XGBE_SFP_BASE_10000_ER:
1130 case XGBE_SFP_BASE_10000_CR:
1131 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1132 break;
1133 default:
1134 break;
1135 }
1136 }
1137
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data * pdata,struct xgbe_sfp_eeprom * sfp_eeprom)1138 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1139 struct xgbe_sfp_eeprom *sfp_eeprom)
1140 {
1141 struct xgbe_sfp_ascii sfp_ascii;
1142 char *sfp_data = (char *)&sfp_ascii;
1143
1144 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1145 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1146 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1147 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1148 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1149 sfp_data);
1150
1151 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1152 XGBE_SFP_BASE_VENDOR_PN_LEN);
1153 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1154 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1155 sfp_data);
1156
1157 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1158 XGBE_SFP_BASE_VENDOR_REV_LEN);
1159 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1160 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1161 sfp_data);
1162
1163 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1164 XGBE_SFP_BASE_VENDOR_SN_LEN);
1165 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1166 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1167 sfp_data);
1168 }
1169
xgbe_phy_sfp_verify_eeprom(u8 cc_in,u8 * buf,unsigned int len)1170 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1171 {
1172 u8 cc;
1173
1174 for (cc = 0; len; buf++, len--)
1175 cc += *buf;
1176
1177 return cc == cc_in;
1178 }
1179
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data * pdata)1180 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1181 {
1182 struct xgbe_phy_data *phy_data = pdata->phy_data;
1183 struct xgbe_sfp_eeprom sfp_eeprom;
1184 u8 eeprom_addr;
1185 int ret;
1186
1187 ret = xgbe_phy_sfp_get_mux(pdata);
1188 if (ret) {
1189 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1190 netdev_name(pdata->netdev));
1191 return ret;
1192 }
1193
1194 /* Read the SFP serial ID eeprom */
1195 eeprom_addr = 0;
1196 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1197 &eeprom_addr, sizeof(eeprom_addr),
1198 &sfp_eeprom, sizeof(sfp_eeprom));
1199 if (ret) {
1200 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1201 netdev_name(pdata->netdev));
1202 goto put;
1203 }
1204
1205 /* Validate the contents read */
1206 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1207 sfp_eeprom.base,
1208 sizeof(sfp_eeprom.base) - 1)) {
1209 ret = -EINVAL;
1210 goto put;
1211 }
1212
1213 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1214 sfp_eeprom.extd,
1215 sizeof(sfp_eeprom.extd) - 1)) {
1216 ret = -EINVAL;
1217 goto put;
1218 }
1219
1220 /* Check for an added or changed SFP */
1221 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1222 phy_data->sfp_changed = 1;
1223
1224 if (netif_msg_drv(pdata))
1225 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1226
1227 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1228
1229 xgbe_phy_free_phy_device(pdata);
1230 } else {
1231 phy_data->sfp_changed = 0;
1232 }
1233
1234 put:
1235 xgbe_phy_sfp_put_mux(pdata);
1236
1237 return ret;
1238 }
1239
xgbe_phy_sfp_signals(struct xgbe_prv_data * pdata)1240 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1241 {
1242 struct xgbe_phy_data *phy_data = pdata->phy_data;
1243 u8 gpio_reg, gpio_ports[2];
1244 int ret;
1245
1246 /* Read the input port registers */
1247 gpio_reg = 0;
1248 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1249 &gpio_reg, sizeof(gpio_reg),
1250 gpio_ports, sizeof(gpio_ports));
1251 if (ret) {
1252 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1253 netdev_name(pdata->netdev));
1254 return;
1255 }
1256
1257 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1258
1259 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1260 }
1261
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data * pdata)1262 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1263 {
1264 struct xgbe_phy_data *phy_data = pdata->phy_data;
1265
1266 xgbe_phy_free_phy_device(pdata);
1267
1268 phy_data->sfp_mod_absent = 1;
1269 phy_data->sfp_phy_avail = 0;
1270 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1271 }
1272
xgbe_phy_sfp_reset(struct xgbe_phy_data * phy_data)1273 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1274 {
1275 phy_data->sfp_rx_los = 0;
1276 phy_data->sfp_tx_fault = 0;
1277 phy_data->sfp_mod_absent = 1;
1278 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1279 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1280 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1281 }
1282
xgbe_phy_sfp_detect(struct xgbe_prv_data * pdata)1283 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1284 {
1285 struct xgbe_phy_data *phy_data = pdata->phy_data;
1286 int ret;
1287
1288 /* Reset the SFP signals and info */
1289 xgbe_phy_sfp_reset(phy_data);
1290
1291 ret = xgbe_phy_get_comm_ownership(pdata);
1292 if (ret)
1293 return;
1294
1295 /* Read the SFP signals and check for module presence */
1296 xgbe_phy_sfp_signals(pdata);
1297 if (phy_data->sfp_mod_absent) {
1298 xgbe_phy_sfp_mod_absent(pdata);
1299 goto put;
1300 }
1301
1302 ret = xgbe_phy_sfp_read_eeprom(pdata);
1303 if (ret) {
1304 /* Treat any error as if there isn't an SFP plugged in */
1305 xgbe_phy_sfp_reset(phy_data);
1306 xgbe_phy_sfp_mod_absent(pdata);
1307 goto put;
1308 }
1309
1310 xgbe_phy_sfp_parse_eeprom(pdata);
1311
1312 xgbe_phy_sfp_external_phy(pdata);
1313
1314 put:
1315 xgbe_phy_sfp_phy_settings(pdata);
1316
1317 xgbe_phy_put_comm_ownership(pdata);
1318 }
1319
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)1320 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1321 struct ethtool_eeprom *eeprom, u8 *data)
1322 {
1323 struct xgbe_phy_data *phy_data = pdata->phy_data;
1324 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1325 struct xgbe_sfp_eeprom *sfp_eeprom;
1326 unsigned int i, j, rem;
1327 int ret;
1328
1329 rem = eeprom->len;
1330
1331 if (!eeprom->len) {
1332 ret = -EINVAL;
1333 goto done;
1334 }
1335
1336 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1337 ret = -EINVAL;
1338 goto done;
1339 }
1340
1341 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1342 ret = -ENXIO;
1343 goto done;
1344 }
1345
1346 if (!netif_running(pdata->netdev)) {
1347 ret = -EIO;
1348 goto done;
1349 }
1350
1351 if (phy_data->sfp_mod_absent) {
1352 ret = -EIO;
1353 goto done;
1354 }
1355
1356 ret = xgbe_phy_get_comm_ownership(pdata);
1357 if (ret) {
1358 ret = -EIO;
1359 goto done;
1360 }
1361
1362 ret = xgbe_phy_sfp_get_mux(pdata);
1363 if (ret) {
1364 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1365 ret = -EIO;
1366 goto put_own;
1367 }
1368
1369 /* Read the SFP serial ID eeprom */
1370 eeprom_addr = 0;
1371 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1372 &eeprom_addr, sizeof(eeprom_addr),
1373 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1374 if (ret) {
1375 netdev_err(pdata->netdev,
1376 "I2C error reading SFP EEPROM\n");
1377 ret = -EIO;
1378 goto put_mux;
1379 }
1380
1381 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1382
1383 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1384 /* Read the SFP diagnostic eeprom */
1385 eeprom_addr = 0;
1386 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1387 &eeprom_addr, sizeof(eeprom_addr),
1388 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1389 XGBE_SFP_EEPROM_DIAG_LEN);
1390 if (ret) {
1391 netdev_err(pdata->netdev,
1392 "I2C error reading SFP DIAGS\n");
1393 ret = -EIO;
1394 goto put_mux;
1395 }
1396 }
1397
1398 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1399 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1400 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1401 break;
1402
1403 data[i] = eeprom_data[j];
1404 rem--;
1405 }
1406
1407 put_mux:
1408 xgbe_phy_sfp_put_mux(pdata);
1409
1410 put_own:
1411 xgbe_phy_put_comm_ownership(pdata);
1412
1413 done:
1414 eeprom->len -= rem;
1415
1416 return ret;
1417 }
1418
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)1419 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1420 struct ethtool_modinfo *modinfo)
1421 {
1422 struct xgbe_phy_data *phy_data = pdata->phy_data;
1423
1424 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1425 return -ENXIO;
1426
1427 if (!netif_running(pdata->netdev))
1428 return -EIO;
1429
1430 if (phy_data->sfp_mod_absent)
1431 return -EIO;
1432
1433 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1434 modinfo->type = ETH_MODULE_SFF_8472;
1435 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1436 } else {
1437 modinfo->type = ETH_MODULE_SFF_8079;
1438 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1439 }
1440
1441 return 0;
1442 }
1443
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data * pdata)1444 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1445 {
1446 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1447 struct xgbe_phy_data *phy_data = pdata->phy_data;
1448 u16 lcl_adv = 0, rmt_adv = 0;
1449 u8 fc;
1450
1451 pdata->phy.tx_pause = 0;
1452 pdata->phy.rx_pause = 0;
1453
1454 if (!phy_data->phydev)
1455 return;
1456
1457 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1458
1459 if (phy_data->phydev->pause) {
1460 XGBE_SET_LP_ADV(lks, Pause);
1461 rmt_adv |= LPA_PAUSE_CAP;
1462 }
1463 if (phy_data->phydev->asym_pause) {
1464 XGBE_SET_LP_ADV(lks, Asym_Pause);
1465 rmt_adv |= LPA_PAUSE_ASYM;
1466 }
1467
1468 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1469 if (fc & FLOW_CTRL_TX)
1470 pdata->phy.tx_pause = 1;
1471 if (fc & FLOW_CTRL_RX)
1472 pdata->phy.rx_pause = 1;
1473 }
1474
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data * pdata)1475 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1476 {
1477 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1478 enum xgbe_mode mode;
1479
1480 XGBE_SET_LP_ADV(lks, Autoneg);
1481 XGBE_SET_LP_ADV(lks, TP);
1482
1483 /* Use external PHY to determine flow control */
1484 if (pdata->phy.pause_autoneg)
1485 xgbe_phy_phydev_flowctrl(pdata);
1486
1487 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1488 case XGBE_SGMII_AN_LINK_SPEED_10:
1489 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1490 XGBE_SET_LP_ADV(lks, 10baseT_Full);
1491 mode = XGBE_MODE_SGMII_10;
1492 } else {
1493 /* Half-duplex not supported */
1494 XGBE_SET_LP_ADV(lks, 10baseT_Half);
1495 mode = XGBE_MODE_UNKNOWN;
1496 }
1497 break;
1498 case XGBE_SGMII_AN_LINK_SPEED_100:
1499 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1500 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1501 mode = XGBE_MODE_SGMII_100;
1502 } else {
1503 /* Half-duplex not supported */
1504 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1505 mode = XGBE_MODE_UNKNOWN;
1506 }
1507 break;
1508 case XGBE_SGMII_AN_LINK_SPEED_1000:
1509 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1510 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1511 mode = XGBE_MODE_SGMII_1000;
1512 } else {
1513 /* Half-duplex not supported */
1514 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1515 mode = XGBE_MODE_UNKNOWN;
1516 }
1517 break;
1518 default:
1519 mode = XGBE_MODE_UNKNOWN;
1520 }
1521
1522 return mode;
1523 }
1524
xgbe_phy_an37_outcome(struct xgbe_prv_data * pdata)1525 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1526 {
1527 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1528 enum xgbe_mode mode;
1529 unsigned int ad_reg, lp_reg;
1530
1531 XGBE_SET_LP_ADV(lks, Autoneg);
1532 XGBE_SET_LP_ADV(lks, FIBRE);
1533
1534 /* Compare Advertisement and Link Partner register */
1535 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1536 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1537 if (lp_reg & 0x100)
1538 XGBE_SET_LP_ADV(lks, Pause);
1539 if (lp_reg & 0x80)
1540 XGBE_SET_LP_ADV(lks, Asym_Pause);
1541
1542 if (pdata->phy.pause_autoneg) {
1543 /* Set flow control based on auto-negotiation result */
1544 pdata->phy.tx_pause = 0;
1545 pdata->phy.rx_pause = 0;
1546
1547 if (ad_reg & lp_reg & 0x100) {
1548 pdata->phy.tx_pause = 1;
1549 pdata->phy.rx_pause = 1;
1550 } else if (ad_reg & lp_reg & 0x80) {
1551 if (ad_reg & 0x100)
1552 pdata->phy.rx_pause = 1;
1553 else if (lp_reg & 0x100)
1554 pdata->phy.tx_pause = 1;
1555 }
1556 }
1557
1558 if (lp_reg & 0x20)
1559 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1560
1561 /* Half duplex is not supported */
1562 ad_reg &= lp_reg;
1563 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1564
1565 return mode;
1566 }
1567
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data * pdata)1568 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1569 {
1570 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1571 struct xgbe_phy_data *phy_data = pdata->phy_data;
1572 enum xgbe_mode mode;
1573 unsigned int ad_reg, lp_reg;
1574
1575 XGBE_SET_LP_ADV(lks, Autoneg);
1576 XGBE_SET_LP_ADV(lks, Backplane);
1577
1578 /* Use external PHY to determine flow control */
1579 if (pdata->phy.pause_autoneg)
1580 xgbe_phy_phydev_flowctrl(pdata);
1581
1582 /* Compare Advertisement and Link Partner register 2 */
1583 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1584 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1585 if (lp_reg & 0x80)
1586 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1587 if (lp_reg & 0x20)
1588 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1589
1590 ad_reg &= lp_reg;
1591 if (ad_reg & 0x80) {
1592 switch (phy_data->port_mode) {
1593 case XGBE_PORT_MODE_BACKPLANE:
1594 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1595 mode = XGBE_MODE_KR;
1596 break;
1597 default:
1598 mode = XGBE_MODE_SFI;
1599 break;
1600 }
1601 } else if (ad_reg & 0x20) {
1602 switch (phy_data->port_mode) {
1603 case XGBE_PORT_MODE_BACKPLANE:
1604 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1605 mode = XGBE_MODE_KX_1000;
1606 break;
1607 case XGBE_PORT_MODE_1000BASE_X:
1608 mode = XGBE_MODE_X;
1609 break;
1610 case XGBE_PORT_MODE_SFP:
1611 switch (phy_data->sfp_base) {
1612 case XGBE_SFP_BASE_1000_T:
1613 if (phy_data->phydev &&
1614 (phy_data->phydev->speed == SPEED_10))
1615 mode = XGBE_MODE_SGMII_10;
1616 else if (phy_data->phydev &&
1617 (phy_data->phydev->speed == SPEED_100))
1618 mode = XGBE_MODE_SGMII_100;
1619 else
1620 mode = XGBE_MODE_SGMII_1000;
1621 break;
1622 case XGBE_SFP_BASE_1000_SX:
1623 case XGBE_SFP_BASE_1000_LX:
1624 case XGBE_SFP_BASE_1000_CX:
1625 default:
1626 mode = XGBE_MODE_X;
1627 break;
1628 }
1629 break;
1630 default:
1631 if (phy_data->phydev &&
1632 (phy_data->phydev->speed == SPEED_10))
1633 mode = XGBE_MODE_SGMII_10;
1634 else if (phy_data->phydev &&
1635 (phy_data->phydev->speed == SPEED_100))
1636 mode = XGBE_MODE_SGMII_100;
1637 else
1638 mode = XGBE_MODE_SGMII_1000;
1639 break;
1640 }
1641 } else {
1642 mode = XGBE_MODE_UNKNOWN;
1643 }
1644
1645 /* Compare Advertisement and Link Partner register 3 */
1646 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1647 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1648 if (lp_reg & 0xc000)
1649 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1650
1651 return mode;
1652 }
1653
xgbe_phy_an73_outcome(struct xgbe_prv_data * pdata)1654 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1655 {
1656 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1657 enum xgbe_mode mode;
1658 unsigned int ad_reg, lp_reg;
1659
1660 XGBE_SET_LP_ADV(lks, Autoneg);
1661 XGBE_SET_LP_ADV(lks, Backplane);
1662
1663 /* Compare Advertisement and Link Partner register 1 */
1664 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1665 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1666 if (lp_reg & 0x400)
1667 XGBE_SET_LP_ADV(lks, Pause);
1668 if (lp_reg & 0x800)
1669 XGBE_SET_LP_ADV(lks, Asym_Pause);
1670
1671 if (pdata->phy.pause_autoneg) {
1672 /* Set flow control based on auto-negotiation result */
1673 pdata->phy.tx_pause = 0;
1674 pdata->phy.rx_pause = 0;
1675
1676 if (ad_reg & lp_reg & 0x400) {
1677 pdata->phy.tx_pause = 1;
1678 pdata->phy.rx_pause = 1;
1679 } else if (ad_reg & lp_reg & 0x800) {
1680 if (ad_reg & 0x400)
1681 pdata->phy.rx_pause = 1;
1682 else if (lp_reg & 0x400)
1683 pdata->phy.tx_pause = 1;
1684 }
1685 }
1686
1687 /* Compare Advertisement and Link Partner register 2 */
1688 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1689 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1690 if (lp_reg & 0x80)
1691 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1692 if (lp_reg & 0x20)
1693 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1694
1695 ad_reg &= lp_reg;
1696 if (ad_reg & 0x80)
1697 mode = XGBE_MODE_KR;
1698 else if (ad_reg & 0x20)
1699 mode = XGBE_MODE_KX_1000;
1700 else
1701 mode = XGBE_MODE_UNKNOWN;
1702
1703 /* Compare Advertisement and Link Partner register 3 */
1704 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1705 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1706 if (lp_reg & 0xc000)
1707 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1708
1709 return mode;
1710 }
1711
xgbe_phy_an_outcome(struct xgbe_prv_data * pdata)1712 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1713 {
1714 switch (pdata->an_mode) {
1715 case XGBE_AN_MODE_CL73:
1716 return xgbe_phy_an73_outcome(pdata);
1717 case XGBE_AN_MODE_CL73_REDRV:
1718 return xgbe_phy_an73_redrv_outcome(pdata);
1719 case XGBE_AN_MODE_CL37:
1720 return xgbe_phy_an37_outcome(pdata);
1721 case XGBE_AN_MODE_CL37_SGMII:
1722 return xgbe_phy_an37_sgmii_outcome(pdata);
1723 default:
1724 return XGBE_MODE_UNKNOWN;
1725 }
1726 }
1727
xgbe_phy_an_advertising(struct xgbe_prv_data * pdata,struct ethtool_link_ksettings * dlks)1728 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1729 struct ethtool_link_ksettings *dlks)
1730 {
1731 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1732 struct xgbe_phy_data *phy_data = pdata->phy_data;
1733
1734 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1735
1736 /* Without a re-driver, just return current advertising */
1737 if (!phy_data->redrv)
1738 return;
1739
1740 /* With the KR re-driver we need to advertise a single speed */
1741 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1742 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1743
1744 /* Advertise FEC support is present */
1745 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1746 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1747
1748 switch (phy_data->port_mode) {
1749 case XGBE_PORT_MODE_BACKPLANE:
1750 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1751 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1752 break;
1753 case XGBE_PORT_MODE_BACKPLANE_2500:
1754 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1755 break;
1756 case XGBE_PORT_MODE_1000BASE_T:
1757 case XGBE_PORT_MODE_1000BASE_X:
1758 case XGBE_PORT_MODE_NBASE_T:
1759 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1760 break;
1761 case XGBE_PORT_MODE_10GBASE_T:
1762 if (phy_data->phydev &&
1763 (phy_data->phydev->speed == SPEED_10000))
1764 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1765 else if (phy_data->phydev &&
1766 (phy_data->phydev->speed == SPEED_2500))
1767 XGBE_SET_ADV(dlks, 2500baseX_Full);
1768 else
1769 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1770 break;
1771 case XGBE_PORT_MODE_10GBASE_R:
1772 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1773 break;
1774 case XGBE_PORT_MODE_SFP:
1775 switch (phy_data->sfp_base) {
1776 case XGBE_SFP_BASE_1000_T:
1777 case XGBE_SFP_BASE_1000_SX:
1778 case XGBE_SFP_BASE_1000_LX:
1779 case XGBE_SFP_BASE_1000_CX:
1780 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1781 break;
1782 default:
1783 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1784 break;
1785 }
1786 break;
1787 default:
1788 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1789 break;
1790 }
1791 }
1792
xgbe_phy_an_config(struct xgbe_prv_data * pdata)1793 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1794 {
1795 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1796 struct xgbe_phy_data *phy_data = pdata->phy_data;
1797 int ret;
1798
1799 ret = xgbe_phy_find_phy_device(pdata);
1800 if (ret)
1801 return ret;
1802
1803 if (!phy_data->phydev)
1804 return 0;
1805
1806 phy_data->phydev->autoneg = pdata->phy.autoneg;
1807 linkmode_and(phy_data->phydev->advertising,
1808 phy_data->phydev->supported,
1809 lks->link_modes.advertising);
1810
1811 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1812 phy_data->phydev->speed = pdata->phy.speed;
1813 phy_data->phydev->duplex = pdata->phy.duplex;
1814 }
1815
1816 ret = phy_start_aneg(phy_data->phydev);
1817
1818 return ret;
1819 }
1820
xgbe_phy_an_sfp_mode(struct xgbe_phy_data * phy_data)1821 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1822 {
1823 switch (phy_data->sfp_base) {
1824 case XGBE_SFP_BASE_1000_T:
1825 return XGBE_AN_MODE_CL37_SGMII;
1826 case XGBE_SFP_BASE_1000_SX:
1827 case XGBE_SFP_BASE_1000_LX:
1828 case XGBE_SFP_BASE_1000_CX:
1829 return XGBE_AN_MODE_CL37;
1830 default:
1831 return XGBE_AN_MODE_NONE;
1832 }
1833 }
1834
xgbe_phy_an_mode(struct xgbe_prv_data * pdata)1835 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1836 {
1837 struct xgbe_phy_data *phy_data = pdata->phy_data;
1838
1839 /* A KR re-driver will always require CL73 AN */
1840 if (phy_data->redrv)
1841 return XGBE_AN_MODE_CL73_REDRV;
1842
1843 switch (phy_data->port_mode) {
1844 case XGBE_PORT_MODE_BACKPLANE:
1845 return XGBE_AN_MODE_CL73;
1846 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1847 case XGBE_PORT_MODE_BACKPLANE_2500:
1848 return XGBE_AN_MODE_NONE;
1849 case XGBE_PORT_MODE_1000BASE_T:
1850 return XGBE_AN_MODE_CL37_SGMII;
1851 case XGBE_PORT_MODE_1000BASE_X:
1852 return XGBE_AN_MODE_CL37;
1853 case XGBE_PORT_MODE_NBASE_T:
1854 return XGBE_AN_MODE_CL37_SGMII;
1855 case XGBE_PORT_MODE_10GBASE_T:
1856 return XGBE_AN_MODE_CL73;
1857 case XGBE_PORT_MODE_10GBASE_R:
1858 return XGBE_AN_MODE_NONE;
1859 case XGBE_PORT_MODE_SFP:
1860 return xgbe_phy_an_sfp_mode(phy_data);
1861 default:
1862 return XGBE_AN_MODE_NONE;
1863 }
1864 }
1865
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1866 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1867 enum xgbe_phy_redrv_mode mode)
1868 {
1869 struct xgbe_phy_data *phy_data = pdata->phy_data;
1870 u16 redrv_reg, redrv_val;
1871
1872 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1873 redrv_val = (u16)mode;
1874
1875 return pdata->hw_if.write_ext_mii_regs_c22(pdata, phy_data->redrv_addr,
1876 redrv_reg, redrv_val);
1877 }
1878
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1879 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1880 enum xgbe_phy_redrv_mode mode)
1881 {
1882 struct xgbe_phy_data *phy_data = pdata->phy_data;
1883 unsigned int redrv_reg;
1884 int ret;
1885
1886 /* Calculate the register to write */
1887 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1888
1889 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1890
1891 return ret;
1892 }
1893
xgbe_phy_set_redrv_mode(struct xgbe_prv_data * pdata)1894 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1895 {
1896 struct xgbe_phy_data *phy_data = pdata->phy_data;
1897 enum xgbe_phy_redrv_mode mode;
1898 int ret;
1899
1900 if (!phy_data->redrv)
1901 return;
1902
1903 mode = XGBE_PHY_REDRV_MODE_CX;
1904 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1905 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1906 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1907 mode = XGBE_PHY_REDRV_MODE_SR;
1908
1909 ret = xgbe_phy_get_comm_ownership(pdata);
1910 if (ret)
1911 return;
1912
1913 if (phy_data->redrv_if)
1914 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1915 else
1916 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1917
1918 xgbe_phy_put_comm_ownership(pdata);
1919 }
1920
1921 #define MAX_RX_ADAPT_RETRIES 1
1922 #define XGBE_PMA_RX_VAL_SIG_MASK (XGBE_PMA_RX_SIG_DET_0_MASK | \
1923 XGBE_PMA_RX_VALID_0_MASK)
1924
xgbe_set_rx_adap_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)1925 static void xgbe_set_rx_adap_mode(struct xgbe_prv_data *pdata,
1926 enum xgbe_mode mode)
1927 {
1928 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
1929 pdata->rx_adapt_retries = 0;
1930 return;
1931 }
1932
1933 xgbe_phy_perform_ratechange(pdata,
1934 mode == XGBE_MODE_KR ?
1935 XGBE_MB_CMD_SET_10G_KR :
1936 XGBE_MB_CMD_SET_10G_SFI,
1937 XGBE_MB_SUBCMD_RX_ADAP);
1938 }
1939
xgbe_rx_adaptation(struct xgbe_prv_data * pdata)1940 static void xgbe_rx_adaptation(struct xgbe_prv_data *pdata)
1941 {
1942 struct xgbe_phy_data *phy_data = pdata->phy_data;
1943 unsigned int reg;
1944
1945 /* step 2: force PCS to send RX_ADAPT Req to PHY */
1946 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
1947 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE);
1948
1949 /* Step 3: Wait for RX_ADAPT ACK from the PHY */
1950 msleep(200);
1951
1952 /* Software polls for coefficient update command (given by local PHY) */
1953 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU);
1954
1955 /* Clear the RX_AD_REQ bit */
1956 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
1957 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE);
1958
1959 /* Check if coefficient update command is set */
1960 if ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK)
1961 goto set_mode;
1962
1963 /* Step 4: Check for Block lock */
1964
1965 /* Link status is latched low, so read once to clear
1966 * and then read again to get current state
1967 */
1968 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1969 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1970 if (reg & MDIO_STAT1_LSTATUS) {
1971 /* If the block lock is found, update the helpers
1972 * and declare the link up
1973 */
1974 netif_dbg(pdata, link, pdata->netdev, "Block_lock done");
1975 pdata->rx_adapt_done = true;
1976 pdata->mode_set = false;
1977 return;
1978 }
1979
1980 set_mode:
1981 xgbe_set_rx_adap_mode(pdata, phy_data->cur_mode);
1982 }
1983
xgbe_phy_rx_adaptation(struct xgbe_prv_data * pdata)1984 static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata)
1985 {
1986 unsigned int reg;
1987
1988 rx_adapt_reinit:
1989 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS,
1990 XGBE_PMA_RX_VAL_SIG_MASK);
1991
1992 /* step 1: Check for RX_VALID && LF_SIGDET */
1993 if ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) {
1994 netif_dbg(pdata, link, pdata->netdev,
1995 "RX_VALID or LF_SIGDET is unset, issue rrc");
1996 xgbe_phy_rrc(pdata);
1997 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
1998 pdata->rx_adapt_retries = 0;
1999 return;
2000 }
2001 goto rx_adapt_reinit;
2002 }
2003
2004 /* perform rx adaptation */
2005 xgbe_rx_adaptation(pdata);
2006 }
2007
xgbe_phy_rx_reset(struct xgbe_prv_data * pdata)2008 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
2009 {
2010 int reg;
2011
2012 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
2013 XGBE_PCS_PSEQ_STATE_MASK);
2014 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
2015 /* Mailbox command timed out, reset of RX block is required.
2016 * This can be done by asseting the reset bit and wait for
2017 * its compeletion.
2018 */
2019 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2020 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
2021 ndelay(20);
2022 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2023 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
2024 usleep_range(40, 50);
2025 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
2026 }
2027 }
2028
xgbe_phy_pll_ctrl(struct xgbe_prv_data * pdata,bool enable)2029 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
2030 {
2031 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
2032 if (pdata->phy.autoneg != AUTONEG_DISABLE)
2033 return;
2034
2035 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
2036 XGBE_PMA_PLL_CTRL_MASK,
2037 enable ? XGBE_PMA_PLL_CTRL_ENABLE
2038 : XGBE_PMA_PLL_CTRL_DISABLE);
2039
2040 /* Wait for command to complete */
2041 usleep_range(100, 200);
2042 }
2043
xgbe_phy_perform_ratechange(struct xgbe_prv_data * pdata,enum xgbe_mb_cmd cmd,enum xgbe_mb_subcmd sub_cmd)2044 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
2045 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd)
2046 {
2047 unsigned int s0 = 0;
2048 unsigned int wait;
2049
2050 /* Disable PLL re-initialization during FW command processing */
2051 xgbe_phy_pll_ctrl(pdata, false);
2052
2053 /* Log if a previous command did not complete */
2054 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2055 netif_dbg(pdata, link, pdata->netdev,
2056 "firmware mailbox not ready for command\n");
2057 xgbe_phy_rx_reset(pdata);
2058 }
2059
2060 /* Construct the command */
2061 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2062 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2063
2064 /* Issue the command */
2065 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2066 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2067 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2068
2069 /* Wait for command to complete */
2070 wait = XGBE_RATECHANGE_COUNT;
2071 while (wait--) {
2072 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2073 goto do_rx_adaptation;
2074
2075 usleep_range(1000, 2000);
2076 }
2077
2078 netif_dbg(pdata, link, pdata->netdev,
2079 "firmware mailbox command did not complete\n");
2080
2081 /* Reset on error */
2082 xgbe_phy_rx_reset(pdata);
2083 goto reenable_pll;
2084
2085 do_rx_adaptation:
2086 if (pdata->en_rx_adap && sub_cmd == XGBE_MB_SUBCMD_RX_ADAP &&
2087 (cmd == XGBE_MB_CMD_SET_10G_KR || cmd == XGBE_MB_CMD_SET_10G_SFI)) {
2088 netif_dbg(pdata, link, pdata->netdev,
2089 "Enabling RX adaptation\n");
2090 pdata->mode_set = true;
2091 xgbe_phy_rx_adaptation(pdata);
2092 /* return from here to avoid enabling PLL ctrl
2093 * during adaptation phase
2094 */
2095 return;
2096 }
2097
2098 reenable_pll:
2099 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
2100 if (cmd != XGBE_MB_CMD_POWER_OFF &&
2101 cmd != XGBE_MB_CMD_RRC)
2102 xgbe_phy_pll_ctrl(pdata, true);
2103 }
2104
xgbe_phy_rrc(struct xgbe_prv_data * pdata)2105 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2106 {
2107 /* Receiver Reset Cycle */
2108 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE);
2109
2110 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2111 }
2112
xgbe_phy_power_off(struct xgbe_prv_data * pdata)2113 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2114 {
2115 struct xgbe_phy_data *phy_data = pdata->phy_data;
2116
2117 /* Power off */
2118 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE);
2119
2120 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2121
2122 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2123 }
2124
enable_rx_adap(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2125 static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2126 {
2127 struct xgbe_phy_data *phy_data = pdata->phy_data;
2128 unsigned int ver;
2129
2130 /* Rx-Adaptation is not supported on older platforms(< 0x30H) */
2131 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2132 if (ver < 0x30)
2133 return false;
2134
2135 /* Re-driver models 4223 && 4227 do not support Rx-Adaptation */
2136 if (phy_data->redrv &&
2137 (phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4223 ||
2138 phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4227))
2139 return false;
2140
2141 /* 10G KR mode with AN does not support Rx-Adaptation */
2142 if (mode == XGBE_MODE_KR &&
2143 phy_data->port_mode != XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG)
2144 return false;
2145
2146 pdata->en_rx_adap = 1;
2147 return true;
2148 }
2149
xgbe_phy_sfi_mode(struct xgbe_prv_data * pdata)2150 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2151 {
2152 struct xgbe_phy_data *phy_data = pdata->phy_data;
2153
2154 xgbe_phy_set_redrv_mode(pdata);
2155
2156 /* 10G/SFI */
2157 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2158 pdata->en_rx_adap = 0;
2159 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE);
2160 } else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
2161 (enable_rx_adap(pdata, XGBE_MODE_SFI))) {
2162 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2163 XGBE_MB_SUBCMD_RX_ADAP);
2164 } else {
2165 if (phy_data->sfp_cable_len <= 1)
2166 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2167 XGBE_MB_SUBCMD_PASSIVE_1M);
2168 else if (phy_data->sfp_cable_len <= 3)
2169 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2170 XGBE_MB_SUBCMD_PASSIVE_3M);
2171 else
2172 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2173 XGBE_MB_SUBCMD_PASSIVE_OTHER);
2174 }
2175
2176 phy_data->cur_mode = XGBE_MODE_SFI;
2177
2178 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2179 }
2180
xgbe_phy_x_mode(struct xgbe_prv_data * pdata)2181 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2182 {
2183 struct xgbe_phy_data *phy_data = pdata->phy_data;
2184
2185 xgbe_phy_set_redrv_mode(pdata);
2186
2187 /* 1G/X */
2188 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2189
2190 phy_data->cur_mode = XGBE_MODE_X;
2191
2192 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2193 }
2194
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data * pdata)2195 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2196 {
2197 struct xgbe_phy_data *phy_data = pdata->phy_data;
2198
2199 xgbe_phy_set_redrv_mode(pdata);
2200
2201 /* 1G/SGMII */
2202 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII);
2203
2204 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2205
2206 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2207 }
2208
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data * pdata)2209 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2210 {
2211 struct xgbe_phy_data *phy_data = pdata->phy_data;
2212
2213 xgbe_phy_set_redrv_mode(pdata);
2214
2215 /* 100M/SGMII */
2216 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS);
2217
2218 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2219
2220 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2221 }
2222
xgbe_phy_sgmii_10_mode(struct xgbe_prv_data * pdata)2223 static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata)
2224 {
2225 struct xgbe_phy_data *phy_data = pdata->phy_data;
2226
2227 xgbe_phy_set_redrv_mode(pdata);
2228
2229 /* 10M/SGMII */
2230 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS);
2231
2232 phy_data->cur_mode = XGBE_MODE_SGMII_10;
2233
2234 netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n");
2235 }
2236
xgbe_phy_kr_mode(struct xgbe_prv_data * pdata)2237 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2238 {
2239 struct xgbe_phy_data *phy_data = pdata->phy_data;
2240
2241 xgbe_phy_set_redrv_mode(pdata);
2242
2243 /* 10G/KR */
2244 if (enable_rx_adap(pdata, XGBE_MODE_KR))
2245 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2246 XGBE_MB_SUBCMD_RX_ADAP);
2247 else
2248 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2249 XGBE_MB_SUBCMD_NONE);
2250
2251 phy_data->cur_mode = XGBE_MODE_KR;
2252
2253 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2254 }
2255
xgbe_phy_kx_2500_mode(struct xgbe_prv_data * pdata)2256 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2257 {
2258 struct xgbe_phy_data *phy_data = pdata->phy_data;
2259
2260 xgbe_phy_set_redrv_mode(pdata);
2261
2262 /* 2.5G/KX */
2263 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE);
2264
2265 phy_data->cur_mode = XGBE_MODE_KX_2500;
2266
2267 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2268 }
2269
xgbe_phy_kx_1000_mode(struct xgbe_prv_data * pdata)2270 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2271 {
2272 struct xgbe_phy_data *phy_data = pdata->phy_data;
2273
2274 xgbe_phy_set_redrv_mode(pdata);
2275
2276 /* 1G/KX */
2277 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2278
2279 phy_data->cur_mode = XGBE_MODE_KX_1000;
2280
2281 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2282 }
2283
xgbe_phy_cur_mode(struct xgbe_prv_data * pdata)2284 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2285 {
2286 struct xgbe_phy_data *phy_data = pdata->phy_data;
2287
2288 return phy_data->cur_mode;
2289 }
2290
xgbe_phy_switch_baset_mode(struct xgbe_prv_data * pdata)2291 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2292 {
2293 struct xgbe_phy_data *phy_data = pdata->phy_data;
2294
2295 /* No switching if not 10GBase-T */
2296 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2297 return xgbe_phy_cur_mode(pdata);
2298
2299 switch (xgbe_phy_cur_mode(pdata)) {
2300 case XGBE_MODE_SGMII_10:
2301 case XGBE_MODE_SGMII_100:
2302 case XGBE_MODE_SGMII_1000:
2303 return XGBE_MODE_KR;
2304 case XGBE_MODE_KX_2500:
2305 return XGBE_MODE_SGMII_1000;
2306 case XGBE_MODE_KR:
2307 default:
2308 return XGBE_MODE_KX_2500;
2309 }
2310 }
2311
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data * pdata)2312 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2313 {
2314 return XGBE_MODE_KX_2500;
2315 }
2316
xgbe_phy_switch_bp_mode(struct xgbe_prv_data * pdata)2317 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2318 {
2319 /* If we are in KR switch to KX, and vice-versa */
2320 switch (xgbe_phy_cur_mode(pdata)) {
2321 case XGBE_MODE_KX_1000:
2322 return XGBE_MODE_KR;
2323 case XGBE_MODE_KR:
2324 default:
2325 return XGBE_MODE_KX_1000;
2326 }
2327 }
2328
xgbe_phy_switch_mode(struct xgbe_prv_data * pdata)2329 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2330 {
2331 struct xgbe_phy_data *phy_data = pdata->phy_data;
2332
2333 switch (phy_data->port_mode) {
2334 case XGBE_PORT_MODE_BACKPLANE:
2335 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2336 return xgbe_phy_switch_bp_mode(pdata);
2337 case XGBE_PORT_MODE_BACKPLANE_2500:
2338 return xgbe_phy_switch_bp_2500_mode(pdata);
2339 case XGBE_PORT_MODE_1000BASE_T:
2340 case XGBE_PORT_MODE_NBASE_T:
2341 case XGBE_PORT_MODE_10GBASE_T:
2342 return xgbe_phy_switch_baset_mode(pdata);
2343 case XGBE_PORT_MODE_1000BASE_X:
2344 case XGBE_PORT_MODE_10GBASE_R:
2345 case XGBE_PORT_MODE_SFP:
2346 /* No switching, so just return current mode */
2347 return xgbe_phy_cur_mode(pdata);
2348 default:
2349 return XGBE_MODE_UNKNOWN;
2350 }
2351 }
2352
xgbe_phy_get_basex_mode(struct xgbe_phy_data * phy_data,int speed)2353 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2354 int speed)
2355 {
2356 switch (speed) {
2357 case SPEED_1000:
2358 return XGBE_MODE_X;
2359 case SPEED_10000:
2360 return XGBE_MODE_KR;
2361 default:
2362 return XGBE_MODE_UNKNOWN;
2363 }
2364 }
2365
xgbe_phy_get_baset_mode(struct xgbe_phy_data * phy_data,int speed)2366 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2367 int speed)
2368 {
2369 switch (speed) {
2370 case SPEED_10:
2371 return XGBE_MODE_SGMII_10;
2372 case SPEED_100:
2373 return XGBE_MODE_SGMII_100;
2374 case SPEED_1000:
2375 return XGBE_MODE_SGMII_1000;
2376 case SPEED_2500:
2377 return XGBE_MODE_KX_2500;
2378 case SPEED_10000:
2379 return XGBE_MODE_KR;
2380 default:
2381 return XGBE_MODE_UNKNOWN;
2382 }
2383 }
2384
xgbe_phy_get_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2385 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2386 int speed)
2387 {
2388 switch (speed) {
2389 case SPEED_10:
2390 return XGBE_MODE_SGMII_10;
2391 case SPEED_100:
2392 return XGBE_MODE_SGMII_100;
2393 case SPEED_1000:
2394 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2395 return XGBE_MODE_SGMII_1000;
2396 else
2397 return XGBE_MODE_X;
2398 case SPEED_10000:
2399 case SPEED_UNKNOWN:
2400 return XGBE_MODE_SFI;
2401 default:
2402 return XGBE_MODE_UNKNOWN;
2403 }
2404 }
2405
xgbe_phy_get_bp_2500_mode(int speed)2406 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2407 {
2408 switch (speed) {
2409 case SPEED_2500:
2410 return XGBE_MODE_KX_2500;
2411 default:
2412 return XGBE_MODE_UNKNOWN;
2413 }
2414 }
2415
xgbe_phy_get_bp_mode(int speed)2416 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2417 {
2418 switch (speed) {
2419 case SPEED_1000:
2420 return XGBE_MODE_KX_1000;
2421 case SPEED_10000:
2422 return XGBE_MODE_KR;
2423 default:
2424 return XGBE_MODE_UNKNOWN;
2425 }
2426 }
2427
xgbe_phy_get_mode(struct xgbe_prv_data * pdata,int speed)2428 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2429 int speed)
2430 {
2431 struct xgbe_phy_data *phy_data = pdata->phy_data;
2432
2433 switch (phy_data->port_mode) {
2434 case XGBE_PORT_MODE_BACKPLANE:
2435 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2436 return xgbe_phy_get_bp_mode(speed);
2437 case XGBE_PORT_MODE_BACKPLANE_2500:
2438 return xgbe_phy_get_bp_2500_mode(speed);
2439 case XGBE_PORT_MODE_1000BASE_T:
2440 case XGBE_PORT_MODE_NBASE_T:
2441 case XGBE_PORT_MODE_10GBASE_T:
2442 return xgbe_phy_get_baset_mode(phy_data, speed);
2443 case XGBE_PORT_MODE_1000BASE_X:
2444 case XGBE_PORT_MODE_10GBASE_R:
2445 return xgbe_phy_get_basex_mode(phy_data, speed);
2446 case XGBE_PORT_MODE_SFP:
2447 return xgbe_phy_get_sfp_mode(phy_data, speed);
2448 default:
2449 return XGBE_MODE_UNKNOWN;
2450 }
2451 }
2452
xgbe_phy_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2453 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2454 {
2455 switch (mode) {
2456 case XGBE_MODE_KX_1000:
2457 xgbe_phy_kx_1000_mode(pdata);
2458 break;
2459 case XGBE_MODE_KX_2500:
2460 xgbe_phy_kx_2500_mode(pdata);
2461 break;
2462 case XGBE_MODE_KR:
2463 xgbe_phy_kr_mode(pdata);
2464 break;
2465 case XGBE_MODE_SGMII_10:
2466 xgbe_phy_sgmii_10_mode(pdata);
2467 break;
2468 case XGBE_MODE_SGMII_100:
2469 xgbe_phy_sgmii_100_mode(pdata);
2470 break;
2471 case XGBE_MODE_SGMII_1000:
2472 xgbe_phy_sgmii_1000_mode(pdata);
2473 break;
2474 case XGBE_MODE_X:
2475 xgbe_phy_x_mode(pdata);
2476 break;
2477 case XGBE_MODE_SFI:
2478 xgbe_phy_sfi_mode(pdata);
2479 break;
2480 default:
2481 break;
2482 }
2483 }
2484
xgbe_phy_check_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode,bool advert)2485 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2486 enum xgbe_mode mode, bool advert)
2487 {
2488 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2489 return advert;
2490 } else {
2491 enum xgbe_mode cur_mode;
2492
2493 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2494 if (cur_mode == mode)
2495 return true;
2496 }
2497
2498 return false;
2499 }
2500
xgbe_phy_use_basex_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2501 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2502 enum xgbe_mode mode)
2503 {
2504 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2505
2506 switch (mode) {
2507 case XGBE_MODE_X:
2508 return xgbe_phy_check_mode(pdata, mode,
2509 XGBE_ADV(lks, 1000baseX_Full));
2510 case XGBE_MODE_KR:
2511 return xgbe_phy_check_mode(pdata, mode,
2512 XGBE_ADV(lks, 10000baseKR_Full));
2513 default:
2514 return false;
2515 }
2516 }
2517
xgbe_phy_use_baset_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2518 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2519 enum xgbe_mode mode)
2520 {
2521 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2522
2523 switch (mode) {
2524 case XGBE_MODE_SGMII_10:
2525 return xgbe_phy_check_mode(pdata, mode,
2526 XGBE_ADV(lks, 10baseT_Full));
2527 case XGBE_MODE_SGMII_100:
2528 return xgbe_phy_check_mode(pdata, mode,
2529 XGBE_ADV(lks, 100baseT_Full));
2530 case XGBE_MODE_SGMII_1000:
2531 return xgbe_phy_check_mode(pdata, mode,
2532 XGBE_ADV(lks, 1000baseT_Full));
2533 case XGBE_MODE_KX_2500:
2534 return xgbe_phy_check_mode(pdata, mode,
2535 XGBE_ADV(lks, 2500baseT_Full));
2536 case XGBE_MODE_KR:
2537 return xgbe_phy_check_mode(pdata, mode,
2538 XGBE_ADV(lks, 10000baseT_Full));
2539 default:
2540 return false;
2541 }
2542 }
2543
xgbe_phy_use_sfp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2544 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2545 enum xgbe_mode mode)
2546 {
2547 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2548 struct xgbe_phy_data *phy_data = pdata->phy_data;
2549
2550 switch (mode) {
2551 case XGBE_MODE_X:
2552 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2553 return false;
2554 return xgbe_phy_check_mode(pdata, mode,
2555 XGBE_ADV(lks, 1000baseX_Full));
2556 case XGBE_MODE_SGMII_10:
2557 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2558 return false;
2559 return xgbe_phy_check_mode(pdata, mode,
2560 XGBE_ADV(lks, 10baseT_Full));
2561 case XGBE_MODE_SGMII_100:
2562 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2563 return false;
2564 return xgbe_phy_check_mode(pdata, mode,
2565 XGBE_ADV(lks, 100baseT_Full));
2566 case XGBE_MODE_SGMII_1000:
2567 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2568 return false;
2569 return xgbe_phy_check_mode(pdata, mode,
2570 XGBE_ADV(lks, 1000baseT_Full));
2571 case XGBE_MODE_SFI:
2572 if (phy_data->sfp_mod_absent)
2573 return true;
2574 return xgbe_phy_check_mode(pdata, mode,
2575 XGBE_ADV(lks, 10000baseSR_Full) ||
2576 XGBE_ADV(lks, 10000baseLR_Full) ||
2577 XGBE_ADV(lks, 10000baseLRM_Full) ||
2578 XGBE_ADV(lks, 10000baseER_Full) ||
2579 XGBE_ADV(lks, 10000baseCR_Full));
2580 default:
2581 return false;
2582 }
2583 }
2584
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2585 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2586 enum xgbe_mode mode)
2587 {
2588 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2589
2590 switch (mode) {
2591 case XGBE_MODE_KX_2500:
2592 return xgbe_phy_check_mode(pdata, mode,
2593 XGBE_ADV(lks, 2500baseX_Full));
2594 default:
2595 return false;
2596 }
2597 }
2598
xgbe_phy_use_bp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2599 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2600 enum xgbe_mode mode)
2601 {
2602 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2603
2604 switch (mode) {
2605 case XGBE_MODE_KX_1000:
2606 return xgbe_phy_check_mode(pdata, mode,
2607 XGBE_ADV(lks, 1000baseKX_Full));
2608 case XGBE_MODE_KR:
2609 return xgbe_phy_check_mode(pdata, mode,
2610 XGBE_ADV(lks, 10000baseKR_Full));
2611 default:
2612 return false;
2613 }
2614 }
2615
xgbe_phy_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2616 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2617 {
2618 struct xgbe_phy_data *phy_data = pdata->phy_data;
2619
2620 switch (phy_data->port_mode) {
2621 case XGBE_PORT_MODE_BACKPLANE:
2622 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2623 return xgbe_phy_use_bp_mode(pdata, mode);
2624 case XGBE_PORT_MODE_BACKPLANE_2500:
2625 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2626 case XGBE_PORT_MODE_1000BASE_T:
2627 case XGBE_PORT_MODE_NBASE_T:
2628 case XGBE_PORT_MODE_10GBASE_T:
2629 return xgbe_phy_use_baset_mode(pdata, mode);
2630 case XGBE_PORT_MODE_1000BASE_X:
2631 case XGBE_PORT_MODE_10GBASE_R:
2632 return xgbe_phy_use_basex_mode(pdata, mode);
2633 case XGBE_PORT_MODE_SFP:
2634 return xgbe_phy_use_sfp_mode(pdata, mode);
2635 default:
2636 return false;
2637 }
2638 }
2639
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data * phy_data,int speed)2640 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2641 int speed)
2642 {
2643 switch (speed) {
2644 case SPEED_1000:
2645 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2646 case SPEED_10000:
2647 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2648 default:
2649 return false;
2650 }
2651 }
2652
xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data * pdata,int speed)2653 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata,
2654 int speed)
2655 {
2656 struct xgbe_phy_data *phy_data = pdata->phy_data;
2657 unsigned int ver;
2658
2659 switch (speed) {
2660 case SPEED_10:
2661 /* Supported in ver 21H and ver >= 30H */
2662 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2663 return (ver == 0x21 || ver >= 0x30);
2664 case SPEED_100:
2665 case SPEED_1000:
2666 return true;
2667 case SPEED_2500:
2668 return ((phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) ||
2669 (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T));
2670 case SPEED_10000:
2671 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2672 default:
2673 return false;
2674 }
2675 }
2676
xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data * pdata,int speed)2677 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata,
2678 int speed)
2679 {
2680 struct xgbe_phy_data *phy_data = pdata->phy_data;
2681 unsigned int ver;
2682
2683 switch (speed) {
2684 case SPEED_10:
2685 /* Supported in ver 21H and ver >= 30H */
2686 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2687 return ((ver == 0x21 || ver >= 0x30) &&
2688 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2689 case SPEED_100:
2690 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2691 case SPEED_1000:
2692 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2693 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2694 case SPEED_10000:
2695 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2696 default:
2697 return false;
2698 }
2699 }
2700
xgbe_phy_valid_speed_bp_2500_mode(int speed)2701 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2702 {
2703 switch (speed) {
2704 case SPEED_2500:
2705 return true;
2706 default:
2707 return false;
2708 }
2709 }
2710
xgbe_phy_valid_speed_bp_mode(int speed)2711 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2712 {
2713 switch (speed) {
2714 case SPEED_1000:
2715 case SPEED_10000:
2716 return true;
2717 default:
2718 return false;
2719 }
2720 }
2721
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)2722 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2723 {
2724 struct xgbe_phy_data *phy_data = pdata->phy_data;
2725
2726 switch (phy_data->port_mode) {
2727 case XGBE_PORT_MODE_BACKPLANE:
2728 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2729 return xgbe_phy_valid_speed_bp_mode(speed);
2730 case XGBE_PORT_MODE_BACKPLANE_2500:
2731 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2732 case XGBE_PORT_MODE_1000BASE_T:
2733 case XGBE_PORT_MODE_NBASE_T:
2734 case XGBE_PORT_MODE_10GBASE_T:
2735 return xgbe_phy_valid_speed_baset_mode(pdata, speed);
2736 case XGBE_PORT_MODE_1000BASE_X:
2737 case XGBE_PORT_MODE_10GBASE_R:
2738 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2739 case XGBE_PORT_MODE_SFP:
2740 return xgbe_phy_valid_speed_sfp_mode(pdata, speed);
2741 default:
2742 return false;
2743 }
2744 }
2745
xgbe_phy_link_status(struct xgbe_prv_data * pdata,int * an_restart)2746 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2747 {
2748 struct xgbe_phy_data *phy_data = pdata->phy_data;
2749 int reg, ret;
2750
2751 *an_restart = 0;
2752
2753 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2754 /* Check SFP signals */
2755 xgbe_phy_sfp_detect(pdata);
2756
2757 if (phy_data->sfp_changed) {
2758 *an_restart = 1;
2759 return 0;
2760 }
2761
2762 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
2763 if (pdata->en_rx_adap)
2764 pdata->rx_adapt_done = false;
2765 return 0;
2766 }
2767 }
2768
2769 if (phy_data->phydev) {
2770 /* Check external PHY */
2771 ret = phy_read_status(phy_data->phydev);
2772 if (ret < 0)
2773 return 0;
2774
2775 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2776 !phy_aneg_done(phy_data->phydev))
2777 return 0;
2778
2779 if (!phy_data->phydev->link)
2780 return 0;
2781 }
2782
2783 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2784 if (reg < 0)
2785 return reg;
2786
2787 /* Link status is latched low so that momentary link drops
2788 * can be detected. If link was already down read again
2789 * to get the latest state.
2790 */
2791
2792 if (!pdata->phy.link && !(reg & MDIO_STAT1_LSTATUS)) {
2793 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2794 if (reg < 0)
2795 return reg;
2796 }
2797
2798 if (pdata->en_rx_adap) {
2799 /* if the link is available and adaptation is done,
2800 * declare link up
2801 */
2802 if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)
2803 return 1;
2804 /* If either link is not available or adaptation is not done,
2805 * retrigger the adaptation logic. (if the mode is not set,
2806 * then issue mailbox command first)
2807 */
2808 if (pdata->mode_set) {
2809 xgbe_phy_rx_adaptation(pdata);
2810 } else {
2811 pdata->rx_adapt_done = false;
2812 xgbe_phy_set_mode(pdata, phy_data->cur_mode);
2813 }
2814
2815 if (pdata->rx_adapt_done)
2816 return 1;
2817 } else if (reg & MDIO_STAT1_LSTATUS)
2818 return 1;
2819
2820 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2821 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2822 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2823 netif_carrier_off(pdata->netdev);
2824 *an_restart = 1;
2825 }
2826 }
2827
2828 /* No link, attempt a receiver reset cycle */
2829 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2830 phy_data->rrc_count = 0;
2831 xgbe_phy_rrc(pdata);
2832 }
2833
2834 return 0;
2835 }
2836
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data * pdata)2837 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2838 {
2839 struct xgbe_phy_data *phy_data = pdata->phy_data;
2840
2841 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2842 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2843 GPIO_ADDR);
2844
2845 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2846 GPIO_MASK);
2847
2848 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2849 GPIO_RX_LOS);
2850 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2851 GPIO_TX_FAULT);
2852 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2853 GPIO_MOD_ABS);
2854 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2855 GPIO_RATE_SELECT);
2856
2857 if (netif_msg_probe(pdata)) {
2858 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2859 phy_data->sfp_gpio_address);
2860 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2861 phy_data->sfp_gpio_mask);
2862 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2863 phy_data->sfp_gpio_rx_los);
2864 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2865 phy_data->sfp_gpio_tx_fault);
2866 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2867 phy_data->sfp_gpio_mod_absent);
2868 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2869 phy_data->sfp_gpio_rate_select);
2870 }
2871 }
2872
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data * pdata)2873 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2874 {
2875 struct xgbe_phy_data *phy_data = pdata->phy_data;
2876 unsigned int mux_addr_hi, mux_addr_lo;
2877
2878 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2879 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2880 if (mux_addr_lo == XGBE_SFP_DIRECT)
2881 return;
2882
2883 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2884 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2885 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2886 MUX_CHAN);
2887
2888 if (netif_msg_probe(pdata)) {
2889 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2890 phy_data->sfp_mux_address);
2891 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2892 phy_data->sfp_mux_channel);
2893 }
2894 }
2895
xgbe_phy_sfp_setup(struct xgbe_prv_data * pdata)2896 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2897 {
2898 xgbe_phy_sfp_comm_setup(pdata);
2899 xgbe_phy_sfp_gpio_setup(pdata);
2900 }
2901
xgbe_phy_int_mdio_reset(struct xgbe_prv_data * pdata)2902 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2903 {
2904 struct xgbe_phy_data *phy_data = pdata->phy_data;
2905 unsigned int ret;
2906
2907 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2908 if (ret)
2909 return ret;
2910
2911 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2912
2913 return ret;
2914 }
2915
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data * pdata)2916 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2917 {
2918 struct xgbe_phy_data *phy_data = pdata->phy_data;
2919 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2920 int ret;
2921
2922 /* Read the output port registers */
2923 gpio_reg = 2;
2924 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2925 &gpio_reg, sizeof(gpio_reg),
2926 gpio_ports, sizeof(gpio_ports));
2927 if (ret)
2928 return ret;
2929
2930 /* Prepare to write the GPIO data */
2931 gpio_data[0] = 2;
2932 gpio_data[1] = gpio_ports[0];
2933 gpio_data[2] = gpio_ports[1];
2934
2935 /* Set the GPIO pin */
2936 if (phy_data->mdio_reset_gpio < 8)
2937 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2938 else
2939 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2940
2941 /* Write the output port registers */
2942 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2943 gpio_data, sizeof(gpio_data));
2944 if (ret)
2945 return ret;
2946
2947 /* Clear the GPIO pin */
2948 if (phy_data->mdio_reset_gpio < 8)
2949 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2950 else
2951 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2952
2953 /* Write the output port registers */
2954 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2955 gpio_data, sizeof(gpio_data));
2956
2957 return ret;
2958 }
2959
xgbe_phy_mdio_reset(struct xgbe_prv_data * pdata)2960 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2961 {
2962 struct xgbe_phy_data *phy_data = pdata->phy_data;
2963 int ret;
2964
2965 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2966 return 0;
2967
2968 ret = xgbe_phy_get_comm_ownership(pdata);
2969 if (ret)
2970 return ret;
2971
2972 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2973 ret = xgbe_phy_i2c_mdio_reset(pdata);
2974 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2975 ret = xgbe_phy_int_mdio_reset(pdata);
2976
2977 xgbe_phy_put_comm_ownership(pdata);
2978
2979 return ret;
2980 }
2981
xgbe_phy_redrv_error(struct xgbe_phy_data * phy_data)2982 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2983 {
2984 if (!phy_data->redrv)
2985 return false;
2986
2987 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2988 return true;
2989
2990 switch (phy_data->redrv_model) {
2991 case XGBE_PHY_REDRV_MODEL_4223:
2992 if (phy_data->redrv_lane > 3)
2993 return true;
2994 break;
2995 case XGBE_PHY_REDRV_MODEL_4227:
2996 if (phy_data->redrv_lane > 1)
2997 return true;
2998 break;
2999 default:
3000 return true;
3001 }
3002
3003 return false;
3004 }
3005
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data * pdata)3006 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3007 {
3008 struct xgbe_phy_data *phy_data = pdata->phy_data;
3009
3010 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3011 return 0;
3012
3013 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3014 switch (phy_data->mdio_reset) {
3015 case XGBE_MDIO_RESET_NONE:
3016 case XGBE_MDIO_RESET_I2C_GPIO:
3017 case XGBE_MDIO_RESET_INT_GPIO:
3018 break;
3019 default:
3020 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
3021 phy_data->mdio_reset);
3022 return -EINVAL;
3023 }
3024
3025 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3026 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3027 XP_GET_BITS(pdata->pp3, XP_PROP_3,
3028 MDIO_RESET_I2C_ADDR);
3029 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3030 MDIO_RESET_I2C_GPIO);
3031 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
3032 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3033 MDIO_RESET_INT_GPIO);
3034 }
3035
3036 return 0;
3037 }
3038
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data * pdata)3039 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3040 {
3041 struct xgbe_phy_data *phy_data = pdata->phy_data;
3042 unsigned int ver;
3043
3044 /* 10 Mbps speed is supported in ver 21H and ver >= 30H */
3045 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
3046 if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10))
3047 return true;
3048
3049 switch (phy_data->port_mode) {
3050 case XGBE_PORT_MODE_BACKPLANE:
3051 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3052 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3053 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3054 return false;
3055 break;
3056 case XGBE_PORT_MODE_BACKPLANE_2500:
3057 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3058 return false;
3059 break;
3060 case XGBE_PORT_MODE_1000BASE_T:
3061 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3062 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3063 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3064 return false;
3065 break;
3066 case XGBE_PORT_MODE_1000BASE_X:
3067 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3068 return false;
3069 break;
3070 case XGBE_PORT_MODE_NBASE_T:
3071 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3072 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3073 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3074 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3075 return false;
3076 break;
3077 case XGBE_PORT_MODE_10GBASE_T:
3078 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3079 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3080 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3081 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) ||
3082 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3083 return false;
3084 break;
3085 case XGBE_PORT_MODE_10GBASE_R:
3086 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3087 return false;
3088 break;
3089 case XGBE_PORT_MODE_SFP:
3090 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3091 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3092 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3093 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3094 return false;
3095 break;
3096 default:
3097 break;
3098 }
3099
3100 return true;
3101 }
3102
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data * pdata)3103 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3104 {
3105 struct xgbe_phy_data *phy_data = pdata->phy_data;
3106
3107 switch (phy_data->port_mode) {
3108 case XGBE_PORT_MODE_BACKPLANE:
3109 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3110 case XGBE_PORT_MODE_BACKPLANE_2500:
3111 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3112 return false;
3113 break;
3114 case XGBE_PORT_MODE_1000BASE_T:
3115 case XGBE_PORT_MODE_1000BASE_X:
3116 case XGBE_PORT_MODE_NBASE_T:
3117 case XGBE_PORT_MODE_10GBASE_T:
3118 case XGBE_PORT_MODE_10GBASE_R:
3119 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3120 return false;
3121 break;
3122 case XGBE_PORT_MODE_SFP:
3123 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3124 return false;
3125 break;
3126 default:
3127 break;
3128 }
3129
3130 return true;
3131 }
3132
xgbe_phy_port_enabled(struct xgbe_prv_data * pdata)3133 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3134 {
3135 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3136 return false;
3137 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3138 return false;
3139
3140 return true;
3141 }
3142
xgbe_phy_cdr_track(struct xgbe_prv_data * pdata)3143 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3144 {
3145 struct xgbe_phy_data *phy_data = pdata->phy_data;
3146
3147 if (!pdata->debugfs_an_cdr_workaround)
3148 return;
3149
3150 if (!phy_data->phy_cdr_notrack)
3151 return;
3152
3153 usleep_range(phy_data->phy_cdr_delay,
3154 phy_data->phy_cdr_delay + 500);
3155
3156 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3157 XGBE_PMA_CDR_TRACK_EN_MASK,
3158 XGBE_PMA_CDR_TRACK_EN_ON);
3159
3160 phy_data->phy_cdr_notrack = 0;
3161 }
3162
xgbe_phy_cdr_notrack(struct xgbe_prv_data * pdata)3163 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3164 {
3165 struct xgbe_phy_data *phy_data = pdata->phy_data;
3166
3167 if (!pdata->debugfs_an_cdr_workaround)
3168 return;
3169
3170 if (phy_data->phy_cdr_notrack)
3171 return;
3172
3173 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3174 XGBE_PMA_CDR_TRACK_EN_MASK,
3175 XGBE_PMA_CDR_TRACK_EN_OFF);
3176
3177 xgbe_phy_rrc(pdata);
3178
3179 phy_data->phy_cdr_notrack = 1;
3180 }
3181
xgbe_phy_kr_training_post(struct xgbe_prv_data * pdata)3182 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3183 {
3184 if (!pdata->debugfs_an_cdr_track_early)
3185 xgbe_phy_cdr_track(pdata);
3186 }
3187
xgbe_phy_kr_training_pre(struct xgbe_prv_data * pdata)3188 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3189 {
3190 if (pdata->debugfs_an_cdr_track_early)
3191 xgbe_phy_cdr_track(pdata);
3192 }
3193
xgbe_phy_an_post(struct xgbe_prv_data * pdata)3194 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3195 {
3196 struct xgbe_phy_data *phy_data = pdata->phy_data;
3197
3198 switch (pdata->an_mode) {
3199 case XGBE_AN_MODE_CL73:
3200 case XGBE_AN_MODE_CL73_REDRV:
3201 if (phy_data->cur_mode != XGBE_MODE_KR)
3202 break;
3203
3204 xgbe_phy_cdr_track(pdata);
3205
3206 switch (pdata->an_result) {
3207 case XGBE_AN_READY:
3208 case XGBE_AN_COMPLETE:
3209 break;
3210 default:
3211 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3212 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3213 else
3214 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3215 break;
3216 }
3217 break;
3218 default:
3219 break;
3220 }
3221 }
3222
xgbe_phy_an_pre(struct xgbe_prv_data * pdata)3223 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3224 {
3225 struct xgbe_phy_data *phy_data = pdata->phy_data;
3226
3227 switch (pdata->an_mode) {
3228 case XGBE_AN_MODE_CL73:
3229 case XGBE_AN_MODE_CL73_REDRV:
3230 if (phy_data->cur_mode != XGBE_MODE_KR)
3231 break;
3232
3233 xgbe_phy_cdr_notrack(pdata);
3234 break;
3235 default:
3236 break;
3237 }
3238 }
3239
xgbe_phy_stop(struct xgbe_prv_data * pdata)3240 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3241 {
3242 struct xgbe_phy_data *phy_data = pdata->phy_data;
3243
3244 /* If we have an external PHY, free it */
3245 xgbe_phy_free_phy_device(pdata);
3246
3247 /* Reset SFP data */
3248 xgbe_phy_sfp_reset(phy_data);
3249 xgbe_phy_sfp_mod_absent(pdata);
3250
3251 /* Reset CDR support */
3252 xgbe_phy_cdr_track(pdata);
3253
3254 /* Power off the PHY */
3255 xgbe_phy_power_off(pdata);
3256
3257 /* Stop the I2C controller */
3258 pdata->i2c_if.i2c_stop(pdata);
3259 }
3260
xgbe_phy_start(struct xgbe_prv_data * pdata)3261 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3262 {
3263 struct xgbe_phy_data *phy_data = pdata->phy_data;
3264 int ret;
3265
3266 /* Start the I2C controller */
3267 ret = pdata->i2c_if.i2c_start(pdata);
3268 if (ret)
3269 return ret;
3270
3271 /* Set the proper MDIO mode for the re-driver */
3272 if (phy_data->redrv && !phy_data->redrv_if) {
3273 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3274 XGBE_MDIO_MODE_CL22);
3275 if (ret) {
3276 netdev_err(pdata->netdev,
3277 "redriver mdio port not compatible (%u)\n",
3278 phy_data->redrv_addr);
3279 return ret;
3280 }
3281 }
3282
3283 /* Start in highest supported mode */
3284 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3285
3286 /* Reset CDR support */
3287 xgbe_phy_cdr_track(pdata);
3288
3289 /* After starting the I2C controller, we can check for an SFP */
3290 switch (phy_data->port_mode) {
3291 case XGBE_PORT_MODE_SFP:
3292 xgbe_phy_sfp_detect(pdata);
3293 break;
3294 default:
3295 break;
3296 }
3297
3298 /* If we have an external PHY, start it */
3299 ret = xgbe_phy_find_phy_device(pdata);
3300 if (ret)
3301 goto err_i2c;
3302
3303 return 0;
3304
3305 err_i2c:
3306 pdata->i2c_if.i2c_stop(pdata);
3307
3308 return ret;
3309 }
3310
xgbe_phy_reset(struct xgbe_prv_data * pdata)3311 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3312 {
3313 struct xgbe_phy_data *phy_data = pdata->phy_data;
3314 enum xgbe_mode cur_mode;
3315 int ret;
3316
3317 /* Reset by power cycling the PHY */
3318 cur_mode = phy_data->cur_mode;
3319 xgbe_phy_power_off(pdata);
3320 xgbe_phy_set_mode(pdata, cur_mode);
3321
3322 if (!phy_data->phydev)
3323 return 0;
3324
3325 /* Reset the external PHY */
3326 ret = xgbe_phy_mdio_reset(pdata);
3327 if (ret)
3328 return ret;
3329
3330 return phy_init_hw(phy_data->phydev);
3331 }
3332
xgbe_phy_exit(struct xgbe_prv_data * pdata)3333 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3334 {
3335 struct xgbe_phy_data *phy_data = pdata->phy_data;
3336
3337 /* Unregister for driving external PHYs */
3338 mdiobus_unregister(phy_data->mii);
3339 }
3340
xgbe_phy_init(struct xgbe_prv_data * pdata)3341 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3342 {
3343 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3344 struct xgbe_phy_data *phy_data;
3345 struct mii_bus *mii;
3346 int ret;
3347
3348 /* Check if enabled */
3349 if (!xgbe_phy_port_enabled(pdata)) {
3350 dev_info(pdata->dev, "device is not enabled\n");
3351 return -ENODEV;
3352 }
3353
3354 /* Initialize the I2C controller */
3355 ret = pdata->i2c_if.i2c_init(pdata);
3356 if (ret)
3357 return ret;
3358
3359 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3360 if (!phy_data)
3361 return -ENOMEM;
3362 pdata->phy_data = phy_data;
3363
3364 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3365 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3366 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3367 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3368 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3369 if (netif_msg_probe(pdata)) {
3370 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3371 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3372 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3373 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3374 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3375 }
3376
3377 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3378 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3379 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3380 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3381 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3382 if (phy_data->redrv && netif_msg_probe(pdata)) {
3383 dev_dbg(pdata->dev, "redrv present\n");
3384 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3385 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3386 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3387 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3388 }
3389
3390 /* Validate the connection requested */
3391 if (xgbe_phy_conn_type_mismatch(pdata)) {
3392 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3393 phy_data->port_mode, phy_data->conn_type);
3394 return -EINVAL;
3395 }
3396
3397 /* Validate the mode requested */
3398 if (xgbe_phy_port_mode_mismatch(pdata)) {
3399 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3400 phy_data->port_mode, phy_data->port_speeds);
3401 return -EINVAL;
3402 }
3403
3404 /* Check for and validate MDIO reset support */
3405 ret = xgbe_phy_mdio_reset_setup(pdata);
3406 if (ret)
3407 return ret;
3408
3409 /* Validate the re-driver information */
3410 if (xgbe_phy_redrv_error(phy_data)) {
3411 dev_err(pdata->dev, "phy re-driver settings error\n");
3412 return -EINVAL;
3413 }
3414 pdata->kr_redrv = phy_data->redrv;
3415
3416 /* Indicate current mode is unknown */
3417 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3418
3419 /* Initialize supported features */
3420 XGBE_ZERO_SUP(lks);
3421
3422 switch (phy_data->port_mode) {
3423 /* Backplane support */
3424 case XGBE_PORT_MODE_BACKPLANE:
3425 XGBE_SET_SUP(lks, Autoneg);
3426 fallthrough;
3427 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3428 XGBE_SET_SUP(lks, Pause);
3429 XGBE_SET_SUP(lks, Asym_Pause);
3430 XGBE_SET_SUP(lks, Backplane);
3431 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3432 XGBE_SET_SUP(lks, 1000baseKX_Full);
3433 phy_data->start_mode = XGBE_MODE_KX_1000;
3434 }
3435 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3436 XGBE_SET_SUP(lks, 10000baseKR_Full);
3437 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3438 XGBE_SET_SUP(lks, 10000baseR_FEC);
3439 phy_data->start_mode = XGBE_MODE_KR;
3440 }
3441
3442 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3443 break;
3444 case XGBE_PORT_MODE_BACKPLANE_2500:
3445 XGBE_SET_SUP(lks, Pause);
3446 XGBE_SET_SUP(lks, Asym_Pause);
3447 XGBE_SET_SUP(lks, Backplane);
3448 XGBE_SET_SUP(lks, 2500baseX_Full);
3449 phy_data->start_mode = XGBE_MODE_KX_2500;
3450
3451 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3452 break;
3453
3454 /* MDIO 1GBase-T support */
3455 case XGBE_PORT_MODE_1000BASE_T:
3456 XGBE_SET_SUP(lks, Autoneg);
3457 XGBE_SET_SUP(lks, Pause);
3458 XGBE_SET_SUP(lks, Asym_Pause);
3459 XGBE_SET_SUP(lks, TP);
3460 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3461 XGBE_SET_SUP(lks, 10baseT_Full);
3462 phy_data->start_mode = XGBE_MODE_SGMII_10;
3463 }
3464 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3465 XGBE_SET_SUP(lks, 100baseT_Full);
3466 phy_data->start_mode = XGBE_MODE_SGMII_100;
3467 }
3468 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3469 XGBE_SET_SUP(lks, 1000baseT_Full);
3470 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3471 }
3472
3473 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3474 break;
3475
3476 /* MDIO Base-X support */
3477 case XGBE_PORT_MODE_1000BASE_X:
3478 XGBE_SET_SUP(lks, Autoneg);
3479 XGBE_SET_SUP(lks, Pause);
3480 XGBE_SET_SUP(lks, Asym_Pause);
3481 XGBE_SET_SUP(lks, FIBRE);
3482 XGBE_SET_SUP(lks, 1000baseX_Full);
3483 phy_data->start_mode = XGBE_MODE_X;
3484
3485 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3486 break;
3487
3488 /* MDIO NBase-T support */
3489 case XGBE_PORT_MODE_NBASE_T:
3490 XGBE_SET_SUP(lks, Autoneg);
3491 XGBE_SET_SUP(lks, Pause);
3492 XGBE_SET_SUP(lks, Asym_Pause);
3493 XGBE_SET_SUP(lks, TP);
3494 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3495 XGBE_SET_SUP(lks, 10baseT_Full);
3496 phy_data->start_mode = XGBE_MODE_SGMII_10;
3497 }
3498 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3499 XGBE_SET_SUP(lks, 100baseT_Full);
3500 phy_data->start_mode = XGBE_MODE_SGMII_100;
3501 }
3502 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3503 XGBE_SET_SUP(lks, 1000baseT_Full);
3504 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3505 }
3506 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3507 XGBE_SET_SUP(lks, 2500baseT_Full);
3508 phy_data->start_mode = XGBE_MODE_KX_2500;
3509 }
3510
3511 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3512 break;
3513
3514 /* 10GBase-T support */
3515 case XGBE_PORT_MODE_10GBASE_T:
3516 XGBE_SET_SUP(lks, Autoneg);
3517 XGBE_SET_SUP(lks, Pause);
3518 XGBE_SET_SUP(lks, Asym_Pause);
3519 XGBE_SET_SUP(lks, TP);
3520 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3521 XGBE_SET_SUP(lks, 10baseT_Full);
3522 phy_data->start_mode = XGBE_MODE_SGMII_10;
3523 }
3524 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3525 XGBE_SET_SUP(lks, 100baseT_Full);
3526 phy_data->start_mode = XGBE_MODE_SGMII_100;
3527 }
3528 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3529 XGBE_SET_SUP(lks, 1000baseT_Full);
3530 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3531 }
3532 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3533 XGBE_SET_SUP(lks, 2500baseT_Full);
3534 phy_data->start_mode = XGBE_MODE_KX_2500;
3535 }
3536 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3537 XGBE_SET_SUP(lks, 10000baseT_Full);
3538 phy_data->start_mode = XGBE_MODE_KR;
3539 }
3540
3541 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3542 break;
3543
3544 /* 10GBase-R support */
3545 case XGBE_PORT_MODE_10GBASE_R:
3546 XGBE_SET_SUP(lks, Autoneg);
3547 XGBE_SET_SUP(lks, Pause);
3548 XGBE_SET_SUP(lks, Asym_Pause);
3549 XGBE_SET_SUP(lks, FIBRE);
3550 XGBE_SET_SUP(lks, 10000baseSR_Full);
3551 XGBE_SET_SUP(lks, 10000baseLR_Full);
3552 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3553 XGBE_SET_SUP(lks, 10000baseER_Full);
3554 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3555 XGBE_SET_SUP(lks, 10000baseR_FEC);
3556 phy_data->start_mode = XGBE_MODE_SFI;
3557
3558 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3559 break;
3560
3561 /* SFP support */
3562 case XGBE_PORT_MODE_SFP:
3563 XGBE_SET_SUP(lks, Autoneg);
3564 XGBE_SET_SUP(lks, Pause);
3565 XGBE_SET_SUP(lks, Asym_Pause);
3566 XGBE_SET_SUP(lks, TP);
3567 XGBE_SET_SUP(lks, FIBRE);
3568 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
3569 phy_data->start_mode = XGBE_MODE_SGMII_10;
3570 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3571 phy_data->start_mode = XGBE_MODE_SGMII_100;
3572 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3573 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3574 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3575 phy_data->start_mode = XGBE_MODE_SFI;
3576
3577 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3578
3579 xgbe_phy_sfp_setup(pdata);
3580 break;
3581 default:
3582 return -EINVAL;
3583 }
3584
3585 if (netif_msg_probe(pdata))
3586 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3587 __ETHTOOL_LINK_MODE_MASK_NBITS,
3588 lks->link_modes.supported);
3589
3590 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3591 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3592 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3593 phy_data->phydev_mode);
3594 if (ret) {
3595 dev_err(pdata->dev,
3596 "mdio port/clause not compatible (%d/%u)\n",
3597 phy_data->mdio_addr, phy_data->phydev_mode);
3598 return -EINVAL;
3599 }
3600 }
3601
3602 if (phy_data->redrv && !phy_data->redrv_if) {
3603 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3604 XGBE_MDIO_MODE_CL22);
3605 if (ret) {
3606 dev_err(pdata->dev,
3607 "redriver mdio port not compatible (%u)\n",
3608 phy_data->redrv_addr);
3609 return -EINVAL;
3610 }
3611 }
3612
3613 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3614
3615 /* Register for driving external PHYs */
3616 mii = devm_mdiobus_alloc(pdata->dev);
3617 if (!mii) {
3618 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3619 return -ENOMEM;
3620 }
3621
3622 mii->priv = pdata;
3623 mii->name = "amd-xgbe-mii";
3624 mii->read = xgbe_phy_mii_read_c22;
3625 mii->write = xgbe_phy_mii_write_c22;
3626 mii->read_c45 = xgbe_phy_mii_read_c45;
3627 mii->write_c45 = xgbe_phy_mii_write_c45;
3628 mii->parent = pdata->dev;
3629 mii->phy_mask = ~0;
3630 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3631 ret = mdiobus_register(mii);
3632 if (ret) {
3633 dev_err(pdata->dev, "mdiobus_register failed\n");
3634 return ret;
3635 }
3636 phy_data->mii = mii;
3637
3638 return 0;
3639 }
3640
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if * phy_if)3641 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3642 {
3643 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3644
3645 phy_impl->init = xgbe_phy_init;
3646 phy_impl->exit = xgbe_phy_exit;
3647
3648 phy_impl->reset = xgbe_phy_reset;
3649 phy_impl->start = xgbe_phy_start;
3650 phy_impl->stop = xgbe_phy_stop;
3651
3652 phy_impl->link_status = xgbe_phy_link_status;
3653
3654 phy_impl->valid_speed = xgbe_phy_valid_speed;
3655
3656 phy_impl->use_mode = xgbe_phy_use_mode;
3657 phy_impl->set_mode = xgbe_phy_set_mode;
3658 phy_impl->get_mode = xgbe_phy_get_mode;
3659 phy_impl->switch_mode = xgbe_phy_switch_mode;
3660 phy_impl->cur_mode = xgbe_phy_cur_mode;
3661
3662 phy_impl->an_mode = xgbe_phy_an_mode;
3663
3664 phy_impl->an_config = xgbe_phy_an_config;
3665
3666 phy_impl->an_advertising = xgbe_phy_an_advertising;
3667
3668 phy_impl->an_outcome = xgbe_phy_an_outcome;
3669
3670 phy_impl->an_pre = xgbe_phy_an_pre;
3671 phy_impl->an_post = xgbe_phy_an_post;
3672
3673 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3674 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3675
3676 phy_impl->module_info = xgbe_phy_module_info;
3677 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
3678 }
3679