1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_tuning.h"
7
8 #include <kunit/visibility.h>
9
10 #include <drm/drm_managed.h>
11 #include <drm/drm_print.h>
12
13 #include "regs/xe_engine_regs.h"
14 #include "regs/xe_gt_regs.h"
15 #include "xe_gt_types.h"
16 #include "xe_platform_types.h"
17 #include "xe_rtp.h"
18 #include "xe_sriov.h"
19
20 #undef XE_REG_MCR
21 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
22
23 VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_tunings = XE_RTP_TABLE_SR(
24 { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),
25 XE_RTP_RULES(PLATFORM(DG2)),
26 XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))
27 },
28 { XE_RTP_NAME("Tuning: 32B Access Enable"),
29 XE_RTP_RULES(PLATFORM(DG2)),
30 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
31 },
32
33 /* Xe2 */
34
35 { XE_RTP_NAME("Tuning: L3 cache"),
36 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
37 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
38 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
39 },
40 { XE_RTP_NAME("Tuning: L3 cache - media"),
41 XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 3499)),
42 XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
43 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
44 },
45 { XE_RTP_NAME("Tuning: Compression Overfetch"),
46 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499),
47 FUNC(xe_rtp_match_has_flat_ccs)),
48 XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
49 SET(CCCHKNREG1, L3CMPCTRL))
50 },
51 { XE_RTP_NAME("Tuning: Compression Overfetch - media"),
52 XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
53 XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
54 SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
55 },
56 { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
57 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
58 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
59 },
60 { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
61 XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
62 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
63 },
64 { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
65 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
66 FUNC(xe_rtp_match_has_flat_ccs)),
67 XE_RTP_ACTIONS(SET(L3SQCREG2,
68 COMPMEMRD256BOVRFETCHEN))
69 },
70 { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
71 XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
72 FUNC(xe_rtp_match_has_flat_ccs)),
73 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
74 COMPMEMRD256BOVRFETCHEN))
75 },
76 { XE_RTP_NAME("Tuning: Stateless compression control"),
77 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
78 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
79 REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
80 },
81 { XE_RTP_NAME("Tuning: Stateless compression control - media"),
82 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, XE_RTP_END_VERSION_UNDEFINED)),
83 XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
84 REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
85 },
86 { XE_RTP_NAME("Tuning: L3 RW flush all Cache"),
87 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
88 XE_RTP_ACTIONS(SET(SCRATCH3_LBCF, RWFLUSHALLEN))
89 },
90 { XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
91 XE_RTP_RULES(MEDIA_VERSION(2000)),
92 XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
93 },
94
95 /* Xe3p */
96
97 { XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),
98 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
99 IS_INTEGRATED),
100 XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
101 BANK_HASH_4KB_MODE))
102 },
103 );
104 EXPORT_SYMBOL_IF_KUNIT(gt_tunings);
105
106 static const struct xe_rtp_table_sr engine_tunings = XE_RTP_TABLE_SR(
107 { XE_RTP_NAME("Tuning: L3 Hashing Mask"),
108 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
109 FUNC(xe_rtp_match_first_render_or_compute)),
110 XE_RTP_ACTIONS(CLR(XELP_GARBCNTL, XELP_BUS_HASH_CTL_BIT_EXC))
111 },
112 { XE_RTP_NAME("Tuning: Set Indirect State Override"),
113 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
114 ENGINE_CLASS(RENDER)),
115 XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))
116 },
117 { XE_RTP_NAME("Tuning: Disable NULL query for Anyhit Shader"),
118 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
119 FUNC(xe_rtp_match_first_render_or_compute)),
120 XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
121 },
122 { XE_RTP_NAME("Tuning: disable HW reporting of ctx switch to GHWSP"),
123 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3500, XE_RTP_END_VERSION_UNDEFINED)),
124 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
125 GHWSP_CSB_REPORT_DIS,
126 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
127 },
128 { XE_RTP_NAME("Tuning: TileY 2x2 Walk"),
129 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
130 FUNC(xe_rtp_match_first_render_or_compute)),
131 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
132 },
133 );
134
135 static const struct xe_rtp_table_sr lrc_tunings = XE_RTP_TABLE_SR(
136 { XE_RTP_NAME("Tuning: Windower HW Filtering"),
137 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3599), ENGINE_CLASS(RENDER)),
138 XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, HW_FILTERING))
139 },
140
141 /* DG2 */
142
143 { XE_RTP_NAME("Tuning: L3 cache"),
144 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
145 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
146 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
147 },
148 { XE_RTP_NAME("Tuning: TDS gang timer"),
149 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
150 /* read verification is ignored as in i915 - need to check enabling */
151 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
152 FF_MODE2_TDS_TIMER_MASK,
153 FF_MODE2_TDS_TIMER_128))
154 },
155 { XE_RTP_NAME("Tuning: TBIMR fast clip"),
156 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
157 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
158 },
159
160 /* Xe_LPG */
161
162 { XE_RTP_NAME("Tuning: L3 cache"),
163 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
164 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
165 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
166 },
167
168 /* Xe2_HPG */
169
170 { XE_RTP_NAME("Tuning: vs hit max value"),
171 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
172 XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
173 REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
174 },
175 );
176
177 /**
178 * xe_tuning_init - initialize gt with tunings bookkeeping
179 * @gt: GT instance to initialize
180 *
181 * Returns 0 for success, negative error code otherwise.
182 */
xe_tuning_init(struct xe_gt * gt)183 int xe_tuning_init(struct xe_gt *gt)
184 {
185 struct xe_device *xe = gt_to_xe(gt);
186 size_t n_lrc, n_engine, n_gt, total;
187 unsigned long *p;
188
189 n_gt = BITS_TO_LONGS(gt_tunings.n_entries);
190 n_engine = BITS_TO_LONGS(engine_tunings.n_entries);
191 n_lrc = BITS_TO_LONGS(lrc_tunings.n_entries);
192 total = n_gt + n_engine + n_lrc;
193
194 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
195 if (!p)
196 return -ENOMEM;
197
198 gt->tuning_active.gt = p;
199 p += n_gt;
200 gt->tuning_active.engine = p;
201 p += n_engine;
202 gt->tuning_active.lrc = p;
203
204 return 0;
205 }
206 ALLOW_ERROR_INJECTION(xe_tuning_init, ERRNO); /* See xe_pci_probe() */
207
xe_tuning_process_gt(struct xe_gt * gt)208 void xe_tuning_process_gt(struct xe_gt *gt)
209 {
210 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
211
212 xe_rtp_process_ctx_enable_active_tracking(&ctx,
213 gt->tuning_active.gt,
214 gt_tunings.n_entries);
215 xe_rtp_process_to_sr(&ctx, >_tunings, >->reg_sr, false);
216 }
217 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);
218
xe_tuning_process_engine(struct xe_hw_engine * hwe)219 void xe_tuning_process_engine(struct xe_hw_engine *hwe)
220 {
221 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
222
223 xe_rtp_process_ctx_enable_active_tracking(&ctx,
224 hwe->gt->tuning_active.engine,
225 engine_tunings.n_entries);
226 xe_rtp_process_to_sr(&ctx, &engine_tunings, &hwe->reg_sr, false);
227 }
228 EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);
229
230 /**
231 * xe_tuning_process_lrc - process lrc tunings
232 * @hwe: engine instance to process tunings for
233 *
234 * Process LRC table for this platform, saving in @hwe all the tunings that need
235 * to be applied on context restore. These are tunings touching registers that
236 * are part of the HW context image.
237 */
xe_tuning_process_lrc(struct xe_hw_engine * hwe)238 void xe_tuning_process_lrc(struct xe_hw_engine *hwe)
239 {
240 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
241
242 xe_rtp_process_ctx_enable_active_tracking(&ctx,
243 hwe->gt->tuning_active.lrc,
244 lrc_tunings.n_entries);
245 xe_rtp_process_to_sr(&ctx, &lrc_tunings, &hwe->reg_lrc, true);
246 }
247
248 /**
249 * xe_tuning_dump() - Dump GT tuning info into a drm printer.
250 * @gt: the &xe_gt
251 * @p: the &drm_printer
252 *
253 * Return: always 0.
254 */
xe_tuning_dump(struct xe_gt * gt,struct drm_printer * p)255 int xe_tuning_dump(struct xe_gt *gt, struct drm_printer *p)
256 {
257 size_t idx;
258
259 drm_printf(p, "GT Tunings\n");
260 for_each_set_bit(idx, gt->tuning_active.gt, gt_tunings.n_entries)
261 drm_printf_indent(p, 1, "%s\n", gt_tunings.entries[idx].name);
262
263 drm_puts(p, "\n");
264 drm_printf(p, "Engine Tunings\n");
265 for_each_set_bit(idx, gt->tuning_active.engine, engine_tunings.n_entries)
266 drm_printf_indent(p, 1, "%s\n", engine_tunings.entries[idx].name);
267
268 drm_puts(p, "\n");
269 drm_printf(p, "LRC Tunings\n");
270 for_each_set_bit(idx, gt->tuning_active.lrc, lrc_tunings.n_entries)
271 drm_printf_indent(p, 1, "%s\n", lrc_tunings.entries[idx].name);
272
273 return 0;
274 }
275