1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #include "xe_pci.h"
7
8 #include <kunit/static_stub.h>
9 #include <linux/device/driver.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/pm_runtime.h>
13
14 #include <drm/drm_color_mgmt.h>
15 #include <drm/drm_drv.h>
16 #include <drm/intel/pciids.h>
17
18 #include "display/xe_display.h"
19 #include "regs/xe_gt_regs.h"
20 #include "xe_device.h"
21 #include "xe_drv.h"
22 #include "xe_gt.h"
23 #include "xe_gt_sriov_vf.h"
24 #include "xe_guc.h"
25 #include "xe_macros.h"
26 #include "xe_mmio.h"
27 #include "xe_module.h"
28 #include "xe_pci_sriov.h"
29 #include "xe_pci_types.h"
30 #include "xe_pm.h"
31 #include "xe_sriov.h"
32 #include "xe_step.h"
33 #include "xe_survivability_mode.h"
34 #include "xe_tile.h"
35
36 enum toggle_d3cold {
37 D3COLD_DISABLE,
38 D3COLD_ENABLE,
39 };
40
41 struct xe_subplatform_desc {
42 enum xe_subplatform subplatform;
43 const char *name;
44 const u16 *pciidlist;
45 };
46
47 struct xe_device_desc {
48 /* Should only ever be set for platforms without GMD_ID */
49 const struct xe_ip *pre_gmdid_graphics_ip;
50 /* Should only ever be set for platforms without GMD_ID */
51 const struct xe_ip *pre_gmdid_media_ip;
52
53 const char *platform_name;
54 const struct xe_subplatform_desc *subplatforms;
55
56 enum xe_platform platform;
57
58 u8 dma_mask_size;
59 u8 max_remote_tiles:2;
60
61 u8 require_force_probe:1;
62 u8 is_dgfx:1;
63
64 u8 has_display:1;
65 u8 has_fan_control:1;
66 u8 has_heci_gscfi:1;
67 u8 has_heci_cscfi:1;
68 u8 has_llc:1;
69 u8 has_mbx_power_limits:1;
70 u8 has_pxp:1;
71 u8 has_sriov:1;
72 u8 needs_scratch:1;
73 u8 skip_guc_pc:1;
74 u8 skip_mtcfg:1;
75 u8 skip_pcode:1;
76 };
77
78 __diag_push();
79 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
80
81 #define PLATFORM(x) \
82 .platform = XE_##x, \
83 .platform_name = #x
84
85 #define NOP(x) x
86
87 static const struct xe_graphics_desc graphics_xelp = {
88 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
89
90 .va_bits = 48,
91 .vm_max_level = 3,
92 };
93
94 #define XE_HP_FEATURES \
95 .has_range_tlb_invalidation = true, \
96 .va_bits = 48, \
97 .vm_max_level = 3
98
99 static const struct xe_graphics_desc graphics_xehpg = {
100 .hw_engine_mask =
101 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
102 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
103 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
104
105 XE_HP_FEATURES,
106 .vram_flags = XE_VRAM_FLAGS_NEED64K,
107
108 .has_flat_ccs = 1,
109 };
110
111 static const struct xe_graphics_desc graphics_xehpc = {
112 .hw_engine_mask =
113 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
114 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
115 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
116 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
117 BIT(XE_HW_ENGINE_BCS8) |
118 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
119 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
120
121 XE_HP_FEATURES,
122 .va_bits = 57,
123 .vm_max_level = 4,
124 .vram_flags = XE_VRAM_FLAGS_NEED64K,
125
126 .has_asid = 1,
127 .has_atomic_enable_pte_bit = 1,
128 .has_usm = 1,
129 };
130
131 static const struct xe_graphics_desc graphics_xelpg = {
132 .hw_engine_mask =
133 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
134 BIT(XE_HW_ENGINE_CCS0),
135
136 XE_HP_FEATURES,
137 };
138
139 #define XE2_GFX_FEATURES \
140 .has_asid = 1, \
141 .has_atomic_enable_pte_bit = 1, \
142 .has_flat_ccs = 1, \
143 .has_range_tlb_invalidation = 1, \
144 .has_usm = 1, \
145 .has_64bit_timestamp = 1, \
146 .va_bits = 48, \
147 .vm_max_level = 4, \
148 .hw_engine_mask = \
149 BIT(XE_HW_ENGINE_RCS0) | \
150 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
151 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
152
153 static const struct xe_graphics_desc graphics_xe2 = {
154 XE2_GFX_FEATURES,
155 };
156
157 static const struct xe_media_desc media_xem = {
158 .hw_engine_mask =
159 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
160 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
161 };
162
163 static const struct xe_media_desc media_xelpmp = {
164 .hw_engine_mask =
165 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
166 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
167 BIT(XE_HW_ENGINE_GSCCS0)
168 };
169
170 /* Pre-GMDID Graphics IPs */
171 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp };
172 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp };
173 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg };
174 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc };
175
176 /* GMDID-based Graphics IPs */
177 static const struct xe_ip graphics_ips[] = {
178 { 1270, "Xe_LPG", &graphics_xelpg },
179 { 1271, "Xe_LPG", &graphics_xelpg },
180 { 1274, "Xe_LPG+", &graphics_xelpg },
181 { 2001, "Xe2_HPG", &graphics_xe2 },
182 { 2004, "Xe2_LPG", &graphics_xe2 },
183 { 3000, "Xe3_LPG", &graphics_xe2 },
184 { 3001, "Xe3_LPG", &graphics_xe2 },
185 };
186
187 /* Pre-GMDID Media IPs */
188 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem };
189 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem };
190
191 /* GMDID-based Media IPs */
192 static const struct xe_ip media_ips[] = {
193 { 1300, "Xe_LPM+", &media_xelpmp },
194 { 1301, "Xe2_HPM", &media_xelpmp },
195 { 2000, "Xe2_LPM", &media_xelpmp },
196 { 3000, "Xe3_LPM", &media_xelpmp },
197 };
198
199 static const struct xe_device_desc tgl_desc = {
200 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
201 .pre_gmdid_media_ip = &media_ip_xem,
202 PLATFORM(TIGERLAKE),
203 .dma_mask_size = 39,
204 .has_display = true,
205 .has_llc = true,
206 .require_force_probe = true,
207 };
208
209 static const struct xe_device_desc rkl_desc = {
210 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
211 .pre_gmdid_media_ip = &media_ip_xem,
212 PLATFORM(ROCKETLAKE),
213 .dma_mask_size = 39,
214 .has_display = true,
215 .has_llc = true,
216 .require_force_probe = true,
217 };
218
219 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
220
221 static const struct xe_device_desc adl_s_desc = {
222 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
223 .pre_gmdid_media_ip = &media_ip_xem,
224 PLATFORM(ALDERLAKE_S),
225 .dma_mask_size = 39,
226 .has_display = true,
227 .has_llc = true,
228 .require_force_probe = true,
229 .subplatforms = (const struct xe_subplatform_desc[]) {
230 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
231 {},
232 },
233 };
234
235 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
236
237 static const struct xe_device_desc adl_p_desc = {
238 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
239 .pre_gmdid_media_ip = &media_ip_xem,
240 PLATFORM(ALDERLAKE_P),
241 .dma_mask_size = 39,
242 .has_display = true,
243 .has_llc = true,
244 .require_force_probe = true,
245 .subplatforms = (const struct xe_subplatform_desc[]) {
246 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
247 {},
248 },
249 };
250
251 static const struct xe_device_desc adl_n_desc = {
252 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
253 .pre_gmdid_media_ip = &media_ip_xem,
254 PLATFORM(ALDERLAKE_N),
255 .dma_mask_size = 39,
256 .has_display = true,
257 .has_llc = true,
258 .require_force_probe = true,
259 };
260
261 #define DGFX_FEATURES \
262 .is_dgfx = 1
263
264 static const struct xe_device_desc dg1_desc = {
265 .pre_gmdid_graphics_ip = &graphics_ip_xelpp,
266 .pre_gmdid_media_ip = &media_ip_xem,
267 DGFX_FEATURES,
268 PLATFORM(DG1),
269 .dma_mask_size = 39,
270 .has_display = true,
271 .has_heci_gscfi = 1,
272 .require_force_probe = true,
273 };
274
275 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
276 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 };
277 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
278
279 #define DG2_FEATURES \
280 DGFX_FEATURES, \
281 PLATFORM(DG2), \
282 .has_heci_gscfi = 1, \
283 .subplatforms = (const struct xe_subplatform_desc[]) { \
284 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
285 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
286 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
287 { } \
288 }
289
290 static const struct xe_device_desc ats_m_desc = {
291 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
292 .pre_gmdid_media_ip = &media_ip_xehpm,
293 .dma_mask_size = 46,
294 .require_force_probe = true,
295
296 DG2_FEATURES,
297 .has_display = false,
298 };
299
300 static const struct xe_device_desc dg2_desc = {
301 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
302 .pre_gmdid_media_ip = &media_ip_xehpm,
303 .dma_mask_size = 46,
304 .require_force_probe = true,
305
306 DG2_FEATURES,
307 .has_display = true,
308 .has_fan_control = true,
309 .has_mbx_power_limits = false,
310 };
311
312 static const __maybe_unused struct xe_device_desc pvc_desc = {
313 .pre_gmdid_graphics_ip = &graphics_ip_xehpc,
314 DGFX_FEATURES,
315 PLATFORM(PVC),
316 .dma_mask_size = 52,
317 .has_display = false,
318 .has_heci_gscfi = 1,
319 .max_remote_tiles = 1,
320 .require_force_probe = true,
321 .has_mbx_power_limits = false,
322 };
323
324 static const struct xe_device_desc mtl_desc = {
325 /* .graphics and .media determined via GMD_ID */
326 .require_force_probe = true,
327 PLATFORM(METEORLAKE),
328 .dma_mask_size = 46,
329 .has_display = true,
330 .has_pxp = true,
331 };
332
333 static const struct xe_device_desc lnl_desc = {
334 PLATFORM(LUNARLAKE),
335 .dma_mask_size = 46,
336 .has_display = true,
337 .has_pxp = true,
338 .needs_scratch = true,
339 };
340
341 static const struct xe_device_desc bmg_desc = {
342 DGFX_FEATURES,
343 PLATFORM(BATTLEMAGE),
344 .dma_mask_size = 46,
345 .has_display = true,
346 .has_fan_control = true,
347 .has_mbx_power_limits = true,
348 .has_heci_cscfi = 1,
349 .needs_scratch = true,
350 };
351
352 static const struct xe_device_desc ptl_desc = {
353 PLATFORM(PANTHERLAKE),
354 .dma_mask_size = 46,
355 .has_display = true,
356 .has_sriov = true,
357 .require_force_probe = true,
358 .needs_scratch = true,
359 };
360
361 #undef PLATFORM
362 __diag_pop();
363
364 /*
365 * Make sure any device matches here are from most specific to most
366 * general. For example, since the Quanta match is based on the subsystem
367 * and subvendor IDs, we need it to come before the more general IVB
368 * PCI ID matches, otherwise we'll use the wrong info struct above.
369 */
370 static const struct pci_device_id pciidlist[] = {
371 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
372 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
373 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
374 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
375 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
376 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
377 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
378 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
379 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
380 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
381 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
382 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
383 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
384 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
385 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
386 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
387 { }
388 };
389 MODULE_DEVICE_TABLE(pci, pciidlist);
390
391 /* is device_id present in comma separated list of ids */
device_id_in_list(u16 device_id,const char * devices,bool negative)392 static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
393 {
394 char *s, *p, *tok;
395 bool ret;
396
397 if (!devices || !*devices)
398 return false;
399
400 /* match everything */
401 if (negative && strcmp(devices, "!*") == 0)
402 return true;
403 if (!negative && strcmp(devices, "*") == 0)
404 return true;
405
406 s = kstrdup(devices, GFP_KERNEL);
407 if (!s)
408 return false;
409
410 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
411 u16 val;
412
413 if (negative && tok[0] == '!')
414 tok++;
415 else if ((negative && tok[0] != '!') ||
416 (!negative && tok[0] == '!'))
417 continue;
418
419 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
420 ret = true;
421 break;
422 }
423 }
424
425 kfree(s);
426
427 return ret;
428 }
429
id_forced(u16 device_id)430 static bool id_forced(u16 device_id)
431 {
432 return device_id_in_list(device_id, xe_modparam.force_probe, false);
433 }
434
id_blocked(u16 device_id)435 static bool id_blocked(u16 device_id)
436 {
437 return device_id_in_list(device_id, xe_modparam.force_probe, true);
438 }
439
440 static const struct xe_subplatform_desc *
find_subplatform(const struct xe_device * xe,const struct xe_device_desc * desc)441 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
442 {
443 const struct xe_subplatform_desc *sp;
444 const u16 *id;
445
446 for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
447 for (id = sp->pciidlist; *id; id++)
448 if (*id == xe->info.devid)
449 return sp;
450
451 return NULL;
452 }
453
454 enum xe_gmdid_type {
455 GMDID_GRAPHICS,
456 GMDID_MEDIA
457 };
458
read_gmdid(struct xe_device * xe,enum xe_gmdid_type type,u32 * ver,u32 * revid)459 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
460 {
461 struct xe_mmio *mmio = xe_root_tile_mmio(xe);
462 struct xe_reg gmdid_reg = GMD_ID;
463 u32 val;
464
465 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
466
467 if (IS_SRIOV_VF(xe)) {
468 struct xe_gt *gt = xe_root_mmio_gt(xe);
469
470 /*
471 * To get the value of the GMDID register, VFs must obtain it
472 * from the GuC using MMIO communication.
473 *
474 * Note that at this point the xe_gt is not fully uninitialized
475 * and only basic access to MMIO registers is possible. To use
476 * our existing GuC communication functions we must perform at
477 * least basic xe_gt and xe_guc initialization.
478 *
479 * Since to obtain the value of GMDID_MEDIA we need to use the
480 * media GuC, temporarily tweak the gt type.
481 */
482 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
483
484 if (type == GMDID_MEDIA) {
485 gt->info.id = 1;
486 gt->info.type = XE_GT_TYPE_MEDIA;
487 } else {
488 gt->info.id = 0;
489 gt->info.type = XE_GT_TYPE_MAIN;
490 }
491
492 xe_gt_mmio_init(gt);
493 xe_guc_comm_init_early(>->uc.guc);
494
495 /* Don't bother with GMDID if failed to negotiate the GuC ABI */
496 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt);
497
498 /*
499 * Only undo xe_gt.info here, the remaining changes made above
500 * will be overwritten as part of the regular initialization.
501 */
502 gt->info.id = 0;
503 gt->info.type = XE_GT_TYPE_UNINITIALIZED;
504 } else {
505 /*
506 * GMD_ID is a GT register, but at this point in the driver
507 * init we haven't fully initialized the GT yet so we need to
508 * read the register with the tile's MMIO accessor. That means
509 * we need to apply the GSI offset manually since it won't get
510 * automatically added as it would if we were using a GT mmio
511 * accessor.
512 */
513 if (type == GMDID_MEDIA)
514 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
515
516 val = xe_mmio_read32(mmio, gmdid_reg);
517 }
518
519 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
520 *revid = REG_FIELD_GET(GMD_ID_REVID, val);
521 }
522
523 /*
524 * Read IP version from hardware and select graphics/media IP descriptors
525 * based on the result.
526 */
handle_gmdid(struct xe_device * xe,const struct xe_ip ** graphics_ip,const struct xe_ip ** media_ip,u32 * graphics_revid,u32 * media_revid)527 static void handle_gmdid(struct xe_device *xe,
528 const struct xe_ip **graphics_ip,
529 const struct xe_ip **media_ip,
530 u32 *graphics_revid,
531 u32 *media_revid)
532 {
533 u32 ver;
534
535 *graphics_ip = NULL;
536 *media_ip = NULL;
537
538 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
539
540 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) {
541 if (ver == graphics_ips[i].verx100) {
542 *graphics_ip = &graphics_ips[i];
543
544 break;
545 }
546 }
547
548 if (!*graphics_ip) {
549 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n",
550 ver / 100, ver % 100);
551 }
552
553 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
554 /* Media may legitimately be fused off / not present */
555 if (ver == 0)
556 return;
557
558 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) {
559 if (ver == media_ips[i].verx100) {
560 *media_ip = &media_ips[i];
561
562 break;
563 }
564 }
565
566 if (!*media_ip) {
567 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
568 ver / 100, ver % 100);
569 }
570 }
571
572 /*
573 * Initialize device info content that only depends on static driver_data
574 * passed to the driver at probe time from PCI ID table.
575 */
xe_info_init_early(struct xe_device * xe,const struct xe_device_desc * desc,const struct xe_subplatform_desc * subplatform_desc)576 static int xe_info_init_early(struct xe_device *xe,
577 const struct xe_device_desc *desc,
578 const struct xe_subplatform_desc *subplatform_desc)
579 {
580 int err;
581
582 xe->info.platform_name = desc->platform_name;
583 xe->info.platform = desc->platform;
584 xe->info.subplatform = subplatform_desc ?
585 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
586
587 xe->info.dma_mask_size = desc->dma_mask_size;
588 xe->info.is_dgfx = desc->is_dgfx;
589 xe->info.has_fan_control = desc->has_fan_control;
590 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
591 xe->info.has_heci_gscfi = desc->has_heci_gscfi;
592 xe->info.has_heci_cscfi = desc->has_heci_cscfi;
593 xe->info.has_llc = desc->has_llc;
594 xe->info.has_pxp = desc->has_pxp;
595 xe->info.has_sriov = desc->has_sriov;
596 xe->info.skip_guc_pc = desc->skip_guc_pc;
597 xe->info.skip_mtcfg = desc->skip_mtcfg;
598 xe->info.skip_pcode = desc->skip_pcode;
599 xe->info.needs_scratch = desc->needs_scratch;
600
601 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
602 xe_modparam.probe_display &&
603 desc->has_display;
604 xe->info.tile_count = 1 + desc->max_remote_tiles;
605
606 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);
607 if (err)
608 return err;
609
610 return 0;
611 }
612
613 /*
614 * Initialize device info content that does require knowledge about
615 * graphics / media IP version.
616 * Make sure that GT / tile structures allocated by the driver match the data
617 * present in device info.
618 */
xe_info_init(struct xe_device * xe,const struct xe_device_desc * desc)619 static int xe_info_init(struct xe_device *xe,
620 const struct xe_device_desc *desc)
621 {
622 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;
623 const struct xe_ip *graphics_ip;
624 const struct xe_ip *media_ip;
625 const struct xe_graphics_desc *graphics_desc;
626 const struct xe_media_desc *media_desc;
627 struct xe_tile *tile;
628 struct xe_gt *gt;
629 u8 id;
630
631 /*
632 * If this platform supports GMD_ID, we'll detect the proper IP
633 * descriptor to use from hardware registers.
634 * desc->pre_gmdid_graphics_ip will only ever be set at this point for
635 * platforms before GMD_ID. In that case the IP descriptions and
636 * versions are simply derived from that.
637 */
638 if (desc->pre_gmdid_graphics_ip) {
639 graphics_ip = desc->pre_gmdid_graphics_ip;
640 media_ip = desc->pre_gmdid_media_ip;
641 xe->info.step = xe_step_pre_gmdid_get(xe);
642 } else {
643 xe_assert(xe, !desc->pre_gmdid_media_ip);
644 handle_gmdid(xe, &graphics_ip, &media_ip,
645 &graphics_gmdid_revid, &media_gmdid_revid);
646 xe->info.step = xe_step_gmdid_get(xe,
647 graphics_gmdid_revid,
648 media_gmdid_revid);
649 }
650
651 /*
652 * If we couldn't detect the graphics IP, that's considered a fatal
653 * error and we should abort driver load. Failing to detect media
654 * IP is non-fatal; we'll just proceed without enabling media support.
655 */
656 if (!graphics_ip)
657 return -ENODEV;
658
659 xe->info.graphics_verx100 = graphics_ip->verx100;
660 xe->info.graphics_name = graphics_ip->name;
661 graphics_desc = graphics_ip->desc;
662
663 if (media_ip) {
664 xe->info.media_verx100 = media_ip->verx100;
665 xe->info.media_name = media_ip->name;
666 media_desc = media_ip->desc;
667 } else {
668 xe->info.media_name = "none";
669 media_desc = NULL;
670 }
671
672 xe->info.vram_flags = graphics_desc->vram_flags;
673 xe->info.va_bits = graphics_desc->va_bits;
674 xe->info.vm_max_level = graphics_desc->vm_max_level;
675 xe->info.has_asid = graphics_desc->has_asid;
676 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
677 if (xe->info.platform != XE_PVC)
678 xe->info.has_device_atomics_on_smem = 1;
679
680 /* Runtime detection may change this later */
681 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
682
683 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation;
684 xe->info.has_usm = graphics_desc->has_usm;
685 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
686
687 for_each_remote_tile(tile, xe, id) {
688 int err;
689
690 err = xe_tile_init_early(tile, xe, id);
691 if (err)
692 return err;
693 }
694
695 /*
696 * All platforms have at least one primary GT. Any platform with media
697 * version 13 or higher has an additional dedicated media GT. And
698 * depending on the graphics IP there may be additional "remote tiles."
699 * All of these together determine the overall GT count.
700 */
701 for_each_tile(tile, xe, id) {
702 gt = tile->primary_gt;
703 gt->info.id = xe->info.gt_count++;
704 gt->info.type = XE_GT_TYPE_MAIN;
705 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
706 gt->info.engine_mask = graphics_desc->hw_engine_mask;
707
708 if (MEDIA_VER(xe) < 13 && media_desc)
709 gt->info.engine_mask |= media_desc->hw_engine_mask;
710
711 if (MEDIA_VER(xe) < 13 || !media_desc)
712 continue;
713
714 /*
715 * Allocate and setup media GT for platforms with standalone
716 * media.
717 */
718 tile->media_gt = xe_gt_alloc(tile);
719 if (IS_ERR(tile->media_gt))
720 return PTR_ERR(tile->media_gt);
721
722 gt = tile->media_gt;
723 gt->info.type = XE_GT_TYPE_MEDIA;
724 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
725 gt->info.engine_mask = media_desc->hw_engine_mask;
726
727 /*
728 * FIXME: At the moment multi-tile and standalone media are
729 * mutually exclusive on current platforms. We'll need to
730 * come up with a better way to number GTs if we ever wind
731 * up with platforms that support both together.
732 */
733 drm_WARN_ON(&xe->drm, id != 0);
734 gt->info.id = xe->info.gt_count++;
735 }
736
737 return 0;
738 }
739
xe_pci_remove(struct pci_dev * pdev)740 static void xe_pci_remove(struct pci_dev *pdev)
741 {
742 struct xe_device *xe = pdev_to_xe_device(pdev);
743
744 if (IS_SRIOV_PF(xe))
745 xe_pci_sriov_configure(pdev, 0);
746
747 if (xe_survivability_mode_is_enabled(xe))
748 return;
749
750 xe_device_remove(xe);
751 xe_pm_fini(xe);
752 }
753
754 /*
755 * Probe the PCI device, initialize various parts of the driver.
756 *
757 * Fault injection is used to test the error paths of some initialization
758 * functions called either directly from xe_pci_probe() or indirectly for
759 * example through xe_device_probe(). Those functions use the kernel fault
760 * injection capabilities infrastructure, see
761 * Documentation/fault-injection/fault-injection.rst for details. The macro
762 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution
763 * at runtime and use a provided return value. The first requirement for
764 * error injectable functions is proper handling of the error code by the
765 * caller for recovery, which is always the case here. The second
766 * requirement is that no state is changed before the first error return.
767 * It is not strictly fulfilled for all initialization functions using the
768 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those
769 * error cases at probe time, the error code is simply propagated up by the
770 * caller. Therefore there is no consequence on those specific callers when
771 * function error injection skips the whole function.
772 */
xe_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)773 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
774 {
775 const struct xe_device_desc *desc = (const void *)ent->driver_data;
776 const struct xe_subplatform_desc *subplatform_desc;
777 struct xe_device *xe;
778 int err;
779
780 if (desc->require_force_probe && !id_forced(pdev->device)) {
781 dev_info(&pdev->dev,
782 "Your graphics device %04x is not officially supported\n"
783 "by xe driver in this kernel version. To force Xe probe,\n"
784 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
785 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
786 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
787 pdev->device, pdev->device, pdev->device,
788 pdev->device, pdev->device);
789 return -ENODEV;
790 }
791
792 if (id_blocked(pdev->device)) {
793 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
794 pdev->vendor, pdev->device);
795 return -ENODEV;
796 }
797
798 if (xe_display_driver_probe_defer(pdev))
799 return -EPROBE_DEFER;
800
801 err = pcim_enable_device(pdev);
802 if (err)
803 return err;
804
805 xe = xe_device_create(pdev, ent);
806 if (IS_ERR(xe))
807 return PTR_ERR(xe);
808
809 pci_set_drvdata(pdev, &xe->drm);
810
811 xe_pm_assert_unbounded_bridge(xe);
812 subplatform_desc = find_subplatform(xe, desc);
813
814 pci_set_master(pdev);
815
816 err = xe_info_init_early(xe, desc, subplatform_desc);
817 if (err)
818 return err;
819
820 err = xe_device_probe_early(xe);
821 /*
822 * In Boot Survivability mode, no drm card is exposed and driver
823 * is loaded with bare minimum to allow for firmware to be
824 * flashed through mei. Return success, if survivability mode
825 * is enabled due to pcode failure or configfs being set
826 */
827 if (xe_survivability_mode_is_enabled(xe))
828 return 0;
829
830 if (err)
831 return err;
832
833 err = xe_info_init(xe, desc);
834 if (err)
835 return err;
836
837 err = xe_display_probe(xe);
838 if (err)
839 return err;
840
841 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d",
842 desc->platform_name,
843 subplatform_desc ? subplatform_desc->name : "",
844 xe->info.devid, xe->info.revid,
845 xe->info.is_dgfx,
846 xe->info.graphics_name,
847 xe->info.graphics_verx100 / 100,
848 xe->info.graphics_verx100 % 100,
849 xe->info.media_name,
850 xe->info.media_verx100 / 100,
851 xe->info.media_verx100 % 100,
852 str_yes_no(xe->info.probe_display),
853 xe->info.dma_mask_size, xe->info.tile_count,
854 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
855
856 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
857 xe_step_name(xe->info.step.graphics),
858 xe_step_name(xe->info.step.media),
859 xe_step_name(xe->info.step.basedie));
860
861 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
862 str_yes_no(xe_device_has_sriov(xe)),
863 xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
864
865 err = xe_pm_init_early(xe);
866 if (err)
867 return err;
868
869 err = xe_device_probe(xe);
870 if (err)
871 return err;
872
873 err = xe_pm_init(xe);
874 if (err)
875 goto err_driver_cleanup;
876
877 drm_dbg(&xe->drm, "d3cold: capable=%s\n",
878 str_yes_no(xe->d3cold.capable));
879
880 return 0;
881
882 err_driver_cleanup:
883 xe_pci_remove(pdev);
884 return err;
885 }
886
xe_pci_shutdown(struct pci_dev * pdev)887 static void xe_pci_shutdown(struct pci_dev *pdev)
888 {
889 xe_device_shutdown(pdev_to_xe_device(pdev));
890 }
891
892 #ifdef CONFIG_PM_SLEEP
d3cold_toggle(struct pci_dev * pdev,enum toggle_d3cold toggle)893 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)
894 {
895 struct xe_device *xe = pdev_to_xe_device(pdev);
896 struct pci_dev *root_pdev;
897
898 if (!xe->d3cold.capable)
899 return;
900
901 root_pdev = pcie_find_root_port(pdev);
902 if (!root_pdev)
903 return;
904
905 switch (toggle) {
906 case D3COLD_DISABLE:
907 pci_d3cold_disable(root_pdev);
908 break;
909 case D3COLD_ENABLE:
910 pci_d3cold_enable(root_pdev);
911 break;
912 }
913 }
914
xe_pci_suspend(struct device * dev)915 static int xe_pci_suspend(struct device *dev)
916 {
917 struct pci_dev *pdev = to_pci_dev(dev);
918 struct xe_device *xe = pdev_to_xe_device(pdev);
919 int err;
920
921 if (xe_survivability_mode_is_enabled(xe))
922 return -EBUSY;
923
924 err = xe_pm_suspend(xe);
925 if (err)
926 return err;
927
928 /*
929 * Enabling D3Cold is needed for S2Idle/S0ix.
930 * It is save to allow here since xe_pm_suspend has evicted
931 * the local memory and the direct complete optimization is disabled.
932 */
933 d3cold_toggle(pdev, D3COLD_ENABLE);
934
935 pci_save_state(pdev);
936 pci_disable_device(pdev);
937 pci_set_power_state(pdev, PCI_D3cold);
938
939 return 0;
940 }
941
xe_pci_resume(struct device * dev)942 static int xe_pci_resume(struct device *dev)
943 {
944 struct pci_dev *pdev = to_pci_dev(dev);
945 int err;
946
947 /* Give back the D3Cold decision to the runtime P M*/
948 d3cold_toggle(pdev, D3COLD_DISABLE);
949
950 err = pci_set_power_state(pdev, PCI_D0);
951 if (err)
952 return err;
953
954 pci_restore_state(pdev);
955
956 err = pci_enable_device(pdev);
957 if (err)
958 return err;
959
960 pci_set_master(pdev);
961
962 err = xe_pm_resume(pdev_to_xe_device(pdev));
963 if (err)
964 return err;
965
966 return 0;
967 }
968
xe_pci_runtime_suspend(struct device * dev)969 static int xe_pci_runtime_suspend(struct device *dev)
970 {
971 struct pci_dev *pdev = to_pci_dev(dev);
972 struct xe_device *xe = pdev_to_xe_device(pdev);
973 int err;
974
975 err = xe_pm_runtime_suspend(xe);
976 if (err)
977 return err;
978
979 pci_save_state(pdev);
980
981 if (xe->d3cold.allowed) {
982 d3cold_toggle(pdev, D3COLD_ENABLE);
983 pci_disable_device(pdev);
984 pci_ignore_hotplug(pdev);
985 pci_set_power_state(pdev, PCI_D3cold);
986 } else {
987 d3cold_toggle(pdev, D3COLD_DISABLE);
988 pci_set_power_state(pdev, PCI_D3hot);
989 }
990
991 return 0;
992 }
993
xe_pci_runtime_resume(struct device * dev)994 static int xe_pci_runtime_resume(struct device *dev)
995 {
996 struct pci_dev *pdev = to_pci_dev(dev);
997 struct xe_device *xe = pdev_to_xe_device(pdev);
998 int err;
999
1000 err = pci_set_power_state(pdev, PCI_D0);
1001 if (err)
1002 return err;
1003
1004 pci_restore_state(pdev);
1005
1006 if (xe->d3cold.allowed) {
1007 err = pci_enable_device(pdev);
1008 if (err)
1009 return err;
1010
1011 pci_set_master(pdev);
1012 }
1013
1014 return xe_pm_runtime_resume(xe);
1015 }
1016
xe_pci_runtime_idle(struct device * dev)1017 static int xe_pci_runtime_idle(struct device *dev)
1018 {
1019 struct pci_dev *pdev = to_pci_dev(dev);
1020 struct xe_device *xe = pdev_to_xe_device(pdev);
1021
1022 xe_pm_d3cold_allowed_toggle(xe);
1023
1024 return 0;
1025 }
1026
1027 static const struct dev_pm_ops xe_pm_ops = {
1028 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)
1029 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)
1030 };
1031 #endif
1032
1033 static struct pci_driver xe_pci_driver = {
1034 .name = DRIVER_NAME,
1035 .id_table = pciidlist,
1036 .probe = xe_pci_probe,
1037 .remove = xe_pci_remove,
1038 .shutdown = xe_pci_shutdown,
1039 .sriov_configure = xe_pci_sriov_configure,
1040 #ifdef CONFIG_PM_SLEEP
1041 .driver.pm = &xe_pm_ops,
1042 #endif
1043 };
1044
xe_register_pci_driver(void)1045 int xe_register_pci_driver(void)
1046 {
1047 return pci_register_driver(&xe_pci_driver);
1048 }
1049
xe_unregister_pci_driver(void)1050 void xe_unregister_pci_driver(void)
1051 {
1052 pci_unregister_driver(&xe_pci_driver);
1053 }
1054
1055 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
1056 #include "tests/xe_pci.c"
1057 #endif
1058