1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <drm/drm_managed.h> 11 #include <uapi/drm/xe_drm.h> 12 13 #include <generated/xe_wa_oob.h> 14 15 #include "instructions/xe_gfxpipe_commands.h" 16 #include "instructions/xe_mi_commands.h" 17 #include "regs/xe_gt_regs.h" 18 #include "xe_assert.h" 19 #include "xe_bb.h" 20 #include "xe_bo.h" 21 #include "xe_device.h" 22 #include "xe_exec_queue.h" 23 #include "xe_execlist.h" 24 #include "xe_force_wake.h" 25 #include "xe_ggtt.h" 26 #include "xe_gsc.h" 27 #include "xe_gt_ccs_mode.h" 28 #include "xe_gt_clock.h" 29 #include "xe_gt_freq.h" 30 #include "xe_gt_idle.h" 31 #include "xe_gt_mcr.h" 32 #include "xe_gt_pagefault.h" 33 #include "xe_gt_printk.h" 34 #include "xe_gt_sriov_pf.h" 35 #include "xe_gt_sysfs.h" 36 #include "xe_gt_tlb_invalidation.h" 37 #include "xe_gt_topology.h" 38 #include "xe_guc_exec_queue_types.h" 39 #include "xe_guc_pc.h" 40 #include "xe_hw_fence.h" 41 #include "xe_hw_engine_class_sysfs.h" 42 #include "xe_irq.h" 43 #include "xe_lmtt.h" 44 #include "xe_lrc.h" 45 #include "xe_map.h" 46 #include "xe_migrate.h" 47 #include "xe_mmio.h" 48 #include "xe_pat.h" 49 #include "xe_pm.h" 50 #include "xe_mocs.h" 51 #include "xe_reg_sr.h" 52 #include "xe_ring_ops.h" 53 #include "xe_sa.h" 54 #include "xe_sched_job.h" 55 #include "xe_sriov.h" 56 #include "xe_tuning.h" 57 #include "xe_uc.h" 58 #include "xe_uc_fw.h" 59 #include "xe_vm.h" 60 #include "xe_wa.h" 61 #include "xe_wopcm.h" 62 63 static void gt_fini(struct drm_device *drm, void *arg) 64 { 65 struct xe_gt *gt = arg; 66 67 destroy_workqueue(gt->ordered_wq); 68 } 69 70 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 71 { 72 struct xe_gt *gt; 73 int err; 74 75 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); 76 if (!gt) 77 return ERR_PTR(-ENOMEM); 78 79 gt->tile = tile; 80 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0); 81 82 err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); 83 if (err) 84 return ERR_PTR(err); 85 86 return gt; 87 } 88 89 void xe_gt_sanitize(struct xe_gt *gt) 90 { 91 /* 92 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 93 * reload 94 */ 95 gt->uc.guc.submission_state.enabled = false; 96 } 97 98 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) 99 { 100 u32 reg; 101 int err; 102 103 if (!XE_WA(gt, 16023588340)) 104 return; 105 106 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 107 if (WARN_ON(err)) 108 return; 109 110 if (!xe_gt_is_media_type(gt)) { 111 xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH); 112 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 113 reg |= CG_DIS_CNTLBUS; 114 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 115 } 116 117 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3); 118 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 119 } 120 121 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) 122 { 123 u32 reg; 124 int err; 125 126 if (!XE_WA(gt, 16023588340)) 127 return; 128 129 if (xe_gt_is_media_type(gt)) 130 return; 131 132 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 133 if (WARN_ON(err)) 134 return; 135 136 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 137 reg &= ~CG_DIS_CNTLBUS; 138 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 139 140 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 141 } 142 143 /** 144 * xe_gt_remove() - Clean up the GT structures before driver removal 145 * @gt: the GT object 146 * 147 * This function should only act on objects/structures that must be cleaned 148 * before the driver removal callback is complete and therefore can't be 149 * deferred to a drmm action. 150 */ 151 void xe_gt_remove(struct xe_gt *gt) 152 { 153 int i; 154 155 xe_uc_remove(>->uc); 156 157 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 158 xe_hw_fence_irq_finish(>->fence_irq[i]); 159 160 xe_gt_disable_host_l2_vram(gt); 161 } 162 163 static void gt_reset_worker(struct work_struct *w); 164 165 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 166 { 167 struct xe_sched_job *job; 168 struct xe_bb *bb; 169 struct dma_fence *fence; 170 long timeout; 171 172 bb = xe_bb_new(gt, 4, false); 173 if (IS_ERR(bb)) 174 return PTR_ERR(bb); 175 176 job = xe_bb_create_job(q, bb); 177 if (IS_ERR(job)) { 178 xe_bb_free(bb, NULL); 179 return PTR_ERR(job); 180 } 181 182 xe_sched_job_arm(job); 183 fence = dma_fence_get(&job->drm.s_fence->finished); 184 xe_sched_job_push(job); 185 186 timeout = dma_fence_wait_timeout(fence, false, HZ); 187 dma_fence_put(fence); 188 xe_bb_free(bb, NULL); 189 if (timeout < 0) 190 return timeout; 191 else if (!timeout) 192 return -ETIME; 193 194 return 0; 195 } 196 197 /* 198 * Convert back from encoded value to type-safe, only to be used when reg.mcr 199 * is true 200 */ 201 static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg) 202 { 203 return (const struct xe_reg_mcr){.__reg.raw = reg.raw }; 204 } 205 206 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 207 { 208 struct xe_reg_sr *sr = &q->hwe->reg_lrc; 209 struct xe_reg_sr_entry *entry; 210 unsigned long idx; 211 struct xe_sched_job *job; 212 struct xe_bb *bb; 213 struct dma_fence *fence; 214 long timeout; 215 int count = 0; 216 217 if (q->hwe->class == XE_ENGINE_CLASS_RENDER) 218 /* Big enough to emit all of the context's 3DSTATE */ 219 bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false); 220 else 221 /* Just pick a large BB size */ 222 bb = xe_bb_new(gt, SZ_4K, false); 223 224 if (IS_ERR(bb)) 225 return PTR_ERR(bb); 226 227 xa_for_each(&sr->xa, idx, entry) 228 ++count; 229 230 if (count) { 231 xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); 232 233 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 234 235 xa_for_each(&sr->xa, idx, entry) { 236 struct xe_reg reg = entry->reg; 237 struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg); 238 u32 val; 239 240 /* 241 * Skip reading the register if it's not really needed 242 */ 243 if (reg.masked) 244 val = entry->clr_bits << 16; 245 else if (entry->clr_bits + 1) 246 val = (reg.mcr ? 247 xe_gt_mcr_unicast_read_any(gt, reg_mcr) : 248 xe_mmio_read32(gt, reg)) & (~entry->clr_bits); 249 else 250 val = 0; 251 252 val |= entry->set_bits; 253 254 bb->cs[bb->len++] = reg.addr; 255 bb->cs[bb->len++] = val; 256 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 257 } 258 } 259 260 xe_lrc_emit_hwe_state_instructions(q, bb); 261 262 job = xe_bb_create_job(q, bb); 263 if (IS_ERR(job)) { 264 xe_bb_free(bb, NULL); 265 return PTR_ERR(job); 266 } 267 268 xe_sched_job_arm(job); 269 fence = dma_fence_get(&job->drm.s_fence->finished); 270 xe_sched_job_push(job); 271 272 timeout = dma_fence_wait_timeout(fence, false, HZ); 273 dma_fence_put(fence); 274 xe_bb_free(bb, NULL); 275 if (timeout < 0) 276 return timeout; 277 else if (!timeout) 278 return -ETIME; 279 280 return 0; 281 } 282 283 int xe_gt_record_default_lrcs(struct xe_gt *gt) 284 { 285 struct xe_device *xe = gt_to_xe(gt); 286 struct xe_hw_engine *hwe; 287 enum xe_hw_engine_id id; 288 int err = 0; 289 290 for_each_hw_engine(hwe, gt, id) { 291 struct xe_exec_queue *q, *nop_q; 292 void *default_lrc; 293 294 if (gt->default_lrc[hwe->class]) 295 continue; 296 297 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe); 298 xe_wa_process_lrc(hwe); 299 xe_hw_engine_setup_default_lrc_state(hwe); 300 xe_tuning_process_lrc(hwe); 301 302 default_lrc = drmm_kzalloc(&xe->drm, 303 xe_gt_lrc_size(gt, hwe->class), 304 GFP_KERNEL); 305 if (!default_lrc) 306 return -ENOMEM; 307 308 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 309 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 310 if (IS_ERR(q)) { 311 err = PTR_ERR(q); 312 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 313 hwe->name, q); 314 return err; 315 } 316 317 /* Prime golden LRC with known good state */ 318 err = emit_wa_job(gt, q); 319 if (err) { 320 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 321 hwe->name, ERR_PTR(err), q->guc->id); 322 goto put_exec_queue; 323 } 324 325 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 326 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 327 if (IS_ERR(nop_q)) { 328 err = PTR_ERR(nop_q); 329 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 330 hwe->name, nop_q); 331 goto put_exec_queue; 332 } 333 334 /* Switch to different LRC */ 335 err = emit_nop_job(gt, nop_q); 336 if (err) { 337 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 338 hwe->name, ERR_PTR(err), nop_q->guc->id); 339 goto put_nop_q; 340 } 341 342 /* Reload golden LRC to record the effect of any indirect W/A */ 343 err = emit_nop_job(gt, q); 344 if (err) { 345 xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", 346 hwe->name, ERR_PTR(err), q->guc->id); 347 goto put_nop_q; 348 } 349 350 xe_map_memcpy_from(xe, default_lrc, 351 &q->lrc[0]->bo->vmap, 352 xe_lrc_pphwsp_offset(q->lrc[0]), 353 xe_gt_lrc_size(gt, hwe->class)); 354 355 gt->default_lrc[hwe->class] = default_lrc; 356 put_nop_q: 357 xe_exec_queue_put(nop_q); 358 put_exec_queue: 359 xe_exec_queue_put(q); 360 if (err) 361 break; 362 } 363 364 return err; 365 } 366 367 int xe_gt_init_early(struct xe_gt *gt) 368 { 369 int err; 370 371 if (IS_SRIOV_PF(gt_to_xe(gt))) { 372 err = xe_gt_sriov_pf_init_early(gt); 373 if (err) 374 return err; 375 } 376 377 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 378 379 err = xe_wa_init(gt); 380 if (err) 381 return err; 382 383 xe_wa_process_gt(gt); 384 xe_wa_process_oob(gt); 385 xe_tuning_process_gt(gt); 386 387 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 388 spin_lock_init(>->global_invl_lock); 389 390 return 0; 391 } 392 393 static void dump_pat_on_error(struct xe_gt *gt) 394 { 395 struct drm_printer p; 396 char prefix[32]; 397 398 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 399 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 400 401 xe_pat_dump(gt, &p); 402 } 403 404 static int gt_fw_domain_init(struct xe_gt *gt) 405 { 406 int err, i; 407 408 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 409 if (err) 410 goto err_hw_fence_irq; 411 412 if (!xe_gt_is_media_type(gt)) { 413 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 414 if (err) 415 goto err_force_wake; 416 if (IS_SRIOV_PF(gt_to_xe(gt))) 417 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 418 } 419 420 /* Enable per hw engine IRQs */ 421 xe_irq_enable_hwe(gt); 422 423 /* Rerun MCR init as we now have hw engine list */ 424 xe_gt_mcr_init(gt); 425 426 err = xe_hw_engines_init_early(gt); 427 if (err) 428 goto err_force_wake; 429 430 err = xe_hw_engine_class_sysfs_init(gt); 431 if (err) 432 goto err_force_wake; 433 434 /* Initialize CCS mode sysfs after early initialization of HW engines */ 435 err = xe_gt_ccs_mode_sysfs_init(gt); 436 if (err) 437 goto err_force_wake; 438 439 /* 440 * Stash hardware-reported version. Since this register does not exist 441 * on pre-MTL platforms, reading it there will (correctly) return 0. 442 */ 443 gt->info.gmdid = xe_mmio_read32(gt, GMD_ID); 444 445 err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 446 XE_WARN_ON(err); 447 448 return 0; 449 450 err_force_wake: 451 dump_pat_on_error(gt); 452 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 453 err_hw_fence_irq: 454 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 455 xe_hw_fence_irq_finish(>->fence_irq[i]); 456 457 return err; 458 } 459 460 static int all_fw_domain_init(struct xe_gt *gt) 461 { 462 int err, i; 463 464 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 465 if (err) 466 goto err_hw_fence_irq; 467 468 xe_gt_mcr_set_implicit_defaults(gt); 469 xe_reg_sr_apply_mmio(>->reg_sr, gt); 470 471 err = xe_gt_clock_init(gt); 472 if (err) 473 goto err_force_wake; 474 475 xe_mocs_init(gt); 476 err = xe_execlist_init(gt); 477 if (err) 478 goto err_force_wake; 479 480 err = xe_hw_engines_init(gt); 481 if (err) 482 goto err_force_wake; 483 484 err = xe_uc_init_post_hwconfig(>->uc); 485 if (err) 486 goto err_force_wake; 487 488 if (!xe_gt_is_media_type(gt)) { 489 /* 490 * USM has its only SA pool to non-block behind user operations 491 */ 492 if (gt_to_xe(gt)->info.has_usm) { 493 struct xe_device *xe = gt_to_xe(gt); 494 495 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 496 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 497 if (IS_ERR(gt->usm.bb_pool)) { 498 err = PTR_ERR(gt->usm.bb_pool); 499 goto err_force_wake; 500 } 501 } 502 } 503 504 if (!xe_gt_is_media_type(gt)) { 505 struct xe_tile *tile = gt_to_tile(gt); 506 507 tile->migrate = xe_migrate_init(tile); 508 if (IS_ERR(tile->migrate)) { 509 err = PTR_ERR(tile->migrate); 510 goto err_force_wake; 511 } 512 } 513 514 err = xe_uc_init_hw(>->uc); 515 if (err) 516 goto err_force_wake; 517 518 /* Configure default CCS mode of 1 engine with all resources */ 519 if (xe_gt_ccs_mode_enabled(gt)) { 520 gt->ccs_mode = 1; 521 xe_gt_apply_ccs_mode(gt); 522 } 523 524 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 525 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 526 527 if (IS_SRIOV_PF(gt_to_xe(gt))) 528 xe_gt_sriov_pf_init_hw(gt); 529 530 err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 531 XE_WARN_ON(err); 532 533 return 0; 534 535 err_force_wake: 536 xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 537 err_hw_fence_irq: 538 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 539 xe_hw_fence_irq_finish(>->fence_irq[i]); 540 541 return err; 542 } 543 544 /* 545 * Initialize enough GT to be able to load GuC in order to obtain hwconfig and 546 * enable CTB communication. 547 */ 548 int xe_gt_init_hwconfig(struct xe_gt *gt) 549 { 550 int err; 551 552 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 553 if (err) 554 goto out; 555 556 xe_gt_mcr_init_early(gt); 557 xe_pat_init(gt); 558 559 err = xe_uc_init(>->uc); 560 if (err) 561 goto out_fw; 562 563 err = xe_uc_init_hwconfig(>->uc); 564 if (err) 565 goto out_fw; 566 567 xe_gt_topology_init(gt); 568 xe_gt_mcr_init(gt); 569 xe_gt_enable_host_l2_vram(gt); 570 571 out_fw: 572 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 573 out: 574 return err; 575 } 576 577 int xe_gt_init(struct xe_gt *gt) 578 { 579 int err; 580 int i; 581 582 INIT_WORK(>->reset.worker, gt_reset_worker); 583 584 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 585 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 586 xe_hw_fence_irq_init(>->fence_irq[i]); 587 } 588 589 err = xe_gt_tlb_invalidation_init(gt); 590 if (err) 591 return err; 592 593 err = xe_gt_pagefault_init(gt); 594 if (err) 595 return err; 596 597 xe_mocs_init_early(gt); 598 599 err = xe_gt_sysfs_init(gt); 600 if (err) 601 return err; 602 603 err = gt_fw_domain_init(gt); 604 if (err) 605 return err; 606 607 err = xe_gt_idle_init(>->gtidle); 608 if (err) 609 return err; 610 611 err = xe_gt_freq_init(gt); 612 if (err) 613 return err; 614 615 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 616 617 err = all_fw_domain_init(gt); 618 if (err) 619 return err; 620 621 xe_gt_record_user_engines(gt); 622 623 return 0; 624 } 625 626 void xe_gt_record_user_engines(struct xe_gt *gt) 627 { 628 struct xe_hw_engine *hwe; 629 enum xe_hw_engine_id id; 630 631 gt->user_engines.mask = 0; 632 memset(gt->user_engines.instances_per_class, 0, 633 sizeof(gt->user_engines.instances_per_class)); 634 635 for_each_hw_engine(hwe, gt, id) { 636 if (xe_hw_engine_is_reserved(hwe)) 637 continue; 638 639 gt->user_engines.mask |= BIT_ULL(id); 640 gt->user_engines.instances_per_class[hwe->class]++; 641 } 642 643 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 644 == gt->info.engine_mask); 645 } 646 647 static int do_gt_reset(struct xe_gt *gt) 648 { 649 int err; 650 651 xe_gsc_wa_14015076503(gt, true); 652 653 xe_mmio_write32(gt, GDRST, GRDOM_FULL); 654 err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 655 if (err) 656 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 657 ERR_PTR(err)); 658 659 xe_gsc_wa_14015076503(gt, false); 660 661 return err; 662 } 663 664 static int vf_gt_restart(struct xe_gt *gt) 665 { 666 int err; 667 668 err = xe_uc_sanitize_reset(>->uc); 669 if (err) 670 return err; 671 672 err = xe_uc_init_hw(>->uc); 673 if (err) 674 return err; 675 676 err = xe_uc_start(>->uc); 677 if (err) 678 return err; 679 680 return 0; 681 } 682 683 static int do_gt_restart(struct xe_gt *gt) 684 { 685 struct xe_hw_engine *hwe; 686 enum xe_hw_engine_id id; 687 int err; 688 689 if (IS_SRIOV_VF(gt_to_xe(gt))) 690 return vf_gt_restart(gt); 691 692 xe_pat_init(gt); 693 694 xe_gt_enable_host_l2_vram(gt); 695 696 xe_gt_mcr_set_implicit_defaults(gt); 697 xe_reg_sr_apply_mmio(>->reg_sr, gt); 698 699 err = xe_wopcm_init(>->uc.wopcm); 700 if (err) 701 return err; 702 703 for_each_hw_engine(hwe, gt, id) 704 xe_hw_engine_enable_ring(hwe); 705 706 err = xe_uc_sanitize_reset(>->uc); 707 if (err) 708 return err; 709 710 err = xe_uc_init_hw(>->uc); 711 if (err) 712 return err; 713 714 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 715 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 716 717 if (IS_SRIOV_PF(gt_to_xe(gt))) 718 xe_gt_sriov_pf_init_hw(gt); 719 720 xe_mocs_init(gt); 721 err = xe_uc_start(>->uc); 722 if (err) 723 return err; 724 725 for_each_hw_engine(hwe, gt, id) { 726 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 727 xe_reg_sr_apply_whitelist(hwe); 728 } 729 730 /* Get CCS mode in sync between sw/hw */ 731 xe_gt_apply_ccs_mode(gt); 732 733 /* Restore GT freq to expected values */ 734 xe_gt_sanitize_freq(gt); 735 736 if (IS_SRIOV_PF(gt_to_xe(gt))) 737 xe_gt_sriov_pf_restart(gt); 738 739 return 0; 740 } 741 742 static int gt_reset(struct xe_gt *gt) 743 { 744 int err; 745 746 if (xe_device_wedged(gt_to_xe(gt))) 747 return -ECANCELED; 748 749 /* We only support GT resets with GuC submission */ 750 if (!xe_device_uc_enabled(gt_to_xe(gt))) 751 return -ENODEV; 752 753 xe_gt_info(gt, "reset started\n"); 754 755 xe_pm_runtime_get(gt_to_xe(gt)); 756 757 if (xe_fault_inject_gt_reset()) { 758 err = -ECANCELED; 759 goto err_fail; 760 } 761 762 xe_gt_sanitize(gt); 763 764 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 765 if (err) 766 goto err_msg; 767 768 xe_uc_gucrc_disable(>->uc); 769 xe_uc_stop_prepare(>->uc); 770 xe_gt_pagefault_reset(gt); 771 772 xe_uc_stop(>->uc); 773 774 xe_gt_tlb_invalidation_reset(gt); 775 776 err = do_gt_reset(gt); 777 if (err) 778 goto err_out; 779 780 err = do_gt_restart(gt); 781 if (err) 782 goto err_out; 783 784 err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 785 XE_WARN_ON(err); 786 xe_pm_runtime_put(gt_to_xe(gt)); 787 788 xe_gt_info(gt, "reset done\n"); 789 790 return 0; 791 792 err_out: 793 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 794 err_msg: 795 XE_WARN_ON(xe_uc_start(>->uc)); 796 err_fail: 797 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 798 799 xe_device_declare_wedged(gt_to_xe(gt)); 800 xe_pm_runtime_put(gt_to_xe(gt)); 801 802 return err; 803 } 804 805 static void gt_reset_worker(struct work_struct *w) 806 { 807 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 808 809 gt_reset(gt); 810 } 811 812 void xe_gt_reset_async(struct xe_gt *gt) 813 { 814 xe_gt_info(gt, "trying reset\n"); 815 816 /* Don't do a reset while one is already in flight */ 817 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc)) 818 return; 819 820 xe_gt_info(gt, "reset queued\n"); 821 queue_work(gt->ordered_wq, >->reset.worker); 822 } 823 824 void xe_gt_suspend_prepare(struct xe_gt *gt) 825 { 826 XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 827 828 xe_uc_stop_prepare(>->uc); 829 830 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 831 } 832 833 int xe_gt_suspend(struct xe_gt *gt) 834 { 835 int err; 836 837 xe_gt_dbg(gt, "suspending\n"); 838 xe_gt_sanitize(gt); 839 840 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 841 if (err) 842 goto err_msg; 843 844 err = xe_uc_suspend(>->uc); 845 if (err) 846 goto err_force_wake; 847 848 xe_gt_idle_disable_pg(gt); 849 850 xe_gt_disable_host_l2_vram(gt); 851 852 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 853 xe_gt_dbg(gt, "suspended\n"); 854 855 return 0; 856 857 err_force_wake: 858 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 859 err_msg: 860 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 861 862 return err; 863 } 864 865 /** 866 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 867 * @gt: the GT object 868 * 869 * Called after driver init/GSC load completes to restore GT frequencies if we 870 * limited them for any WAs. 871 */ 872 int xe_gt_sanitize_freq(struct xe_gt *gt) 873 { 874 int ret = 0; 875 876 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 877 xe_uc_fw_is_loaded(>->uc.gsc.fw)) && XE_WA(gt, 22019338487)) 878 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 879 880 return ret; 881 } 882 883 int xe_gt_resume(struct xe_gt *gt) 884 { 885 int err; 886 887 xe_gt_dbg(gt, "resuming\n"); 888 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 889 if (err) 890 goto err_msg; 891 892 err = do_gt_restart(gt); 893 if (err) 894 goto err_force_wake; 895 896 xe_gt_idle_enable_pg(gt); 897 898 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 899 xe_gt_dbg(gt, "resumed\n"); 900 901 return 0; 902 903 err_force_wake: 904 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 905 err_msg: 906 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err)); 907 908 return err; 909 } 910 911 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 912 enum xe_engine_class class, 913 u16 instance, bool logical) 914 { 915 struct xe_hw_engine *hwe; 916 enum xe_hw_engine_id id; 917 918 for_each_hw_engine(hwe, gt, id) 919 if (hwe->class == class && 920 ((!logical && hwe->instance == instance) || 921 (logical && hwe->logical_instance == instance))) 922 return hwe; 923 924 return NULL; 925 } 926 927 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 928 enum xe_engine_class class) 929 { 930 struct xe_hw_engine *hwe; 931 enum xe_hw_engine_id id; 932 933 for_each_hw_engine(hwe, gt, id) { 934 switch (class) { 935 case XE_ENGINE_CLASS_RENDER: 936 case XE_ENGINE_CLASS_COMPUTE: 937 if (hwe->class == XE_ENGINE_CLASS_RENDER || 938 hwe->class == XE_ENGINE_CLASS_COMPUTE) 939 return hwe; 940 break; 941 default: 942 if (hwe->class == class) 943 return hwe; 944 } 945 } 946 947 return NULL; 948 } 949 950 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 951 { 952 struct xe_hw_engine *hwe; 953 enum xe_hw_engine_id id; 954 955 for_each_hw_engine(hwe, gt, id) 956 return hwe; 957 958 return NULL; 959 } 960 961 /** 962 * xe_gt_declare_wedged() - Declare GT wedged 963 * @gt: the GT object 964 * 965 * Wedge the GT which stops all submission, saves desired debug state, and 966 * cleans up anything which could timeout. 967 */ 968 void xe_gt_declare_wedged(struct xe_gt *gt) 969 { 970 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 971 972 xe_uc_declare_wedged(>->uc); 973 xe_gt_tlb_invalidation_reset(gt); 974 } 975