1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1998-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SCAT_ASICBRD_TYPES_H 28 #define _SCAT_ASICBRD_TYPES_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * This file contains enumerations of the board and asic types used 34 * in Starcat. 35 */ 36 37 /* 38 * POST DEVELOPERS: 39 * This file is copied to the OS workspace, and thus must abide by the OS 40 * coding standards. This file must always pass cstyle and hdrchk. 41 */ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 48 /* Enumeration of Starcat positional board types: */ 49 typedef enum { 50 XCBT_SYS0 = 0, /* Full-slot system board, e.g., CPU */ 51 XCBT_SYS1 = 1, /* Half-slot system board, e,g., I/O */ 52 XCBT_EXB = 2, /* Expander board */ 53 XCBT_CSB = 3, /* Centerplane support board */ 54 XCBT_CP = 4, /* Half-centerplane */ 55 XCBT_SC = 5, /* System controller */ 56 57 XCBT_COUNT /* Size of array */ 58 } xcbrdtype_t; 59 #define IS_VALID_XCBT(xcbt) \ 60 ((((int)(xcbt)) >= 0) && (((int)(xcbt)) < (int)XCBT_COUNT)) 61 62 /* Enumeration of Starcat L1 system board types */ 63 typedef enum { 64 XCL1BT_CPU, /* Slot 0. Four CPUs, memory */ 65 XCL1BT_WIB, /* Slot 0. Two CPUs & mem, two WCIs */ 66 XCL1BT_hPCI, /* Slot 1. Two Schizos. "Hotplug PCI" */ 67 XCL1BT_cPCI, /* Slot 1. Two Schizos. */ 68 XCL1BT_MAXCAT, /* Slot 1. Two CPUs, no memory */ 69 XCL1BT_WIBPCI, /* Slot 1, hybrid hPCI / WCI */ 70 XCL1BT_sPCI, /* Slot 1. Two Schizos. "Standard PCI" */ 71 72 XCL1BT_COUNT 73 } xcl1bt_t; 74 #define IS_VALID_XCL1BT(l1bt) \ 75 ((((int)(l1bt)) >= 0) && (((int)(l1bt)) < (int)XCL1BT_COUNT)) 76 77 78 /* 79 * Arbitrarily chosen enumeration for the Starcat asics, so we 80 * can build some tables & bitmasks. Make sure any changes are 81 * reflected in the initialization of xc_asic_name[] in libxcpost. 82 */ 83 typedef enum { 84 XCASICT_AXQ, 85 XCASICT_SDI, 86 XCASICT_AMX, 87 XCASICT_RMX, 88 XCASICT_DARB, 89 XCASICT_DMX, 90 XCASICT_CSBCBR, /* Mode of SDI CSB Console Bus Repeater */ 91 XCASICT_EXBCBR, /* Mode of SDI EXB Console Bus Repeater */ 92 93 XCASICT_AR, 94 XCASICT_DX, 95 XCASICT_SDC, 96 XCASICT_DCDS, 97 XCASICT_L1EPLD, 98 99 XCASICT_L1BBC, 100 XCASICT_EXBBBC, 101 XCASICT_CSBBBC, 102 103 XCASICT_CPU, 104 XCASICT_RIO, 105 XCASICT_SCHIZO, 106 XCASICT_WCI, 107 108 XCASICT_CBH, 109 XCASICT_SCM, 110 111 XCASICT_COUNT /* Size of array */ 112 } xcasictype_t; 113 #define IS_VALID_XCASICT(asict) \ 114 ((((int)(asict)) >= 0) && (((int)(asict)) < (int)XCASICT_COUNT)) 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* !_SCAT_ASICBRD_TYPES_H */ 121