1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Semihalf.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/lock.h>
33 #include <sys/mutex.h>
34 #include <sys/smp.h>
35
36 #include <vm/vm.h>
37 #include <vm/vm_kern.h>
38 #include <vm/vm_extern.h>
39 #include <vm/pmap.h>
40
41 #include <dev/fdt/fdt_common.h>
42
43 #include <machine/cpu.h>
44 #include <machine/smp.h>
45 #include <machine/fdt.h>
46 #include <machine/armreg.h>
47
48 #include <arm/mv/mvwin.h>
49 #include <arm/mv/mvvar.h>
50
51 #include <machine/platformvar.h>
52
53 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700)
54 #define CPU_DIVCLK_CTRL0 0x00
55 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08
56 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c
57 #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x))))
58
59 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x)))
60 #define CPU_PMU_BOOT 0x24
61
62 #define MP (MV_BASE + 0x20800)
63 #define MP_SW_RESET(x) ((x) * 8)
64
65 #define CPU_RESUME_CONTROL (0x20988)
66
67 void armadaxp_init_coher_fabric(void);
68 int platform_get_ncpus(void);
69
70 void mv_axp_platform_mp_setmaxid(platform_t plat);
71 void mv_axp_platform_mp_start_ap(platform_t plat);
72
73 /* Coherency Fabric registers */
74 static uint32_t
read_cpu_clkdiv(uint32_t reg)75 read_cpu_clkdiv(uint32_t reg)
76 {
77
78 return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg));
79 }
80
81 static void
write_cpu_clkdiv(uint32_t reg,uint32_t val)82 write_cpu_clkdiv(uint32_t reg, uint32_t val)
83 {
84
85 bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val);
86 }
87
88 void
mv_axp_platform_mp_setmaxid(platform_t plat)89 mv_axp_platform_mp_setmaxid(platform_t plat)
90 {
91
92 mp_ncpus = platform_get_ncpus();
93 mp_maxid = mp_ncpus - 1;
94 }
95
96 void mptramp(void);
97 void mptramp_end(void);
98 extern vm_offset_t mptramp_pmu_boot;
99
100 void
mv_axp_platform_mp_start_ap(platform_t plat)101 mv_axp_platform_mp_start_ap(platform_t plat)
102 {
103 uint32_t reg, *src, *dst, cpu_num, div_val, cputype;
104 vm_offset_t pmu_boot_off;
105 /*
106 * Initialization procedure depends on core revision,
107 * in this step CHIP ID is checked to choose proper procedure
108 */
109 cputype = cp15_midr_get();
110 cputype &= CPU_ID_CPU_MASK;
111
112 /*
113 * Set the PA of CPU0 Boot Address Redirect register used in
114 * mptramp according to the actual SoC registers' base address.
115 */
116 pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT;
117 mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off;
118 dst = pmap_mapdev(0xffff0000, PAGE_SIZE);
119 for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end;
120 src++, dst++) {
121 *dst = *src;
122 }
123 pmap_unmapdev(dst, PAGE_SIZE);
124 if (cputype == CPU_ID_MV88SV584X_V7) {
125 /* Core rev A0 */
126 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
127 div_val &= 0x3f;
128
129 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) {
130 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
131 reg &= CPU_DIVCLK_MASK(cpu_num);
132 reg |= div_val << (cpu_num * 8);
133 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
134 }
135 } else {
136 /* Core rev Z1 */
137 div_val = 0x01;
138
139 if (mp_ncpus > 1) {
140 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);
141 reg &= CPU_DIVCLK_MASK(3);
142 reg |= div_val << 24;
143 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);
144 }
145
146 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) {
147 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
148 reg &= CPU_DIVCLK_MASK(cpu_num);
149 reg |= div_val << (cpu_num * 8);
150 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
151 }
152 }
153
154 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
155 reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;
156 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
157 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
158 reg |= 0x01000000;
159 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
160
161 DELAY(100);
162 reg &= ~(0xf << 21);
163 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
164 DELAY(100);
165
166 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);
167
168 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
169 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
170 pmap_kextract((vm_offset_t)mpentry));
171
172 dcache_wbinv_poc_all();
173
174 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
175 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
176
177 /* XXX: Temporary workaround for hangup after releasing AP's */
178 wmb();
179 DELAY(10);
180
181 armadaxp_init_coher_fabric();
182 }
183