1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Clock implementation for VIA/Wondermedia SoC's
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 */
6
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10 #include <linux/slab.h>
11 #include <linux/bitops.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14
15 #define LEGACY_PMC_BASE 0xD8130000
16
17 /* All clocks share the same lock as none can be changed concurrently */
18 static DEFINE_SPINLOCK(_lock);
19
20 struct clk_device {
21 struct clk_hw hw;
22 void __iomem *div_reg;
23 unsigned int div_mask;
24 void __iomem *en_reg;
25 int en_bit;
26 spinlock_t *lock;
27 };
28
29 /*
30 * Add new PLL_TYPE_x definitions here as required. Use the first known model
31 * to support the new type as the name.
32 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
33 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
34 */
35
36 #define PLL_TYPE_VT8500 0
37 #define PLL_TYPE_WM8650 1
38 #define PLL_TYPE_WM8750 2
39 #define PLL_TYPE_WM8850 3
40
41 struct clk_pll {
42 struct clk_hw hw;
43 void __iomem *reg;
44 spinlock_t *lock;
45 int type;
46 };
47
48 static void __iomem *pmc_base;
49
vtwm_set_pmc_base(void)50 static __init void vtwm_set_pmc_base(void)
51 {
52 struct device_node *np =
53 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
54
55 if (np)
56 pmc_base = of_iomap(np, 0);
57 else
58 pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
59 of_node_put(np);
60
61 if (!pmc_base)
62 pr_err("%s:of_iomap(pmc) failed\n", __func__);
63 }
64
65 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
66
67 #define VT8500_PMC_BUSY_MASK 0x18
68
vt8500_pmc_wait_busy(void)69 static void vt8500_pmc_wait_busy(void)
70 {
71 while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
72 cpu_relax();
73 }
74
vt8500_dclk_enable(struct clk_hw * hw)75 static int vt8500_dclk_enable(struct clk_hw *hw)
76 {
77 struct clk_device *cdev = to_clk_device(hw);
78 u32 en_val;
79 unsigned long flags = 0;
80
81 spin_lock_irqsave(cdev->lock, flags);
82
83 en_val = readl(cdev->en_reg);
84 en_val |= BIT(cdev->en_bit);
85 writel(en_val, cdev->en_reg);
86
87 spin_unlock_irqrestore(cdev->lock, flags);
88 return 0;
89 }
90
vt8500_dclk_disable(struct clk_hw * hw)91 static void vt8500_dclk_disable(struct clk_hw *hw)
92 {
93 struct clk_device *cdev = to_clk_device(hw);
94 u32 en_val;
95 unsigned long flags = 0;
96
97 spin_lock_irqsave(cdev->lock, flags);
98
99 en_val = readl(cdev->en_reg);
100 en_val &= ~BIT(cdev->en_bit);
101 writel(en_val, cdev->en_reg);
102
103 spin_unlock_irqrestore(cdev->lock, flags);
104 }
105
vt8500_dclk_is_enabled(struct clk_hw * hw)106 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
107 {
108 struct clk_device *cdev = to_clk_device(hw);
109 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
110
111 return en_val ? 1 : 0;
112 }
113
vt8500_dclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)114 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
115 unsigned long parent_rate)
116 {
117 struct clk_device *cdev = to_clk_device(hw);
118 u32 div = readl(cdev->div_reg) & cdev->div_mask;
119
120 /* Special case for SDMMC devices */
121 if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
122 div = 64 * (div & 0x1f);
123
124 /* div == 0 is actually the highest divisor */
125 if (div == 0)
126 div = (cdev->div_mask + 1);
127
128 return parent_rate / div;
129 }
130
vt8500_dclk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)131 static int vt8500_dclk_determine_rate(struct clk_hw *hw,
132 struct clk_rate_request *req)
133 {
134 struct clk_device *cdev = to_clk_device(hw);
135 u32 divisor;
136
137 if (req->rate == 0)
138 return 0;
139
140 divisor = req->best_parent_rate / req->rate;
141
142 /* If prate / rate would be decimal, incr the divisor */
143 if (req->rate * divisor < req->best_parent_rate)
144 divisor++;
145
146 /*
147 * If this is a request for SDMMC we have to adjust the divisor
148 * when >31 to use the fixed predivisor
149 */
150 if ((cdev->div_mask == 0x3F) && (divisor > 31))
151 divisor = 64 * ((divisor / 64) + 1);
152
153 req->rate = req->best_parent_rate / divisor;
154
155 return 0;
156 }
157
vt8500_dclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)158 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
159 unsigned long parent_rate)
160 {
161 struct clk_device *cdev = to_clk_device(hw);
162 u32 divisor;
163 unsigned long flags = 0;
164
165 if (rate == 0)
166 return 0;
167
168 divisor = parent_rate / rate;
169
170 if (divisor == cdev->div_mask + 1)
171 divisor = 0;
172
173 /* SDMMC mask may need to be corrected before testing if its valid */
174 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
175 /*
176 * Bit 5 is a fixed /64 predivisor. If the requested divisor
177 * is >31 then correct for the fixed divisor being required.
178 */
179 divisor = 0x20 + (divisor / 64);
180 }
181
182 if (divisor > cdev->div_mask) {
183 pr_err("%s: invalid divisor for clock\n", __func__);
184 return -EINVAL;
185 }
186
187 spin_lock_irqsave(cdev->lock, flags);
188
189 vt8500_pmc_wait_busy();
190 writel(divisor, cdev->div_reg);
191 vt8500_pmc_wait_busy();
192
193 spin_unlock_irqrestore(cdev->lock, flags);
194
195 return 0;
196 }
197
198
199 static const struct clk_ops vt8500_gated_clk_ops = {
200 .enable = vt8500_dclk_enable,
201 .disable = vt8500_dclk_disable,
202 .is_enabled = vt8500_dclk_is_enabled,
203 };
204
205 static const struct clk_ops vt8500_divisor_clk_ops = {
206 .determine_rate = vt8500_dclk_determine_rate,
207 .set_rate = vt8500_dclk_set_rate,
208 .recalc_rate = vt8500_dclk_recalc_rate,
209 };
210
211 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
212 .enable = vt8500_dclk_enable,
213 .disable = vt8500_dclk_disable,
214 .is_enabled = vt8500_dclk_is_enabled,
215 .determine_rate = vt8500_dclk_determine_rate,
216 .set_rate = vt8500_dclk_set_rate,
217 .recalc_rate = vt8500_dclk_recalc_rate,
218 };
219
220 #define CLK_INIT_GATED BIT(0)
221 #define CLK_INIT_DIVISOR BIT(1)
222 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
223
vtwm_device_clk_init(struct device_node * node)224 static __init void vtwm_device_clk_init(struct device_node *node)
225 {
226 u32 en_reg, div_reg;
227 struct clk_hw *hw;
228 struct clk_device *dev_clk;
229 const char *clk_name = node->name;
230 const char *parent_name;
231 struct clk_init_data init;
232 int rc;
233 int clk_init_flags = 0;
234
235 if (!pmc_base)
236 vtwm_set_pmc_base();
237
238 dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
239 if (WARN_ON(!dev_clk))
240 return;
241
242 dev_clk->lock = &_lock;
243
244 rc = of_property_read_u32(node, "enable-reg", &en_reg);
245 if (!rc) {
246 dev_clk->en_reg = pmc_base + en_reg;
247 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
248 if (rc) {
249 pr_err("%s: enable-bit property required for gated clock\n",
250 __func__);
251 return;
252 }
253 clk_init_flags |= CLK_INIT_GATED;
254 }
255
256 rc = of_property_read_u32(node, "divisor-reg", &div_reg);
257 if (!rc) {
258 dev_clk->div_reg = pmc_base + div_reg;
259 /*
260 * use 0x1f as the default mask since it covers
261 * almost all the clocks and reduces dts properties
262 */
263 dev_clk->div_mask = 0x1f;
264
265 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
266 clk_init_flags |= CLK_INIT_DIVISOR;
267 }
268
269 of_property_read_string(node, "clock-output-names", &clk_name);
270
271 switch (clk_init_flags) {
272 case CLK_INIT_GATED:
273 init.ops = &vt8500_gated_clk_ops;
274 break;
275 case CLK_INIT_DIVISOR:
276 init.ops = &vt8500_divisor_clk_ops;
277 break;
278 case CLK_INIT_GATED_DIVISOR:
279 init.ops = &vt8500_gated_divisor_clk_ops;
280 break;
281 default:
282 pr_err("%s: Invalid clock description in device tree\n",
283 __func__);
284 kfree(dev_clk);
285 return;
286 }
287
288 init.name = clk_name;
289 init.flags = 0;
290 parent_name = of_clk_get_parent_name(node, 0);
291 init.parent_names = &parent_name;
292 init.num_parents = 1;
293
294 dev_clk->hw.init = &init;
295
296 hw = &dev_clk->hw;
297 rc = clk_hw_register(NULL, hw);
298 if (WARN_ON(rc)) {
299 kfree(dev_clk);
300 return;
301 }
302 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
303 clk_hw_register_clkdev(hw, clk_name, NULL);
304 }
305 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
306
307 /* PLL clock related functions */
308
309 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
310
311 /* Helper macros for PLL_VT8500 */
312 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
313 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
314
315 #define VT8500_BITS_TO_FREQ(r, m, d) \
316 ((r / d) * m)
317
318 #define VT8500_BITS_TO_VAL(m, d) \
319 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
320
321 /* Helper macros for PLL_WM8650 */
322 #define WM8650_PLL_MUL(x) (x & 0x3FF)
323 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
324
325 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
326 (r * m / (d1 * (1 << d2)))
327
328 #define WM8650_BITS_TO_VAL(m, d1, d2) \
329 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
330
331 /* Helper macros for PLL_WM8750 */
332 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
333 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
334
335 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
336 (r * (m+1) / ((d1+1) * (1 << d2)))
337
338 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \
339 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
340
341 /* Helper macros for PLL_WM8850 */
342 #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
343 #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
344
345 #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
346 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
347
348 #define WM8850_BITS_TO_VAL(m, d1, d2) \
349 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
350
vt8500_find_pll_bits(unsigned long rate,unsigned long parent_rate,u32 * multiplier,u32 * prediv)351 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
352 u32 *multiplier, u32 *prediv)
353 {
354 unsigned long tclk;
355
356 /* sanity check */
357 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
358 pr_err("%s: requested rate out of range\n", __func__);
359 *multiplier = 0;
360 *prediv = 1;
361 return -EINVAL;
362 }
363 if (rate <= parent_rate * 31)
364 /* use the prediv to double the resolution */
365 *prediv = 2;
366 else
367 *prediv = 1;
368
369 *multiplier = rate / (parent_rate / *prediv);
370 tclk = (parent_rate / *prediv) * *multiplier;
371
372 if (tclk != rate)
373 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
374 rate, tclk);
375
376 return 0;
377 }
378
379 /*
380 * M * parent [O1] => / P [O2] => / D [O3]
381 * Where O1 is 900MHz...3GHz;
382 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
383 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * Possible ranges (O3):
385 * D = 8: 37,5MHz...75MHz
386 * D = 4: 75MHz...150MHz
387 * D = 2: 150MHz...300MHz
388 * D = 1: 300MHz...600MHz
389 */
wm8650_find_pll_bits(unsigned long rate,unsigned long parent_rate,u32 * multiplier,u32 * divisor1,u32 * divisor2)390 static int wm8650_find_pll_bits(unsigned long rate,
391 unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
392 u32 *divisor2)
393 {
394 unsigned long O1, min_err, rate_err;
395
396 if (!parent_rate || (rate < 37500000) || (rate > 600000000))
397 return -EINVAL;
398
399 *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
400 rate <= 300000000 ? 1 : 0;
401 /*
402 * Divisor P cannot be calculated. Test all divisors and find where M
403 * will be as close as possible to the requested rate.
404 */
405 min_err = ULONG_MAX;
406 for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
407 O1 = rate * *divisor1 * (1 << (*divisor2));
408 rate_err = O1 % parent_rate;
409 if (rate_err < min_err) {
410 *multiplier = O1 / parent_rate;
411 if (rate_err == 0)
412 return 0;
413
414 min_err = rate_err;
415 }
416 }
417
418 if ((*multiplier < 3) || (*multiplier > 1023))
419 return -EINVAL;
420
421 pr_warn("%s: rate error is %lu\n", __func__, min_err);
422
423 return 0;
424 }
425
wm8750_get_filter(u32 parent_rate,u32 divisor1)426 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
427 {
428 /* calculate frequency (MHz) after pre-divisor */
429 u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
430
431 if ((freq < 10) || (freq > 200))
432 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
433 __func__, freq);
434
435 if (freq >= 166)
436 return 7;
437 else if (freq >= 104)
438 return 6;
439 else if (freq >= 65)
440 return 5;
441 else if (freq >= 42)
442 return 4;
443 else if (freq >= 26)
444 return 3;
445 else if (freq >= 16)
446 return 2;
447 else if (freq >= 10)
448 return 1;
449
450 return 0;
451 }
452
wm8750_find_pll_bits(unsigned long rate,unsigned long parent_rate,u32 * filter,u32 * multiplier,u32 * divisor1,u32 * divisor2)453 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
454 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
455 {
456 u32 mul;
457 int div1, div2;
458 unsigned long tclk, rate_err, best_err;
459
460 best_err = (unsigned long)-1;
461
462 /* Find the closest match (lower or equal to requested) */
463 for (div1 = 1; div1 >= 0; div1--)
464 for (div2 = 7; div2 >= 0; div2--)
465 for (mul = 0; mul <= 255; mul++) {
466 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
467 if (tclk > rate)
468 continue;
469 /* error will always be +ve */
470 rate_err = rate - tclk;
471 if (rate_err == 0) {
472 *filter = wm8750_get_filter(parent_rate, div1);
473 *multiplier = mul;
474 *divisor1 = div1;
475 *divisor2 = div2;
476 return 0;
477 }
478
479 if (rate_err < best_err) {
480 best_err = rate_err;
481 *multiplier = mul;
482 *divisor1 = div1;
483 *divisor2 = div2;
484 }
485 }
486
487 if (best_err == (unsigned long)-1) {
488 pr_warn("%s: impossible rate %lu\n", __func__, rate);
489 return -EINVAL;
490 }
491
492 /* if we got here, it wasn't an exact match */
493 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
494 rate - best_err);
495
496 *filter = wm8750_get_filter(parent_rate, *divisor1);
497
498 return 0;
499 }
500
wm8850_find_pll_bits(unsigned long rate,unsigned long parent_rate,u32 * multiplier,u32 * divisor1,u32 * divisor2)501 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
502 u32 *multiplier, u32 *divisor1, u32 *divisor2)
503 {
504 u32 mul;
505 int div1, div2;
506 unsigned long tclk, rate_err, best_err;
507
508 best_err = (unsigned long)-1;
509
510 /* Find the closest match (lower or equal to requested) */
511 for (div1 = 1; div1 >= 0; div1--)
512 for (div2 = 3; div2 >= 0; div2--)
513 for (mul = 0; mul <= 127; mul++) {
514 tclk = parent_rate * ((mul + 1) * 2) /
515 ((div1 + 1) * (1 << div2));
516 if (tclk > rate)
517 continue;
518 /* error will always be +ve */
519 rate_err = rate - tclk;
520 if (rate_err == 0) {
521 *multiplier = mul;
522 *divisor1 = div1;
523 *divisor2 = div2;
524 return 0;
525 }
526
527 if (rate_err < best_err) {
528 best_err = rate_err;
529 *multiplier = mul;
530 *divisor1 = div1;
531 *divisor2 = div2;
532 }
533 }
534
535 if (best_err == (unsigned long)-1) {
536 pr_warn("%s: impossible rate %lu\n", __func__, rate);
537 return -EINVAL;
538 }
539
540 /* if we got here, it wasn't an exact match */
541 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
542 rate - best_err);
543
544 return 0;
545 }
546
vtwm_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)547 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
548 unsigned long parent_rate)
549 {
550 struct clk_pll *pll = to_clk_pll(hw);
551 u32 filter, mul, div1, div2;
552 u32 pll_val;
553 unsigned long flags = 0;
554 int ret;
555
556 /* sanity check */
557
558 switch (pll->type) {
559 case PLL_TYPE_VT8500:
560 ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
561 if (!ret)
562 pll_val = VT8500_BITS_TO_VAL(mul, div1);
563 break;
564 case PLL_TYPE_WM8650:
565 ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
566 if (!ret)
567 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
568 break;
569 case PLL_TYPE_WM8750:
570 ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
571 if (!ret)
572 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
573 break;
574 case PLL_TYPE_WM8850:
575 ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
576 if (!ret)
577 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
578 break;
579 default:
580 pr_err("%s: invalid pll type\n", __func__);
581 ret = -EINVAL;
582 }
583
584 if (ret)
585 return ret;
586
587 spin_lock_irqsave(pll->lock, flags);
588
589 vt8500_pmc_wait_busy();
590 writel(pll_val, pll->reg);
591 vt8500_pmc_wait_busy();
592
593 spin_unlock_irqrestore(pll->lock, flags);
594
595 return 0;
596 }
597
vtwm_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)598 static int vtwm_pll_determine_rate(struct clk_hw *hw,
599 struct clk_rate_request *req)
600 {
601 struct clk_pll *pll = to_clk_pll(hw);
602 u32 filter, mul, div1, div2;
603 long round_rate;
604 int ret;
605
606 switch (pll->type) {
607 case PLL_TYPE_VT8500:
608 ret = vt8500_find_pll_bits(req->rate, req->best_parent_rate,
609 &mul, &div1);
610 if (!ret)
611 round_rate = VT8500_BITS_TO_FREQ(req->best_parent_rate,
612 mul, div1);
613 break;
614 case PLL_TYPE_WM8650:
615 ret = wm8650_find_pll_bits(req->rate, req->best_parent_rate,
616 &mul, &div1, &div2);
617 if (!ret)
618 round_rate = WM8650_BITS_TO_FREQ(req->best_parent_rate,
619 mul, div1, div2);
620 break;
621 case PLL_TYPE_WM8750:
622 ret = wm8750_find_pll_bits(req->rate, req->best_parent_rate,
623 &filter, &mul, &div1, &div2);
624 if (!ret)
625 round_rate = WM8750_BITS_TO_FREQ(req->best_parent_rate,
626 mul, div1, div2);
627 break;
628 case PLL_TYPE_WM8850:
629 ret = wm8850_find_pll_bits(req->rate, req->best_parent_rate,
630 &mul, &div1, &div2);
631 if (!ret)
632 round_rate = WM8850_BITS_TO_FREQ(req->best_parent_rate,
633 mul, div1, div2);
634 break;
635 default:
636 return -EINVAL;
637 }
638
639 if (ret)
640 req->rate = ret;
641 else
642 req->rate = round_rate;
643
644 return 0;
645 }
646
vtwm_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)647 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
648 unsigned long parent_rate)
649 {
650 struct clk_pll *pll = to_clk_pll(hw);
651 u32 pll_val = readl(pll->reg);
652 unsigned long pll_freq;
653
654 switch (pll->type) {
655 case PLL_TYPE_VT8500:
656 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
657 pll_freq /= VT8500_PLL_DIV(pll_val);
658 break;
659 case PLL_TYPE_WM8650:
660 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
661 pll_freq /= WM8650_PLL_DIV(pll_val);
662 break;
663 case PLL_TYPE_WM8750:
664 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
665 pll_freq /= WM8750_PLL_DIV(pll_val);
666 break;
667 case PLL_TYPE_WM8850:
668 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
669 pll_freq /= WM8850_PLL_DIV(pll_val);
670 break;
671 default:
672 pll_freq = 0;
673 }
674
675 return pll_freq;
676 }
677
678 static const struct clk_ops vtwm_pll_ops = {
679 .determine_rate = vtwm_pll_determine_rate,
680 .set_rate = vtwm_pll_set_rate,
681 .recalc_rate = vtwm_pll_recalc_rate,
682 };
683
vtwm_pll_clk_init(struct device_node * node,int pll_type)684 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
685 {
686 u32 reg;
687 struct clk_hw *hw;
688 struct clk_pll *pll_clk;
689 const char *clk_name = node->name;
690 const char *parent_name;
691 struct clk_init_data init;
692 int rc;
693
694 if (!pmc_base)
695 vtwm_set_pmc_base();
696
697 rc = of_property_read_u32(node, "reg", ®);
698 if (WARN_ON(rc))
699 return;
700
701 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
702 if (WARN_ON(!pll_clk))
703 return;
704
705 pll_clk->reg = pmc_base + reg;
706 pll_clk->lock = &_lock;
707 pll_clk->type = pll_type;
708
709 of_property_read_string(node, "clock-output-names", &clk_name);
710
711 init.name = clk_name;
712 init.ops = &vtwm_pll_ops;
713 init.flags = 0;
714 parent_name = of_clk_get_parent_name(node, 0);
715 init.parent_names = &parent_name;
716 init.num_parents = 1;
717
718 pll_clk->hw.init = &init;
719
720 hw = &pll_clk->hw;
721 rc = clk_hw_register(NULL, &pll_clk->hw);
722 if (WARN_ON(rc)) {
723 kfree(pll_clk);
724 return;
725 }
726 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
727 clk_hw_register_clkdev(hw, clk_name, NULL);
728 }
729
730
731 /* Wrappers for initialization functions */
732
vt8500_pll_init(struct device_node * node)733 static void __init vt8500_pll_init(struct device_node *node)
734 {
735 vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
736 }
737 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
738
wm8650_pll_init(struct device_node * node)739 static void __init wm8650_pll_init(struct device_node *node)
740 {
741 vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
742 }
743 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
744
wm8750_pll_init(struct device_node * node)745 static void __init wm8750_pll_init(struct device_node *node)
746 {
747 vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
748 }
749 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
750
wm8850_pll_init(struct device_node * node)751 static void __init wm8850_pll_init(struct device_node *node)
752 {
753 vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
754 }
755 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
756