1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&l2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 }; 58 59 cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a7"; 62 enable-method = "qcom,kpss-acc-v2"; 63 next-level-cache = <&l2>; 64 qcom,acc = <&acc1>; 65 qcom,saw = <&saw1>; 66 reg = <0x1>; 67 clocks = <&gcc GCC_APPS_CLK_SRC>; 68 clock-frequency = <0>; 69 operating-points-v2 = <&cpu0_opp_table>; 70 }; 71 72 cpu@2 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a7"; 75 enable-method = "qcom,kpss-acc-v2"; 76 next-level-cache = <&l2>; 77 qcom,acc = <&acc2>; 78 qcom,saw = <&saw2>; 79 reg = <0x2>; 80 clocks = <&gcc GCC_APPS_CLK_SRC>; 81 clock-frequency = <0>; 82 operating-points-v2 = <&cpu0_opp_table>; 83 }; 84 85 cpu@3 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a7"; 88 enable-method = "qcom,kpss-acc-v2"; 89 next-level-cache = <&l2>; 90 qcom,acc = <&acc3>; 91 qcom,saw = <&saw3>; 92 reg = <0x3>; 93 clocks = <&gcc GCC_APPS_CLK_SRC>; 94 clock-frequency = <0>; 95 operating-points-v2 = <&cpu0_opp_table>; 96 }; 97 98 l2: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 qcom,saw = <&saw_l2>; 103 }; 104 }; 105 106 cpu0_opp_table: opp-table { 107 compatible = "operating-points-v2"; 108 opp-shared; 109 110 opp-48000000 { 111 opp-hz = /bits/ 64 <48000000>; 112 clock-latency-ns = <256000>; 113 }; 114 opp-200000000 { 115 opp-hz = /bits/ 64 <200000000>; 116 clock-latency-ns = <256000>; 117 }; 118 opp-500000000 { 119 opp-hz = /bits/ 64 <500000000>; 120 clock-latency-ns = <256000>; 121 }; 122 opp-716000000 { 123 opp-hz = /bits/ 64 <716000000>; 124 clock-latency-ns = <256000>; 125 }; 126 }; 127 128 memory { 129 device_type = "memory"; 130 reg = <0x0 0x0>; 131 }; 132 133 pmu { 134 compatible = "arm,cortex-a7-pmu"; 135 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 136 IRQ_TYPE_LEVEL_HIGH)>; 137 }; 138 139 clocks { 140 sleep_clk: sleep_clk { 141 compatible = "fixed-clock"; 142 clock-frequency = <32000>; 143 #clock-cells = <0>; 144 }; 145 146 xo: xo { 147 compatible = "fixed-clock"; 148 clock-frequency = <48000000>; 149 #clock-cells = <0>; 150 }; 151 }; 152 153 firmware { 154 scm { 155 compatible = "qcom,scm-ipq4019", "qcom,scm"; 156 }; 157 }; 158 159 timer { 160 compatible = "arm,armv7-timer"; 161 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 162 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 164 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 165 clock-frequency = <48000000>; 166 always-on; 167 }; 168 169 soc { 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges; 173 compatible = "simple-bus"; 174 175 intc: interrupt-controller@b000000 { 176 compatible = "qcom,msm-qgic2"; 177 interrupt-controller; 178 #interrupt-cells = <3>; 179 reg = <0x0b000000 0x1000>, 180 <0x0b002000 0x1000>; 181 }; 182 183 gcc: clock-controller@1800000 { 184 compatible = "qcom,gcc-ipq4019"; 185 #clock-cells = <1>; 186 #reset-cells = <1>; 187 reg = <0x1800000 0x60000>; 188 clocks = <&xo>, <&sleep_clk>; 189 clock-names = "xo", "sleep_clk"; 190 }; 191 192 prng: rng@22000 { 193 compatible = "qcom,prng"; 194 reg = <0x22000 0x140>; 195 clocks = <&gcc GCC_PRNG_AHB_CLK>; 196 clock-names = "core"; 197 status = "disabled"; 198 }; 199 200 tlmm: pinctrl@1000000 { 201 compatible = "qcom,ipq4019-pinctrl"; 202 reg = <0x01000000 0x300000>; 203 gpio-controller; 204 gpio-ranges = <&tlmm 0 0 100>; 205 #gpio-cells = <2>; 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 209 }; 210 211 vqmmc: regulator@1948000 { 212 compatible = "qcom,vqmmc-ipq4019-regulator"; 213 reg = <0x01948000 0x4>; 214 regulator-name = "vqmmc"; 215 regulator-min-microvolt = <1500000>; 216 regulator-max-microvolt = <3000000>; 217 regulator-always-on; 218 status = "disabled"; 219 }; 220 221 sdhci: mmc@7824900 { 222 compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4"; 223 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 224 reg-names = "hc", "core"; 225 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "hc_irq", "pwr_irq"; 227 bus-width = <8>; 228 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 229 <&gcc GCC_SDCC1_APPS_CLK>, 230 <&xo>; 231 clock-names = "iface", 232 "core", 233 "xo"; 234 status = "disabled"; 235 }; 236 237 blsp_dma: dma-controller@7884000 { 238 compatible = "qcom,bam-v1.7.0"; 239 reg = <0x07884000 0x23000>; 240 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 242 clock-names = "bam_clk"; 243 #dma-cells = <1>; 244 qcom,ee = <0>; 245 status = "disabled"; 246 }; 247 248 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 249 compatible = "qcom,spi-qup-v2.2.1"; 250 reg = <0x78b5000 0x600>; 251 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 253 <&gcc GCC_BLSP1_AHB_CLK>; 254 clock-names = "core", "iface"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 258 dma-names = "tx", "rx"; 259 status = "disabled"; 260 }; 261 262 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 263 compatible = "qcom,spi-qup-v2.2.1"; 264 reg = <0x78b6000 0x600>; 265 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 267 <&gcc GCC_BLSP1_AHB_CLK>; 268 clock-names = "core", "iface"; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 272 dma-names = "tx", "rx"; 273 status = "disabled"; 274 }; 275 276 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 277 compatible = "qcom,i2c-qup-v2.2.1"; 278 reg = <0x78b7000 0x600>; 279 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 281 <&gcc GCC_BLSP1_AHB_CLK>; 282 clock-names = "core", "iface"; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 286 dma-names = "tx", "rx"; 287 status = "disabled"; 288 }; 289 290 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 291 compatible = "qcom,i2c-qup-v2.2.1"; 292 reg = <0x78b8000 0x600>; 293 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 295 <&gcc GCC_BLSP1_AHB_CLK>; 296 clock-names = "core", "iface"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 300 dma-names = "tx", "rx"; 301 status = "disabled"; 302 }; 303 304 cryptobam: dma-controller@8e04000 { 305 compatible = "qcom,bam-v1.7.0"; 306 reg = <0x08e04000 0x20000>; 307 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 309 clock-names = "bam_clk"; 310 #dma-cells = <1>; 311 qcom,ee = <1>; 312 qcom,controlled-remotely; 313 status = "disabled"; 314 }; 315 316 crypto: crypto@8e3a000 { 317 compatible = "qcom,crypto-v5.1"; 318 reg = <0x08e3a000 0x6000>; 319 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 320 <&gcc GCC_CRYPTO_AXI_CLK>, 321 <&gcc GCC_CRYPTO_CLK>; 322 clock-names = "iface", "bus", "core"; 323 dmas = <&cryptobam 2>, <&cryptobam 3>; 324 dma-names = "rx", "tx"; 325 status = "disabled"; 326 }; 327 328 acc0: power-manager@b088000 { 329 compatible = "qcom,kpss-acc-v2"; 330 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 331 }; 332 333 acc1: power-manager@b098000 { 334 compatible = "qcom,kpss-acc-v2"; 335 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 336 }; 337 338 acc2: power-manager@b0a8000 { 339 compatible = "qcom,kpss-acc-v2"; 340 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 341 }; 342 343 acc3: power-manager@b0b8000 { 344 compatible = "qcom,kpss-acc-v2"; 345 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 346 }; 347 348 saw0: power-manager@b089000 { 349 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 350 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 351 }; 352 353 saw1: power-manager@b099000 { 354 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 355 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 356 }; 357 358 saw2: power-manager@b0a9000 { 359 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 360 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 361 }; 362 363 saw3: power-manager@b0b9000 { 364 compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; 365 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 366 }; 367 368 saw_l2: power-manager@b012000 { 369 compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; 370 reg = <0xb012000 0x1000>; 371 }; 372 373 blsp1_uart1: serial@78af000 { 374 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 375 reg = <0x78af000 0x200>; 376 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 377 status = "disabled"; 378 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 379 <&gcc GCC_BLSP1_AHB_CLK>; 380 clock-names = "core", "iface"; 381 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 382 dma-names = "tx", "rx"; 383 }; 384 385 blsp1_uart2: serial@78b0000 { 386 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 387 reg = <0x78b0000 0x200>; 388 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 389 status = "disabled"; 390 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 391 <&gcc GCC_BLSP1_AHB_CLK>; 392 clock-names = "core", "iface"; 393 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 394 dma-names = "tx", "rx"; 395 }; 396 397 watchdog: watchdog@b017000 { 398 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; 399 reg = <0xb017000 0x40>; 400 clocks = <&sleep_clk>; 401 timeout-sec = <10>; 402 status = "disabled"; 403 }; 404 405 restart@4ab000 { 406 compatible = "qcom,pshold"; 407 reg = <0x4ab000 0x4>; 408 }; 409 410 pcie0: pcie@40000000 { 411 compatible = "qcom,pcie-ipq4019"; 412 reg = <0x40000000 0xf1d>, 413 <0x40000f20 0xa8>, 414 <0x80000 0x2000>, 415 <0x40100000 0x1000>; 416 reg-names = "dbi", "elbi", "parf", "config"; 417 device_type = "pci"; 418 linux,pci-domain = <0>; 419 bus-range = <0x00 0xff>; 420 num-lanes = <1>; 421 #address-cells = <3>; 422 #size-cells = <2>; 423 424 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 425 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 426 427 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "msi"; 429 #interrupt-cells = <1>; 430 interrupt-map-mask = <0 0 0 0x7>; 431 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 432 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 433 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 434 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 435 clocks = <&gcc GCC_PCIE_AHB_CLK>, 436 <&gcc GCC_PCIE_AXI_M_CLK>, 437 <&gcc GCC_PCIE_AXI_S_CLK>; 438 clock-names = "aux", 439 "master_bus", 440 "slave_bus"; 441 442 resets = <&gcc PCIE_AXI_M_ARES>, 443 <&gcc PCIE_AXI_S_ARES>, 444 <&gcc PCIE_PIPE_ARES>, 445 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 446 <&gcc PCIE_AXI_S_XPU_ARES>, 447 <&gcc PCIE_PARF_XPU_ARES>, 448 <&gcc PCIE_PHY_ARES>, 449 <&gcc PCIE_AXI_M_STICKY_ARES>, 450 <&gcc PCIE_PIPE_STICKY_ARES>, 451 <&gcc PCIE_PWR_ARES>, 452 <&gcc PCIE_AHB_ARES>, 453 <&gcc PCIE_PHY_AHB_ARES>; 454 reset-names = "axi_m", 455 "axi_s", 456 "pipe", 457 "axi_m_vmid", 458 "axi_s_xpu", 459 "parf", 460 "phy", 461 "axi_m_sticky", 462 "pipe_sticky", 463 "pwr", 464 "ahb", 465 "phy_ahb"; 466 467 status = "disabled"; 468 469 pcie@0 { 470 device_type = "pci"; 471 reg = <0x0 0x0 0x0 0x0 0x0>; 472 bus-range = <0x01 0xff>; 473 474 #address-cells = <3>; 475 #size-cells = <2>; 476 ranges; 477 }; 478 }; 479 480 qpic_bam: dma-controller@7984000 { 481 compatible = "qcom,bam-v1.7.0"; 482 reg = <0x7984000 0x1a000>; 483 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&gcc GCC_QPIC_CLK>; 485 clock-names = "bam_clk"; 486 #dma-cells = <1>; 487 qcom,ee = <0>; 488 status = "disabled"; 489 }; 490 491 nand: nand-controller@79b0000 { 492 compatible = "qcom,ipq4019-nand"; 493 reg = <0x79b0000 0x1000>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 clocks = <&gcc GCC_QPIC_CLK>, 497 <&gcc GCC_QPIC_AHB_CLK>; 498 clock-names = "core", "aon"; 499 500 dmas = <&qpic_bam 0>, 501 <&qpic_bam 1>, 502 <&qpic_bam 2>; 503 dma-names = "tx", "rx", "cmd"; 504 status = "disabled"; 505 506 nand@0 { 507 reg = <0>; 508 509 nand-ecc-strength = <4>; 510 nand-ecc-step-size = <512>; 511 nand-bus-width = <8>; 512 }; 513 }; 514 515 wifi0: wifi@a000000 { 516 compatible = "qcom,ipq4019-wifi"; 517 reg = <0xa000000 0x200000>; 518 resets = <&gcc WIFI0_CPU_INIT_RESET>, 519 <&gcc WIFI0_RADIO_SRIF_RESET>, 520 <&gcc WIFI0_RADIO_WARM_RESET>, 521 <&gcc WIFI0_RADIO_COLD_RESET>, 522 <&gcc WIFI0_CORE_WARM_RESET>, 523 <&gcc WIFI0_CORE_COLD_RESET>; 524 reset-names = "wifi_cpu_init", "wifi_radio_srif", 525 "wifi_radio_warm", "wifi_radio_cold", 526 "wifi_core_warm", "wifi_core_cold"; 527 clocks = <&gcc GCC_WCSS2G_CLK>, 528 <&gcc GCC_WCSS2G_REF_CLK>, 529 <&gcc GCC_WCSS2G_RTC_CLK>; 530 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 531 "wifi_wcss_rtc"; 532 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 547 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 548 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "msi0", "msi1", "msi2", "msi3", 550 "msi4", "msi5", "msi6", "msi7", 551 "msi8", "msi9", "msi10", "msi11", 552 "msi12", "msi13", "msi14", "msi15", 553 "legacy"; 554 status = "disabled"; 555 }; 556 557 wifi1: wifi@a800000 { 558 compatible = "qcom,ipq4019-wifi"; 559 reg = <0xa800000 0x200000>; 560 resets = <&gcc WIFI1_CPU_INIT_RESET>, 561 <&gcc WIFI1_RADIO_SRIF_RESET>, 562 <&gcc WIFI1_RADIO_WARM_RESET>, 563 <&gcc WIFI1_RADIO_COLD_RESET>, 564 <&gcc WIFI1_CORE_WARM_RESET>, 565 <&gcc WIFI1_CORE_COLD_RESET>; 566 reset-names = "wifi_cpu_init", "wifi_radio_srif", 567 "wifi_radio_warm", "wifi_radio_cold", 568 "wifi_core_warm", "wifi_core_cold"; 569 clocks = <&gcc GCC_WCSS5G_CLK>, 570 <&gcc GCC_WCSS5G_REF_CLK>, 571 <&gcc GCC_WCSS5G_RTC_CLK>; 572 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 573 "wifi_wcss_rtc"; 574 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 587 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 588 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 589 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 590 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "msi0", "msi1", "msi2", "msi3", 592 "msi4", "msi5", "msi6", "msi7", 593 "msi8", "msi9", "msi10", "msi11", 594 "msi12", "msi13", "msi14", "msi15", 595 "legacy"; 596 status = "disabled"; 597 }; 598 599 mdio: mdio@90000 { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 compatible = "qcom,ipq4019-mdio"; 603 reg = <0x90000 0x64>; 604 status = "disabled"; 605 606 ethernet-phy-package@0 { 607 #address-cells = <1>; 608 #size-cells = <0>; 609 compatible = "qcom,qca8075-package"; 610 reg = <0>; 611 612 qcom,tx-drive-strength-milliwatt = <300>; 613 614 ethphy0: ethernet-phy@0 { 615 reg = <0>; 616 }; 617 618 ethphy1: ethernet-phy@1 { 619 reg = <1>; 620 }; 621 622 ethphy2: ethernet-phy@2 { 623 reg = <2>; 624 }; 625 626 ethphy3: ethernet-phy@3 { 627 reg = <3>; 628 }; 629 630 ethphy4: ethernet-phy@4 { 631 reg = <4>; 632 }; 633 }; 634 }; 635 636 usb3_ss_phy: usb-phy@9a000 { 637 compatible = "qcom,usb-ss-ipq4019-phy"; 638 #phy-cells = <0>; 639 reg = <0x9a000 0x800>; 640 reg-names = "phy_base"; 641 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 642 reset-names = "por_rst"; 643 status = "disabled"; 644 }; 645 646 usb3_hs_phy: usb-phy@a6000 { 647 compatible = "qcom,usb-hs-ipq4019-phy"; 648 #phy-cells = <0>; 649 reg = <0xa6000 0x40>; 650 reg-names = "phy_base"; 651 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 652 reset-names = "por_rst", "srif_rst"; 653 status = "disabled"; 654 }; 655 656 usb3: usb@8af8800 { 657 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 658 reg = <0x8af8800 0x100>; 659 #address-cells = <1>; 660 #size-cells = <1>; 661 clocks = <&gcc GCC_USB3_MASTER_CLK>, 662 <&gcc GCC_USB3_SLEEP_CLK>, 663 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 664 clock-names = "core", "sleep", "mock_utmi"; 665 ranges; 666 status = "disabled"; 667 668 usb3_dwc: usb@8a00000 { 669 compatible = "snps,dwc3"; 670 reg = <0x8a00000 0xf8000>; 671 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 672 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 673 phy-names = "usb2-phy", "usb3-phy"; 674 dr_mode = "host"; 675 }; 676 }; 677 678 usb2_hs_phy: usb-phy@a8000 { 679 compatible = "qcom,usb-hs-ipq4019-phy"; 680 #phy-cells = <0>; 681 reg = <0xa8000 0x40>; 682 reg-names = "phy_base"; 683 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 684 reset-names = "por_rst", "srif_rst"; 685 status = "disabled"; 686 }; 687 688 usb2: usb@60f8800 { 689 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 690 reg = <0x60f8800 0x100>; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 clocks = <&gcc GCC_USB2_MASTER_CLK>, 694 <&gcc GCC_USB2_SLEEP_CLK>, 695 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 696 clock-names = "core", "sleep", "mock_utmi"; 697 ranges; 698 status = "disabled"; 699 700 usb@6000000 { 701 compatible = "snps,dwc3"; 702 reg = <0x6000000 0xf8000>; 703 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 704 phys = <&usb2_hs_phy>; 705 phy-names = "usb2-phy"; 706 dr_mode = "host"; 707 }; 708 }; 709 }; 710}; 711