1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
3
4 #ifndef __MTK_WED_PRIV_H
5 #define __MTK_WED_PRIV_H
6
7 #include <linux/soc/mediatek/mtk_wed.h>
8 #include <linux/debugfs.h>
9 #include <linux/regmap.h>
10 #include <linux/netdevice.h>
11
12 #include "mtk_wed_regs.h"
13
14 struct mtk_eth;
15 struct mtk_wed_wo;
16
17 struct mtk_wed_soc_data {
18 struct {
19 u32 tx_bm_tkid;
20 u32 wpdma_rx_ring0;
21 u32 reset_idx_tx_mask;
22 u32 reset_idx_rx_mask;
23 } regmap;
24 u32 tx_ring_desc_size;
25 u32 wdma_desc_size;
26 };
27
28 struct mtk_wed_amsdu {
29 void *txd;
30 dma_addr_t txd_phy;
31 };
32
33 struct mtk_wed_hw {
34 const struct mtk_wed_soc_data *soc;
35 struct device_node *node;
36 struct mtk_eth *eth;
37 struct regmap *regs;
38 struct regmap *hifsys;
39 struct device *dev;
40 void __iomem *wdma;
41 phys_addr_t wdma_phy;
42 struct regmap *mirror;
43 struct dentry *debugfs_dir;
44 struct mtk_wed_device *wed_dev;
45 struct mtk_wed_wo *wed_wo;
46 struct mtk_wed_amsdu *wed_amsdu;
47 u32 pcie_base;
48 u32 debugfs_reg;
49 u32 num_flows;
50 u8 version;
51 char dirname[5];
52 int irq;
53 int index;
54 };
55
56 struct mtk_wdma_info {
57 u8 wdma_idx;
58 u8 queue;
59 u16 wcid;
60 u8 bss;
61 u8 amsdu;
62 };
63
64 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
mtk_wed_is_v1(struct mtk_wed_hw * hw)65 static inline bool mtk_wed_is_v1(struct mtk_wed_hw *hw)
66 {
67 return hw->version == 1;
68 }
69
mtk_wed_is_v2(struct mtk_wed_hw * hw)70 static inline bool mtk_wed_is_v2(struct mtk_wed_hw *hw)
71 {
72 return hw->version == 2;
73 }
74
mtk_wed_is_v3(struct mtk_wed_hw * hw)75 static inline bool mtk_wed_is_v3(struct mtk_wed_hw *hw)
76 {
77 return hw->version == 3;
78 }
79
mtk_wed_is_v3_or_greater(struct mtk_wed_hw * hw)80 static inline bool mtk_wed_is_v3_or_greater(struct mtk_wed_hw *hw)
81 {
82 return hw->version > 2;
83 }
84
85 static inline void
wed_w32(struct mtk_wed_device * dev,u32 reg,u32 val)86 wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
87 {
88 regmap_write(dev->hw->regs, reg, val);
89 }
90
91 static inline u32
wed_r32(struct mtk_wed_device * dev,u32 reg)92 wed_r32(struct mtk_wed_device *dev, u32 reg)
93 {
94 unsigned int val;
95
96 regmap_read(dev->hw->regs, reg, &val);
97
98 return val;
99 }
100
101 static inline void
wdma_w32(struct mtk_wed_device * dev,u32 reg,u32 val)102 wdma_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
103 {
104 writel(val, dev->hw->wdma + reg);
105 }
106
107 static inline u32
wdma_r32(struct mtk_wed_device * dev,u32 reg)108 wdma_r32(struct mtk_wed_device *dev, u32 reg)
109 {
110 return readl(dev->hw->wdma + reg);
111 }
112
113 static inline u32
wpdma_tx_r32(struct mtk_wed_device * dev,int ring,u32 reg)114 wpdma_tx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
115 {
116 if (!dev->tx_ring[ring].wpdma)
117 return 0;
118
119 return readl(dev->tx_ring[ring].wpdma + reg);
120 }
121
122 static inline void
wpdma_tx_w32(struct mtk_wed_device * dev,int ring,u32 reg,u32 val)123 wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
124 {
125 if (!dev->tx_ring[ring].wpdma)
126 return;
127
128 writel(val, dev->tx_ring[ring].wpdma + reg);
129 }
130
131 static inline u32
wpdma_rx_r32(struct mtk_wed_device * dev,int ring,u32 reg)132 wpdma_rx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
133 {
134 if (!dev->rx_ring[ring].wpdma)
135 return 0;
136
137 return readl(dev->rx_ring[ring].wpdma + reg);
138 }
139
140 static inline void
wpdma_rx_w32(struct mtk_wed_device * dev,int ring,u32 reg,u32 val)141 wpdma_rx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
142 {
143 if (!dev->rx_ring[ring].wpdma)
144 return;
145
146 writel(val, dev->rx_ring[ring].wpdma + reg);
147 }
148
149 static inline u32
wpdma_txfree_r32(struct mtk_wed_device * dev,u32 reg)150 wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)
151 {
152 if (!dev->txfree_ring.wpdma)
153 return 0;
154
155 return readl(dev->txfree_ring.wpdma + reg);
156 }
157
158 static inline void
wpdma_txfree_w32(struct mtk_wed_device * dev,u32 reg,u32 val)159 wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
160 {
161 if (!dev->txfree_ring.wpdma)
162 return;
163
164 writel(val, dev->txfree_ring.wpdma + reg);
165 }
166
mtk_wed_get_pcie_base(struct mtk_wed_device * dev)167 static inline u32 mtk_wed_get_pcie_base(struct mtk_wed_device *dev)
168 {
169 if (!mtk_wed_is_v3_or_greater(dev->hw))
170 return MTK_WED_PCIE_BASE;
171
172 switch (dev->hw->index) {
173 case 1:
174 return MTK_WED_PCIE_BASE1;
175 case 2:
176 return MTK_WED_PCIE_BASE2;
177 default:
178 return MTK_WED_PCIE_BASE0;
179 }
180 }
181
182 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
183 void __iomem *wdma, phys_addr_t wdma_phy,
184 int index);
185 void mtk_wed_exit(void);
186 int mtk_wed_flow_add(int index);
187 void mtk_wed_flow_remove(int index);
188 void mtk_wed_fe_reset(void);
189 void mtk_wed_fe_reset_complete(void);
190 #else
191 static inline void
mtk_wed_add_hw(struct device_node * np,struct mtk_eth * eth,void __iomem * wdma,phys_addr_t wdma_phy,int index)192 mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
193 void __iomem *wdma, phys_addr_t wdma_phy,
194 int index)
195 {
196 }
197 static inline void
mtk_wed_exit(void)198 mtk_wed_exit(void)
199 {
200 }
mtk_wed_flow_add(int index)201 static inline int mtk_wed_flow_add(int index)
202 {
203 return -EINVAL;
204 }
mtk_wed_flow_remove(int index)205 static inline void mtk_wed_flow_remove(int index)
206 {
207 }
208
mtk_wed_fe_reset(void)209 static inline void mtk_wed_fe_reset(void)
210 {
211 }
212
mtk_wed_fe_reset_complete(void)213 static inline void mtk_wed_fe_reset_complete(void)
214 {
215 }
216 #endif
217
218 #ifdef CONFIG_DEBUG_FS
219 void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw);
220 #else
mtk_wed_hw_add_debugfs(struct mtk_wed_hw * hw)221 static inline void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
222 {
223 }
224 #endif
225
226 #endif
227