1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/types.h>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #if defined(__FreeBSD__)
11 #include <linux/delay.h>
12 #endif
13 #include "core.h"
14 #include "hw.h"
15 #include "hif.h"
16 #include "wmi-ops.h"
17 #include "bmi.h"
18 #include "rx_desc.h"
19
20 const struct ath10k_hw_regs qca988x_regs = {
21 .rtc_soc_base_address = 0x00004000,
22 .rtc_wmac_base_address = 0x00005000,
23 .soc_core_base_address = 0x00009000,
24 .wlan_mac_base_address = 0x00020000,
25 .ce_wrapper_base_address = 0x00057000,
26 .ce0_base_address = 0x00057400,
27 .ce1_base_address = 0x00057800,
28 .ce2_base_address = 0x00057c00,
29 .ce3_base_address = 0x00058000,
30 .ce4_base_address = 0x00058400,
31 .ce5_base_address = 0x00058800,
32 .ce6_base_address = 0x00058c00,
33 .ce7_base_address = 0x00059000,
34 .soc_reset_control_si0_rst_mask = 0x00000001,
35 .soc_reset_control_ce_rst_mask = 0x00040000,
36 .soc_chip_id_address = 0x000000ec,
37 .scratch_3_address = 0x00000030,
38 .fw_indicator_address = 0x00009030,
39 .pcie_local_base_address = 0x00080000,
40 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
41 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
42 .pcie_intr_fw_mask = 0x00000400,
43 .pcie_intr_ce_mask_all = 0x0007f800,
44 .pcie_intr_clr_address = 0x00000014,
45 };
46
47 const struct ath10k_hw_regs qca6174_regs = {
48 .rtc_soc_base_address = 0x00000800,
49 .rtc_wmac_base_address = 0x00001000,
50 .soc_core_base_address = 0x0003a000,
51 .wlan_mac_base_address = 0x00010000,
52 .ce_wrapper_base_address = 0x00034000,
53 .ce0_base_address = 0x00034400,
54 .ce1_base_address = 0x00034800,
55 .ce2_base_address = 0x00034c00,
56 .ce3_base_address = 0x00035000,
57 .ce4_base_address = 0x00035400,
58 .ce5_base_address = 0x00035800,
59 .ce6_base_address = 0x00035c00,
60 .ce7_base_address = 0x00036000,
61 .soc_reset_control_si0_rst_mask = 0x00000000,
62 .soc_reset_control_ce_rst_mask = 0x00000001,
63 .soc_chip_id_address = 0x000000f0,
64 .scratch_3_address = 0x00000028,
65 .fw_indicator_address = 0x0003a028,
66 .pcie_local_base_address = 0x00080000,
67 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
68 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
69 .pcie_intr_fw_mask = 0x00000400,
70 .pcie_intr_ce_mask_all = 0x0007f800,
71 .pcie_intr_clr_address = 0x00000014,
72 .cpu_pll_init_address = 0x00404020,
73 .cpu_speed_address = 0x00404024,
74 .core_clk_div_address = 0x00404028,
75 };
76
77 const struct ath10k_hw_regs qca99x0_regs = {
78 .rtc_soc_base_address = 0x00080000,
79 .rtc_wmac_base_address = 0x00000000,
80 .soc_core_base_address = 0x00082000,
81 .wlan_mac_base_address = 0x00030000,
82 .ce_wrapper_base_address = 0x0004d000,
83 .ce0_base_address = 0x0004a000,
84 .ce1_base_address = 0x0004a400,
85 .ce2_base_address = 0x0004a800,
86 .ce3_base_address = 0x0004ac00,
87 .ce4_base_address = 0x0004b000,
88 .ce5_base_address = 0x0004b400,
89 .ce6_base_address = 0x0004b800,
90 .ce7_base_address = 0x0004bc00,
91 /* Note: qca99x0 supports up to 12 Copy Engines. Other than address of
92 * CE0 and CE1 no other copy engine is directly referred in the code.
93 * It is not really necessary to assign address for newly supported
94 * CEs in this address table.
95 * Copy Engine Address
96 * CE8 0x0004c000
97 * CE9 0x0004c400
98 * CE10 0x0004c800
99 * CE11 0x0004cc00
100 */
101 .soc_reset_control_si0_rst_mask = 0x00000001,
102 .soc_reset_control_ce_rst_mask = 0x00000100,
103 .soc_chip_id_address = 0x000000ec,
104 .scratch_3_address = 0x00040050,
105 .fw_indicator_address = 0x00040050,
106 .pcie_local_base_address = 0x00000000,
107 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
108 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
109 .pcie_intr_fw_mask = 0x00100000,
110 .pcie_intr_ce_mask_all = 0x000fff00,
111 .pcie_intr_clr_address = 0x00000010,
112 };
113
114 const struct ath10k_hw_regs qca4019_regs = {
115 .rtc_soc_base_address = 0x00080000,
116 .soc_core_base_address = 0x00082000,
117 .wlan_mac_base_address = 0x00030000,
118 .ce_wrapper_base_address = 0x0004d000,
119 .ce0_base_address = 0x0004a000,
120 .ce1_base_address = 0x0004a400,
121 .ce2_base_address = 0x0004a800,
122 .ce3_base_address = 0x0004ac00,
123 .ce4_base_address = 0x0004b000,
124 .ce5_base_address = 0x0004b400,
125 .ce6_base_address = 0x0004b800,
126 .ce7_base_address = 0x0004bc00,
127 /* qca4019 supports up to 12 copy engines. Since base address
128 * of ce8 to ce11 are not directly referred in the code,
129 * no need have them in separate members in this table.
130 * Copy Engine Address
131 * CE8 0x0004c000
132 * CE9 0x0004c400
133 * CE10 0x0004c800
134 * CE11 0x0004cc00
135 */
136 .soc_reset_control_si0_rst_mask = 0x00000001,
137 .soc_reset_control_ce_rst_mask = 0x00000100,
138 .soc_chip_id_address = 0x000000ec,
139 .fw_indicator_address = 0x0004f00c,
140 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
141 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
142 .pcie_intr_fw_mask = 0x00100000,
143 .pcie_intr_ce_mask_all = 0x000fff00,
144 .pcie_intr_clr_address = 0x00000010,
145 };
146
147 const struct ath10k_hw_values qca988x_values = {
148 .rtc_state_val_on = 3,
149 .ce_count = 8,
150 .msi_assign_ce_max = 7,
151 .num_target_ce_config_wlan = 7,
152 .ce_desc_meta_data_mask = 0xFFFC,
153 .ce_desc_meta_data_lsb = 2,
154 };
155
156 const struct ath10k_hw_values qca6174_values = {
157 .rtc_state_val_on = 3,
158 .ce_count = 8,
159 .msi_assign_ce_max = 7,
160 .num_target_ce_config_wlan = 7,
161 .ce_desc_meta_data_mask = 0xFFFC,
162 .ce_desc_meta_data_lsb = 2,
163 .rfkill_pin = 16,
164 .rfkill_cfg = 0,
165 .rfkill_on_level = 1,
166 };
167
168 const struct ath10k_hw_values qca99x0_values = {
169 .rtc_state_val_on = 7,
170 .ce_count = 12,
171 .msi_assign_ce_max = 12,
172 .num_target_ce_config_wlan = 10,
173 .ce_desc_meta_data_mask = 0xFFF0,
174 .ce_desc_meta_data_lsb = 4,
175 };
176
177 const struct ath10k_hw_values qca9888_values = {
178 .rtc_state_val_on = 3,
179 .ce_count = 12,
180 .msi_assign_ce_max = 12,
181 .num_target_ce_config_wlan = 10,
182 .ce_desc_meta_data_mask = 0xFFF0,
183 .ce_desc_meta_data_lsb = 4,
184 };
185
186 const struct ath10k_hw_values qca4019_values = {
187 .ce_count = 12,
188 .num_target_ce_config_wlan = 10,
189 .ce_desc_meta_data_mask = 0xFFF0,
190 .ce_desc_meta_data_lsb = 4,
191 };
192
193 const struct ath10k_hw_regs wcn3990_regs = {
194 .rtc_soc_base_address = 0x00000000,
195 .rtc_wmac_base_address = 0x00000000,
196 .soc_core_base_address = 0x00000000,
197 .ce_wrapper_base_address = 0x0024C000,
198 .ce0_base_address = 0x00240000,
199 .ce1_base_address = 0x00241000,
200 .ce2_base_address = 0x00242000,
201 .ce3_base_address = 0x00243000,
202 .ce4_base_address = 0x00244000,
203 .ce5_base_address = 0x00245000,
204 .ce6_base_address = 0x00246000,
205 .ce7_base_address = 0x00247000,
206 .ce8_base_address = 0x00248000,
207 .ce9_base_address = 0x00249000,
208 .ce10_base_address = 0x0024A000,
209 .ce11_base_address = 0x0024B000,
210 .soc_chip_id_address = 0x000000f0,
211 .soc_reset_control_si0_rst_mask = 0x00000001,
212 .soc_reset_control_ce_rst_mask = 0x00000100,
213 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
214 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
215 .pcie_intr_fw_mask = 0x00100000,
216 };
217
218 static const struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
219 .msb = 0x00000010,
220 .lsb = 0x00000010,
221 .mask = GENMASK(17, 17),
222 };
223
224 static const struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
225 .msb = 0x00000012,
226 .lsb = 0x00000012,
227 .mask = GENMASK(18, 18),
228 };
229
230 static const struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
231 .msb = 0x00000000,
232 .lsb = 0x00000000,
233 .mask = GENMASK(15, 0),
234 };
235
236 static const struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
237 .addr = 0x00000018,
238 .src_ring = &wcn3990_src_ring,
239 .dst_ring = &wcn3990_dst_ring,
240 .dmax = &wcn3990_dmax,
241 };
242
243 static const struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
244 .mask = GENMASK(0, 0),
245 };
246
247 static const struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
248 .copy_complete = &wcn3990_host_ie_cc,
249 };
250
251 static const struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
252 .dstr_lmask = 0x00000010,
253 .dstr_hmask = 0x00000008,
254 .srcr_lmask = 0x00000004,
255 .srcr_hmask = 0x00000002,
256 .cc_mask = 0x00000001,
257 .wm_mask = 0x0000001E,
258 .addr = 0x00000030,
259 };
260
261 static const struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
262 .axi_err = 0x00000100,
263 .dstr_add_err = 0x00000200,
264 .srcr_len_err = 0x00000100,
265 .dstr_mlen_vio = 0x00000080,
266 .dstr_overflow = 0x00000040,
267 .srcr_overflow = 0x00000020,
268 .err_mask = 0x000003E0,
269 .addr = 0x00000038,
270 };
271
272 static const struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
273 .msb = 0x00000000,
274 .lsb = 0x00000010,
275 .mask = GENMASK(31, 16),
276 };
277
278 static const struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
279 .msb = 0x0000000f,
280 .lsb = 0x00000000,
281 .mask = GENMASK(15, 0),
282 };
283
284 static const struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
285 .addr = 0x0000004c,
286 .low_rst = 0x00000000,
287 .high_rst = 0x00000000,
288 .wm_low = &wcn3990_src_wm_low,
289 .wm_high = &wcn3990_src_wm_high,
290 };
291
292 static const struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
293 .lsb = 0x00000010,
294 .mask = GENMASK(31, 16),
295 };
296
297 static const struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
298 .msb = 0x0000000f,
299 .lsb = 0x00000000,
300 .mask = GENMASK(15, 0),
301 };
302
303 static const struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
304 .addr = 0x00000050,
305 .low_rst = 0x00000000,
306 .high_rst = 0x00000000,
307 .wm_low = &wcn3990_dst_wm_low,
308 .wm_high = &wcn3990_dst_wm_high,
309 };
310
311 static const struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = {
312 .shift = 19,
313 .mask = 0x00080000,
314 .enable = 0x00000000,
315 };
316
317 const struct ath10k_hw_ce_regs wcn3990_ce_regs = {
318 .sr_base_addr_lo = 0x00000000,
319 .sr_base_addr_hi = 0x00000004,
320 .sr_size_addr = 0x00000008,
321 .dr_base_addr_lo = 0x0000000c,
322 .dr_base_addr_hi = 0x00000010,
323 .dr_size_addr = 0x00000014,
324 .misc_ie_addr = 0x00000034,
325 .sr_wr_index_addr = 0x0000003c,
326 .dst_wr_index_addr = 0x00000040,
327 .current_srri_addr = 0x00000044,
328 .current_drri_addr = 0x00000048,
329 .ce_rri_low = 0x0024C004,
330 .ce_rri_high = 0x0024C008,
331 .host_ie_addr = 0x0000002c,
332 .ctrl1_regs = &wcn3990_ctrl1,
333 .host_ie = &wcn3990_host_ie,
334 .wm_regs = &wcn3990_wm_reg,
335 .misc_regs = &wcn3990_misc_reg,
336 .wm_srcr = &wcn3990_wm_src_ring,
337 .wm_dstr = &wcn3990_wm_dst_ring,
338 .upd = &wcn3990_ctrl1_upd,
339 };
340
341 const struct ath10k_hw_values wcn3990_values = {
342 .rtc_state_val_on = 5,
343 .ce_count = 12,
344 .msi_assign_ce_max = 12,
345 .num_target_ce_config_wlan = 12,
346 .ce_desc_meta_data_mask = 0xFFF0,
347 .ce_desc_meta_data_lsb = 4,
348 };
349
350 static const struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
351 .msb = 0x00000010,
352 .lsb = 0x00000010,
353 .mask = GENMASK(16, 16),
354 };
355
356 static const struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
357 .msb = 0x00000011,
358 .lsb = 0x00000011,
359 .mask = GENMASK(17, 17),
360 };
361
362 static const struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
363 .msb = 0x0000000f,
364 .lsb = 0x00000000,
365 .mask = GENMASK(15, 0),
366 };
367
368 static const struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
369 .addr = 0x00000010,
370 .hw_mask = 0x0007ffff,
371 .sw_mask = 0x0007ffff,
372 .hw_wr_mask = 0x00000000,
373 .sw_wr_mask = 0x0007ffff,
374 .reset_mask = 0xffffffff,
375 .reset = 0x00000080,
376 .src_ring = &qcax_src_ring,
377 .dst_ring = &qcax_dst_ring,
378 .dmax = &qcax_dmax,
379 };
380
381 static const struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
382 .msb = 0x00000003,
383 .lsb = 0x00000003,
384 .mask = GENMASK(3, 3),
385 };
386
387 static const struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
388 .msb = 0x00000000,
389 .mask = GENMASK(0, 0),
390 .status_reset = 0x00000000,
391 .status = &qcax_cmd_halt_status,
392 };
393
394 static const struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
395 .msb = 0x00000000,
396 .lsb = 0x00000000,
397 .mask = GENMASK(0, 0),
398 };
399
400 static const struct ath10k_hw_ce_host_ie qcax_host_ie = {
401 .copy_complete_reset = 0x00000000,
402 .copy_complete = &qcax_host_ie_cc,
403 };
404
405 static const struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
406 .dstr_lmask = 0x00000010,
407 .dstr_hmask = 0x00000008,
408 .srcr_lmask = 0x00000004,
409 .srcr_hmask = 0x00000002,
410 .cc_mask = 0x00000001,
411 .wm_mask = 0x0000001E,
412 .addr = 0x00000030,
413 };
414
415 static const struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
416 .axi_err = 0x00000400,
417 .dstr_add_err = 0x00000200,
418 .srcr_len_err = 0x00000100,
419 .dstr_mlen_vio = 0x00000080,
420 .dstr_overflow = 0x00000040,
421 .srcr_overflow = 0x00000020,
422 .err_mask = 0x000007E0,
423 .addr = 0x00000038,
424 };
425
426 static const struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
427 .msb = 0x0000001f,
428 .lsb = 0x00000010,
429 .mask = GENMASK(31, 16),
430 };
431
432 static const struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
433 .msb = 0x0000000f,
434 .lsb = 0x00000000,
435 .mask = GENMASK(15, 0),
436 };
437
438 static const struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
439 .addr = 0x0000004c,
440 .low_rst = 0x00000000,
441 .high_rst = 0x00000000,
442 .wm_low = &qcax_src_wm_low,
443 .wm_high = &qcax_src_wm_high,
444 };
445
446 static const struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
447 .lsb = 0x00000010,
448 .mask = GENMASK(31, 16),
449 };
450
451 static const struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
452 .msb = 0x0000000f,
453 .lsb = 0x00000000,
454 .mask = GENMASK(15, 0),
455 };
456
457 static const struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
458 .addr = 0x00000050,
459 .low_rst = 0x00000000,
460 .high_rst = 0x00000000,
461 .wm_low = &qcax_dst_wm_low,
462 .wm_high = &qcax_dst_wm_high,
463 };
464
465 const struct ath10k_hw_ce_regs qcax_ce_regs = {
466 .sr_base_addr_lo = 0x00000000,
467 .sr_size_addr = 0x00000004,
468 .dr_base_addr_lo = 0x00000008,
469 .dr_size_addr = 0x0000000c,
470 .ce_cmd_addr = 0x00000018,
471 .misc_ie_addr = 0x00000034,
472 .sr_wr_index_addr = 0x0000003c,
473 .dst_wr_index_addr = 0x00000040,
474 .current_srri_addr = 0x00000044,
475 .current_drri_addr = 0x00000048,
476 .host_ie_addr = 0x0000002c,
477 .ctrl1_regs = &qcax_ctrl1,
478 .cmd_halt = &qcax_cmd_halt,
479 .host_ie = &qcax_host_ie,
480 .wm_regs = &qcax_wm_reg,
481 .misc_regs = &qcax_misc_reg,
482 .wm_srcr = &qcax_wm_src_ring,
483 .wm_dstr = &qcax_wm_dst_ring,
484 };
485
486 const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = {
487 {
488 .refclk = 48000000,
489 .div = 0xe,
490 .rnfrac = 0x2aaa8,
491 .settle_time = 2400,
492 .refdiv = 0,
493 .outdiv = 1,
494 },
495 {
496 .refclk = 19200000,
497 .div = 0x24,
498 .rnfrac = 0x2aaa8,
499 .settle_time = 960,
500 .refdiv = 0,
501 .outdiv = 1,
502 },
503 {
504 .refclk = 24000000,
505 .div = 0x1d,
506 .rnfrac = 0x15551,
507 .settle_time = 1200,
508 .refdiv = 0,
509 .outdiv = 1,
510 },
511 {
512 .refclk = 26000000,
513 .div = 0x1b,
514 .rnfrac = 0x4ec4,
515 .settle_time = 1300,
516 .refdiv = 0,
517 .outdiv = 1,
518 },
519 {
520 .refclk = 37400000,
521 .div = 0x12,
522 .rnfrac = 0x34b49,
523 .settle_time = 1870,
524 .refdiv = 0,
525 .outdiv = 1,
526 },
527 {
528 .refclk = 38400000,
529 .div = 0x12,
530 .rnfrac = 0x15551,
531 .settle_time = 1920,
532 .refdiv = 0,
533 .outdiv = 1,
534 },
535 {
536 .refclk = 40000000,
537 .div = 0x12,
538 .rnfrac = 0x26665,
539 .settle_time = 2000,
540 .refdiv = 0,
541 .outdiv = 1,
542 },
543 {
544 .refclk = 52000000,
545 .div = 0x1b,
546 .rnfrac = 0x4ec4,
547 .settle_time = 2600,
548 .refdiv = 0,
549 .outdiv = 1,
550 },
551 };
552
ath10k_hw_fill_survey_time(struct ath10k * ar,struct survey_info * survey,u32 cc,u32 rcc,u32 cc_prev,u32 rcc_prev)553 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
554 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
555 {
556 u32 cc_fix = 0;
557 u32 rcc_fix = 0;
558 enum ath10k_hw_cc_wraparound_type wraparound_type;
559
560 survey->filled |= SURVEY_INFO_TIME |
561 SURVEY_INFO_TIME_BUSY;
562
563 wraparound_type = ar->hw_params.cc_wraparound_type;
564
565 if (cc < cc_prev || rcc < rcc_prev) {
566 switch (wraparound_type) {
567 case ATH10K_HW_CC_WRAP_SHIFTED_ALL:
568 if (cc < cc_prev) {
569 cc_fix = 0x7fffffff;
570 survey->filled &= ~SURVEY_INFO_TIME_BUSY;
571 }
572 break;
573 case ATH10K_HW_CC_WRAP_SHIFTED_EACH:
574 if (cc < cc_prev)
575 cc_fix = 0x7fffffff;
576
577 if (rcc < rcc_prev)
578 rcc_fix = 0x7fffffff;
579 break;
580 case ATH10K_HW_CC_WRAP_DISABLED:
581 break;
582 }
583 }
584
585 cc -= cc_prev - cc_fix;
586 rcc -= rcc_prev - rcc_fix;
587
588 survey->time = CCNT_TO_MSEC(ar, cc);
589 survey->time_busy = CCNT_TO_MSEC(ar, rcc);
590 }
591
592 /* The firmware does not support setting the coverage class. Instead this
593 * function monitors and modifies the corresponding MAC registers.
594 */
ath10k_hw_qca988x_set_coverage_class(struct ath10k * ar,int radio_idx,s16 value)595 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
596 int radio_idx,
597 s16 value)
598 {
599 u32 slottime_reg;
600 u32 slottime;
601 u32 timeout_reg;
602 u32 ack_timeout;
603 u32 cts_timeout;
604 u32 phyclk_reg;
605 u32 phyclk;
606 u64 fw_dbglog_mask;
607 u32 fw_dbglog_level;
608
609 mutex_lock(&ar->conf_mutex);
610
611 /* Only modify registers if the core is started. */
612 if ((ar->state != ATH10K_STATE_ON) &&
613 (ar->state != ATH10K_STATE_RESTARTED)) {
614 spin_lock_bh(&ar->data_lock);
615 /* Store config value for when radio boots up */
616 ar->fw_coverage.coverage_class = value;
617 spin_unlock_bh(&ar->data_lock);
618 goto unlock;
619 }
620
621 /* Retrieve the current values of the two registers that need to be
622 * adjusted.
623 */
624 slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
625 WAVE1_PCU_GBL_IFS_SLOT);
626 timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
627 WAVE1_PCU_ACK_CTS_TIMEOUT);
628 phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
629 WAVE1_PHYCLK);
630 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;
631
632 if (value < 0)
633 value = ar->fw_coverage.coverage_class;
634
635 /* Break out if the coverage class and registers have the expected
636 * value.
637 */
638 if (value == ar->fw_coverage.coverage_class &&
639 slottime_reg == ar->fw_coverage.reg_slottime_conf &&
640 timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
641 phyclk_reg == ar->fw_coverage.reg_phyclk)
642 goto unlock;
643
644 /* Store new initial register values from the firmware. */
645 if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
646 ar->fw_coverage.reg_slottime_orig = slottime_reg;
647 if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
648 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
649 ar->fw_coverage.reg_phyclk = phyclk_reg;
650
651 /* Calculate new value based on the (original) firmware calculation. */
652 slottime_reg = ar->fw_coverage.reg_slottime_orig;
653 timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
654
655 /* Do some sanity checks on the slottime register. */
656 if (slottime_reg % phyclk) {
657 ath10k_warn(ar,
658 "failed to set coverage class: expected integer microsecond value in register\n");
659
660 goto store_regs;
661 }
662
663 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
664 slottime = slottime / phyclk;
665 if (slottime != 9 && slottime != 20) {
666 ath10k_warn(ar,
667 "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
668 slottime);
669
670 goto store_regs;
671 }
672
673 /* Recalculate the register values by adding the additional propagation
674 * delay (3us per coverage class).
675 */
676
677 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
678 slottime += value * 3 * phyclk;
679 slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
680 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
681 slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;
682
683 /* Update ack timeout (lower halfword). */
684 ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
685 ack_timeout += 3 * value * phyclk;
686 ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
687 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
688
689 /* Update cts timeout (upper halfword). */
690 cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
691 cts_timeout += 3 * value * phyclk;
692 cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
693 cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
694
695 timeout_reg = ack_timeout | cts_timeout;
696
697 ath10k_hif_write32(ar,
698 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
699 slottime_reg);
700 ath10k_hif_write32(ar,
701 WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
702 timeout_reg);
703
704 /* Ensure we have a debug level of WARN set for the case that the
705 * coverage class is larger than 0. This is important as we need to
706 * set the registers again if the firmware does an internal reset and
707 * this way we will be notified of the event.
708 */
709 fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
710 fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
711
712 if (value > 0) {
713 if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
714 fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
715 fw_dbglog_mask = ~0;
716 }
717
718 ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
719
720 store_regs:
721 /* After an error we will not retry setting the coverage class. */
722 spin_lock_bh(&ar->data_lock);
723 ar->fw_coverage.coverage_class = value;
724 spin_unlock_bh(&ar->data_lock);
725
726 ar->fw_coverage.reg_slottime_conf = slottime_reg;
727 ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
728
729 unlock:
730 mutex_unlock(&ar->conf_mutex);
731 }
732
733 /**
734 * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
735 * @ar: the ath10k blob
736 *
737 * This function is very hardware specific, the clock initialization
738 * steps is very sensitive and could lead to unknown crash, so they
739 * should be done in sequence.
740 *
741 * *** Be aware if you planned to refactor them. ***
742 *
743 * Return: 0 if successfully enable the pll, otherwise EINVAL
744 */
ath10k_hw_qca6174_enable_pll_clock(struct ath10k * ar)745 static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar)
746 {
747 int ret, wait_limit;
748 u32 clk_div_addr, pll_init_addr, speed_addr;
749 u32 addr, reg_val, mem_val;
750 struct ath10k_hw_params *hw;
751 const struct ath10k_hw_clk_params *hw_clk;
752
753 hw = &ar->hw_params;
754
755 if (ar->regs->core_clk_div_address == 0 ||
756 ar->regs->cpu_pll_init_address == 0 ||
757 ar->regs->cpu_speed_address == 0)
758 return -EINVAL;
759
760 clk_div_addr = ar->regs->core_clk_div_address;
761 pll_init_addr = ar->regs->cpu_pll_init_address;
762 speed_addr = ar->regs->cpu_speed_address;
763
764 /* Read efuse register to find out the right hw clock configuration */
765 addr = (RTC_SOC_BASE_ADDRESS | EFUSE_OFFSET);
766 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
767 if (ret)
768 return -EINVAL;
769
770 /* sanitize if the hw refclk index is out of the boundary */
771 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)
772 return -EINVAL;
773
774 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];
775
776 /* Set the rnfrac and outdiv params to bb_pll register */
777 addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET);
778 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
779 if (ret)
780 return -EINVAL;
781
782 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);
783 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |
784 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV));
785 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
786 if (ret)
787 return -EINVAL;
788
789 /* Set the correct settle time value to pll_settle register */
790 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_SETTLE_OFFSET);
791 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
792 if (ret)
793 return -EINVAL;
794
795 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;
796 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);
797 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
798 if (ret)
799 return -EINVAL;
800
801 /* Set the clock_ctrl div to core_clk_ctrl register */
802 addr = (RTC_SOC_BASE_ADDRESS | SOC_CORE_CLK_CTRL_OFFSET);
803 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
804 if (ret)
805 return -EINVAL;
806
807 reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;
808 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);
809 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
810 if (ret)
811 return -EINVAL;
812
813 /* Set the clock_div register */
814 mem_val = 1;
815 #if defined(__linux__)
816 ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val,
817 #elif defined(__FreeBSD__)
818 ret = ath10k_bmi_write_memory(ar, clk_div_addr, (u8 *)&mem_val,
819 #endif
820 sizeof(mem_val));
821 if (ret)
822 return -EINVAL;
823
824 /* Configure the pll_control register */
825 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
826 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
827 if (ret)
828 return -EINVAL;
829
830 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |
831 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) |
832 SM(1, WLAN_PLL_CONTROL_NOPWD));
833 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
834 if (ret)
835 return -EINVAL;
836
837 /* busy wait (max 1s) the rtc_sync status register indicate ready */
838 wait_limit = 100000;
839 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);
840 do {
841 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
842 if (ret)
843 return -EINVAL;
844
845 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
846 break;
847
848 wait_limit--;
849 udelay(10);
850
851 } while (wait_limit > 0);
852
853 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
854 return -EINVAL;
855
856 /* Unset the pll_bypass in pll_control register */
857 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
858 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
859 if (ret)
860 return -EINVAL;
861
862 reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;
863 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);
864 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
865 if (ret)
866 return -EINVAL;
867
868 /* busy wait (max 1s) the rtc_sync status register indicate ready */
869 wait_limit = 100000;
870 addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);
871 do {
872 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
873 if (ret)
874 return -EINVAL;
875
876 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
877 break;
878
879 wait_limit--;
880 udelay(10);
881
882 } while (wait_limit > 0);
883
884 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
885 return -EINVAL;
886
887 /* Enable the hardware cpu clock register */
888 addr = (RTC_SOC_BASE_ADDRESS | SOC_CPU_CLOCK_OFFSET);
889 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
890 if (ret)
891 return -EINVAL;
892
893 reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;
894 reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);
895 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
896 if (ret)
897 return -EINVAL;
898
899 /* unset the nopwd from pll_control register */
900 addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
901 ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val);
902 if (ret)
903 return -EINVAL;
904
905 reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;
906 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
907 if (ret)
908 return -EINVAL;
909
910 /* enable the pll_init register */
911 mem_val = 1;
912 #if defined(__linux__)
913 ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val,
914 #elif defined(__FreeBSD__)
915 ret = ath10k_bmi_write_memory(ar, pll_init_addr, (u8 *)&mem_val,
916 #endif
917 sizeof(mem_val));
918 if (ret)
919 return -EINVAL;
920
921 /* set the target clock frequency to speed register */
922 #if defined(__linux__)
923 ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,
924 #elif defined(__FreeBSD__)
925 ret = ath10k_bmi_write_memory(ar, speed_addr, (u8 *)&hw->target_cpu_freq,
926 #endif
927 sizeof(hw->target_cpu_freq));
928 if (ret)
929 return -EINVAL;
930
931 return 0;
932 }
933
934 /* Program CPU_ADDR_MSB to allow different memory
935 * region access.
936 */
ath10k_hw_map_target_mem(struct ath10k * ar,u32 msb)937 static void ath10k_hw_map_target_mem(struct ath10k *ar, u32 msb)
938 {
939 u32 address = SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS;
940
941 ath10k_hif_write32(ar, address, msb);
942 }
943
944 /* 1. Write to memory region of target, such as IRAM and DRAM.
945 * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)
946 * can be written directly. See ath10k_pci_targ_cpu_to_ce_addr() too.
947 * 3. In order to access the region other than the above,
948 * we need to set the value of register CPU_ADDR_MSB.
949 * 4. Target memory access space is limited to 1M size. If the size is larger
950 * than 1M, need to split it and program CPU_ADDR_MSB accordingly.
951 */
ath10k_hw_diag_segment_msb_download(struct ath10k * ar,const void * buffer,u32 address,u32 length)952 static int ath10k_hw_diag_segment_msb_download(struct ath10k *ar,
953 #if defined(__linux__)
954 const void *buffer,
955 #elif defined(__FreeBSD__)
956 const u8 *buffer,
957 #endif
958 u32 address,
959 u32 length)
960 {
961 u32 addr = address & REGION_ACCESS_SIZE_MASK;
962 int ret, remain_size, size;
963 const u8 *buf;
964
965 ath10k_hw_map_target_mem(ar, CPU_ADDR_MSB_REGION_VAL(address));
966
967 if (addr + length > REGION_ACCESS_SIZE_LIMIT) {
968 size = REGION_ACCESS_SIZE_LIMIT - addr;
969 remain_size = length - size;
970
971 ret = ath10k_hif_diag_write(ar, address, buffer, size);
972 if (ret) {
973 ath10k_warn(ar,
974 "failed to download the first %d bytes segment to address:0x%x: %d\n",
975 size, address, ret);
976 goto done;
977 }
978
979 /* Change msb to the next memory region*/
980 ath10k_hw_map_target_mem(ar,
981 CPU_ADDR_MSB_REGION_VAL(address) + 1);
982 buf = buffer + size;
983 ret = ath10k_hif_diag_write(ar,
984 address & ~REGION_ACCESS_SIZE_MASK,
985 buf, remain_size);
986 if (ret) {
987 ath10k_warn(ar,
988 "failed to download the second %d bytes segment to address:0x%x: %d\n",
989 remain_size,
990 address & ~REGION_ACCESS_SIZE_MASK,
991 ret);
992 goto done;
993 }
994 } else {
995 ret = ath10k_hif_diag_write(ar, address, buffer, length);
996 if (ret) {
997 ath10k_warn(ar,
998 "failed to download the only %d bytes segment to address:0x%x: %d\n",
999 length, address, ret);
1000 goto done;
1001 }
1002 }
1003
1004 done:
1005 /* Change msb to DRAM */
1006 ath10k_hw_map_target_mem(ar,
1007 CPU_ADDR_MSB_REGION_VAL(DRAM_BASE_ADDRESS));
1008 return ret;
1009 }
1010
ath10k_hw_diag_segment_download(struct ath10k * ar,const void * buffer,u32 address,u32 length)1011 static int ath10k_hw_diag_segment_download(struct ath10k *ar,
1012 const void *buffer,
1013 u32 address,
1014 u32 length)
1015 {
1016 if (address >= DRAM_BASE_ADDRESS + REGION_ACCESS_SIZE_LIMIT)
1017 /* Needs to change MSB for memory write */
1018 return ath10k_hw_diag_segment_msb_download(ar, buffer,
1019 address, length);
1020 else
1021 return ath10k_hif_diag_write(ar, address, buffer, length);
1022 }
1023
ath10k_hw_diag_fast_download(struct ath10k * ar,u32 address,const void * buffer,u32 length)1024 int ath10k_hw_diag_fast_download(struct ath10k *ar,
1025 u32 address,
1026 const void *buffer,
1027 u32 length)
1028 {
1029 const u8 *buf = buffer;
1030 bool sgmt_end = false;
1031 u32 base_addr = 0;
1032 u32 base_len = 0;
1033 u32 left = 0;
1034 #if defined(__linux__)
1035 struct bmi_segmented_file_header *hdr;
1036 struct bmi_segmented_metadata *metadata;
1037 #elif defined(__FreeBSD__)
1038 const struct bmi_segmented_file_header *hdr;
1039 const struct bmi_segmented_metadata *metadata;
1040 #endif
1041 int ret = 0;
1042
1043 if (length < sizeof(*hdr))
1044 return -EINVAL;
1045
1046 /* check firmware header. If it has no correct magic number
1047 * or it's compressed, returns error.
1048 */
1049 #if defined(__linux__)
1050 hdr = (struct bmi_segmented_file_header *)buf;
1051 #elif defined(__FreeBSD__)
1052 hdr = (const struct bmi_segmented_file_header *)buf;
1053 #endif
1054 if (__le32_to_cpu(hdr->magic_num) != BMI_SGMTFILE_MAGIC_NUM) {
1055 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1056 "Not a supported firmware, magic_num:0x%x\n",
1057 hdr->magic_num);
1058 return -EINVAL;
1059 }
1060
1061 if (hdr->file_flags != 0) {
1062 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1063 "Not a supported firmware, file_flags:0x%x\n",
1064 hdr->file_flags);
1065 return -EINVAL;
1066 }
1067
1068 #if defined(__linux__)
1069 metadata = (struct bmi_segmented_metadata *)hdr->data;
1070 #elif defined(__FreeBSD__)
1071 metadata = (const struct bmi_segmented_metadata *)hdr->data;
1072 #endif
1073 left = length - sizeof(*hdr);
1074
1075 while (left > 0) {
1076 if (left < sizeof(*metadata)) {
1077 ath10k_warn(ar, "firmware segment is truncated: %d\n",
1078 left);
1079 ret = -EINVAL;
1080 break;
1081 }
1082 base_addr = __le32_to_cpu(metadata->addr);
1083 base_len = __le32_to_cpu(metadata->length);
1084 buf = metadata->data;
1085 left -= sizeof(*metadata);
1086
1087 switch (base_len) {
1088 case BMI_SGMTFILE_BEGINADDR:
1089 /* base_addr is the start address to run */
1090 ret = ath10k_bmi_set_start(ar, base_addr);
1091 base_len = 0;
1092 break;
1093 case BMI_SGMTFILE_DONE:
1094 /* no more segment */
1095 base_len = 0;
1096 sgmt_end = true;
1097 ret = 0;
1098 break;
1099 case BMI_SGMTFILE_BDDATA:
1100 case BMI_SGMTFILE_EXEC:
1101 ath10k_warn(ar,
1102 "firmware has unsupported segment:%d\n",
1103 base_len);
1104 ret = -EINVAL;
1105 break;
1106 default:
1107 if (base_len > left) {
1108 /* sanity check */
1109 ath10k_warn(ar,
1110 "firmware has invalid segment length, %d > %d\n",
1111 base_len, left);
1112 ret = -EINVAL;
1113 break;
1114 }
1115
1116 ret = ath10k_hw_diag_segment_download(ar,
1117 buf,
1118 base_addr,
1119 base_len);
1120
1121 if (ret)
1122 ath10k_warn(ar,
1123 "failed to download firmware via diag interface:%d\n",
1124 ret);
1125 break;
1126 }
1127
1128 if (ret || sgmt_end)
1129 break;
1130
1131 #if defined(__linux__)
1132 metadata = (struct bmi_segmented_metadata *)(buf + base_len);
1133 #elif defined(__FreeBSD__)
1134 metadata = (const struct bmi_segmented_metadata *)(buf + base_len);
1135 #endif
1136 left -= base_len;
1137 }
1138
1139 if (ret == 0)
1140 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1141 "boot firmware fast diag download successfully.\n");
1142 return ret;
1143 }
1144
ath10k_htt_tx_rssi_enable(struct htt_resp * resp)1145 static int ath10k_htt_tx_rssi_enable(struct htt_resp *resp)
1146 {
1147 return (resp->data_tx_completion.flags2 & HTT_TX_CMPL_FLAG_DATA_RSSI);
1148 }
1149
ath10k_htt_tx_rssi_enable_wcn3990(struct htt_resp * resp)1150 static int ath10k_htt_tx_rssi_enable_wcn3990(struct htt_resp *resp)
1151 {
1152 return (resp->data_tx_completion.flags2 &
1153 HTT_TX_DATA_RSSI_ENABLE_WCN3990);
1154 }
1155
ath10k_get_htt_tx_data_rssi_pad(struct htt_resp * resp)1156 static int ath10k_get_htt_tx_data_rssi_pad(struct htt_resp *resp)
1157 {
1158 struct htt_data_tx_completion_ext extd;
1159 int pad_bytes = 0;
1160
1161 if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_RETRIES)
1162 pad_bytes += sizeof(extd.a_retries) /
1163 sizeof(extd.msdus_rssi[0]);
1164
1165 if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_TIMESTAMP)
1166 pad_bytes += sizeof(extd.t_stamp) / sizeof(extd.msdus_rssi[0]);
1167
1168 return pad_bytes;
1169 }
1170
1171 const struct ath10k_hw_ops qca988x_ops = {
1172 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
1173 .is_rssi_enable = ath10k_htt_tx_rssi_enable,
1174 };
1175
1176 const struct ath10k_hw_ops qca99x0_ops = {
1177 .is_rssi_enable = ath10k_htt_tx_rssi_enable,
1178 };
1179
1180 const struct ath10k_hw_ops qca6174_ops = {
1181 .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
1182 .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock,
1183 .is_rssi_enable = ath10k_htt_tx_rssi_enable,
1184 };
1185
1186 const struct ath10k_hw_ops qca6174_sdio_ops = {
1187 .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock,
1188 };
1189
1190 const struct ath10k_hw_ops wcn3990_ops = {
1191 .tx_data_rssi_pad_bytes = ath10k_get_htt_tx_data_rssi_pad,
1192 .is_rssi_enable = ath10k_htt_tx_rssi_enable_wcn3990,
1193 };
1194