1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2020 Joyent, Inc.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
33 * Copyright 2024 Oxide Computer Company
34 */
35
36 #include <sys/types.h>
37 #include <sys/thread.h>
38 #include <sys/cpuvar.h>
39 #include <sys/cpu.h>
40 #include <sys/t_lock.h>
41 #include <sys/param.h>
42 #include <sys/proc.h>
43 #include <sys/disp.h>
44 #include <sys/class.h>
45 #include <sys/cmn_err.h>
46 #include <sys/debug.h>
47 #include <sys/note.h>
48 #include <sys/asm_linkage.h>
49 #include <sys/x_call.h>
50 #include <sys/systm.h>
51 #include <sys/var.h>
52 #include <sys/vtrace.h>
53 #include <vm/hat.h>
54 #include <vm/as.h>
55 #include <vm/seg_kmem.h>
56 #include <vm/seg_kp.h>
57 #include <sys/segments.h>
58 #include <sys/kmem.h>
59 #include <sys/stack.h>
60 #include <sys/smp_impldefs.h>
61 #include <sys/x86_archext.h>
62 #include <sys/machsystm.h>
63 #include <sys/traptrace.h>
64 #include <sys/clock.h>
65 #include <sys/cpc_impl.h>
66 #include <sys/pg.h>
67 #include <sys/cmt.h>
68 #include <sys/dtrace.h>
69 #include <sys/archsystm.h>
70 #include <sys/fp.h>
71 #include <sys/reboot.h>
72 #include <sys/kdi_machimpl.h>
73 #include <vm/hat_i86.h>
74 #include <vm/vm_dep.h>
75 #include <sys/memnode.h>
76 #include <sys/pci_cfgspace.h>
77 #include <sys/mach_mmu.h>
78 #include <sys/sysmacros.h>
79 #if defined(__xpv)
80 #include <sys/hypervisor.h>
81 #else
82 #include <sys/hma.h>
83 #endif
84 #include <sys/cpu_module.h>
85 #include <sys/ontrap.h>
86
87 struct cpu cpus[1] __aligned(MMU_PAGESIZE);
88 struct cpu *cpu[NCPU] = {&cpus[0]};
89 struct cpu *cpu_free_list;
90 cpu_core_t cpu_core[NCPU];
91
92 #define cpu_next_free cpu_prev
93
94 /*
95 * Useful for disabling MP bring-up on a MP capable system.
96 */
97 int use_mp = 1;
98
99 /*
100 * to be set by a PSM to indicate what cpus
101 * are sitting around on the system.
102 */
103 cpuset_t mp_cpus;
104
105 /*
106 * This variable is used by the hat layer to decide whether or not
107 * critical sections are needed to prevent race conditions. For sun4m,
108 * this variable is set once enough MP initialization has been done in
109 * order to allow cross calls.
110 */
111 int flushes_require_xcalls;
112
113 cpuset_t cpu_ready_set; /* initialized in startup() */
114
115 static void mp_startup_boot(void);
116 static void mp_startup_hotplug(void);
117
118 static void cpu_sep_enable(void);
119 static void cpu_sep_disable(void);
120 static void cpu_asysc_enable(void);
121 static void cpu_asysc_disable(void);
122
123 /*
124 * Init CPU info - get CPU type info for processor_info system call.
125 */
126 void
init_cpu_info(struct cpu * cp)127 init_cpu_info(struct cpu *cp)
128 {
129 processor_info_t *pi = &cp->cpu_type_info;
130
131 /*
132 * Get clock-frequency property for the CPU.
133 */
134 pi->pi_clock = cpu_freq;
135
136 /*
137 * Current frequency in Hz.
138 */
139 cp->cpu_curr_clock = cpu_freq_hz;
140
141 /*
142 * Supported frequencies.
143 */
144 if (cp->cpu_supp_freqs == NULL) {
145 cpu_set_supp_freqs(cp, NULL);
146 }
147
148 (void) strcpy(pi->pi_processor_type, "i386");
149 if (fpu_exists)
150 (void) strcpy(pi->pi_fputypes, "i387 compatible");
151
152 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
153 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
154
155 /*
156 * If called for the BSP, cp is equal to current CPU.
157 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
158 * of current CPU as default values for cpu_idstr and cpu_brandstr.
159 * They will be corrected in mp_startup_common() after
160 * CPUID_PASS_DYNAMIC has been invoked on target CPU.
161 */
162 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
163 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
164 }
165
166 /*
167 * Configure syscall support on this CPU.
168 */
169 /*ARGSUSED*/
170 void
init_cpu_syscall(struct cpu * cp)171 init_cpu_syscall(struct cpu *cp)
172 {
173 kpreempt_disable();
174
175 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
176 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
177 uint64_t flags;
178
179 #if !defined(__xpv)
180 /*
181 * The syscall instruction imposes a certain ordering on
182 * segment selectors, so we double-check that ordering
183 * here.
184 */
185 CTASSERT(KDS_SEL == KCS_SEL + 8);
186 CTASSERT(UDS_SEL == U32CS_SEL + 8);
187 CTASSERT(UCS_SEL == U32CS_SEL + 16);
188 #endif
189
190 /*
191 * Turn syscall/sysret extensions on.
192 */
193 cpu_asysc_enable();
194
195 /*
196 * Program the magic registers ..
197 */
198 wrmsr(MSR_AMD_STAR,
199 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
200 if (kpti_enable == 1) {
201 wrmsr(MSR_AMD_LSTAR,
202 (uint64_t)(uintptr_t)tr_sys_syscall);
203 wrmsr(MSR_AMD_CSTAR,
204 (uint64_t)(uintptr_t)tr_sys_syscall32);
205 } else {
206 wrmsr(MSR_AMD_LSTAR,
207 (uint64_t)(uintptr_t)sys_syscall);
208 wrmsr(MSR_AMD_CSTAR,
209 (uint64_t)(uintptr_t)sys_syscall32);
210 }
211
212 /*
213 * This list of flags is masked off the incoming
214 * %rfl when we enter the kernel.
215 */
216 flags = PS_IE | PS_T;
217 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
218 flags |= PS_ACHK;
219 wrmsr(MSR_AMD_SFMASK, flags);
220 }
221
222 /*
223 * On 64-bit kernels on Nocona machines, the 32-bit syscall
224 * variant isn't available to 32-bit applications, but sysenter is.
225 */
226 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
227 is_x86_feature(x86_featureset, X86FSET_SEP)) {
228
229 #if !defined(__xpv)
230 /*
231 * The sysenter instruction imposes a certain ordering on
232 * segment selectors, so we double-check that ordering
233 * here. See "sysenter" in Intel document 245471-012, "IA-32
234 * Intel Architecture Software Developer's Manual Volume 2:
235 * Instruction Set Reference"
236 */
237 CTASSERT(KDS_SEL == KCS_SEL + 8);
238
239 CTASSERT(U32CS_SEL == ((KCS_SEL + 16) | 3));
240 CTASSERT(UDS_SEL == U32CS_SEL + 8);
241 #endif
242
243 cpu_sep_enable();
244
245 /*
246 * resume() sets this value to the base of the threads stack
247 * via a context handler.
248 */
249 wrmsr(MSR_INTC_SEP_ESP, 0);
250
251 if (kpti_enable == 1) {
252 wrmsr(MSR_INTC_SEP_EIP,
253 (uint64_t)(uintptr_t)tr_sys_sysenter);
254 } else {
255 wrmsr(MSR_INTC_SEP_EIP,
256 (uint64_t)(uintptr_t)sys_sysenter);
257 }
258 }
259
260 kpreempt_enable();
261 }
262
263 #if !defined(__xpv)
264 /*
265 * Configure per-cpu ID GDT
266 */
267 static void
init_cpu_id_gdt(struct cpu * cp)268 init_cpu_id_gdt(struct cpu *cp)
269 {
270 /* Write cpu_id into limit field of GDT for usermode retrieval */
271 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
272 SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
273 }
274 #endif /* !defined(__xpv) */
275
276 /*
277 * Multiprocessor initialization.
278 *
279 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
280 * startup and idle threads for the specified CPU.
281 * Parameter boot is true for boot time operations and is false for CPU
282 * DR operations.
283 */
284 static struct cpu *
mp_cpu_configure_common(int cpun,boolean_t boot)285 mp_cpu_configure_common(int cpun, boolean_t boot)
286 {
287 struct cpu *cp;
288 kthread_id_t tp;
289 caddr_t sp;
290 proc_t *procp;
291 #if !defined(__xpv)
292 extern int idle_cpu_prefer_mwait;
293 extern void cpu_idle_mwait();
294 #endif
295 extern void idle();
296 extern void cpu_idle();
297
298 #ifdef TRAPTRACE
299 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
300 #endif
301
302 ASSERT(MUTEX_HELD(&cpu_lock));
303 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
304
305 if (cpu_free_list == NULL) {
306 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
307 } else {
308 cp = cpu_free_list;
309 cpu_free_list = cp->cpu_next_free;
310 }
311
312 cp->cpu_m.mcpu_istamp = cpun << 16;
313
314 /* Create per CPU specific threads in the process p0. */
315 procp = &p0;
316
317 /*
318 * Initialize the dispatcher first.
319 */
320 disp_cpu_init(cp);
321
322 cpu_vm_data_init(cp);
323
324 /*
325 * Allocate and initialize the startup thread for this CPU.
326 * Interrupt and process switch stacks get allocated later
327 * when the CPU starts running.
328 */
329 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
330 TS_STOPPED, maxclsyspri);
331
332 /*
333 * Set state to TS_ONPROC since this thread will start running
334 * as soon as the CPU comes online.
335 *
336 * All the other fields of the thread structure are setup by
337 * thread_create().
338 */
339 THREAD_ONPROC(tp, cp);
340 tp->t_preempt = 1;
341 tp->t_bound_cpu = cp;
342 tp->t_affinitycnt = 1;
343 tp->t_cpu = cp;
344 tp->t_disp_queue = cp->cpu_disp;
345
346 /*
347 * Setup thread to start in mp_startup_common.
348 */
349 sp = tp->t_stk;
350 tp->t_sp = (uintptr_t)(sp - MINFRAME);
351 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
352 /*
353 * Setup thread start entry point for boot or hotplug.
354 */
355 if (boot) {
356 tp->t_pc = (uintptr_t)mp_startup_boot;
357 } else {
358 tp->t_pc = (uintptr_t)mp_startup_hotplug;
359 }
360
361 cp->cpu_id = cpun;
362 cp->cpu_self = cp;
363 cp->cpu_thread = tp;
364 cp->cpu_lwp = NULL;
365 cp->cpu_dispthread = tp;
366 cp->cpu_dispatch_pri = DISP_PRIO(tp);
367
368 /*
369 * cpu_base_spl must be set explicitly here to prevent any blocking
370 * operations in mp_startup_common from causing the spl of the cpu
371 * to drop to 0 (allowing device interrupts before we're ready) in
372 * resume().
373 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
374 * As an extra bit of security on DEBUG kernels, this is enforced with
375 * an assertion in mp_startup_common() -- before cpu_base_spl is set
376 * to its proper value.
377 */
378 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
379
380 /*
381 * Now, initialize per-CPU idle thread for this CPU.
382 */
383 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
384
385 cp->cpu_idle_thread = tp;
386
387 tp->t_preempt = 1;
388 tp->t_bound_cpu = cp;
389 tp->t_affinitycnt = 1;
390 tp->t_cpu = cp;
391 tp->t_disp_queue = cp->cpu_disp;
392
393 /*
394 * Bootstrap the CPU's PG data
395 */
396 pg_cpu_bootstrap(cp);
397
398 /*
399 * Perform CPC initialization on the new CPU.
400 */
401 kcpc_hw_init(cp);
402
403 /*
404 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
405 * for each CPU.
406 */
407 setup_vaddr_for_ppcopy(cp);
408
409 /*
410 * Allocate page for new GDT and initialize from current GDT.
411 */
412 #if !defined(__lint)
413 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
414 #endif
415 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
416 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
417
418
419 /*
420 * Allocate pages for the CPU LDT.
421 */
422 cp->cpu_m.mcpu_ldt = kmem_zalloc(LDT_CPU_SIZE, KM_SLEEP);
423 cp->cpu_m.mcpu_ldt_len = 0;
424
425 /*
426 * Allocate a per-CPU IDT and initialize the new IDT to the currently
427 * runing CPU.
428 */
429 #if !defined(__lint)
430 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
431 #endif
432 cp->cpu_idt = kmem_alloc(PAGESIZE, KM_SLEEP);
433 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
434
435 /*
436 * alloc space for cpuid info
437 */
438 cpuid_alloc_space(cp);
439 #if !defined(__xpv)
440 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
441 idle_cpu_prefer_mwait) {
442 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
443 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
444 } else
445 #endif
446 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
447
448 init_cpu_info(cp);
449
450 #if !defined(__xpv)
451 init_cpu_id_gdt(cp);
452 #endif
453
454 /*
455 * alloc space for ucode_info
456 */
457 ucode_alloc_space(cp);
458 xc_init_cpu(cp);
459 hat_cpu_online(cp);
460
461 #ifdef TRAPTRACE
462 /*
463 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
464 */
465 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
466 ttc->ttc_next = ttc->ttc_first;
467 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
468 #endif
469
470 /*
471 * Record that we have another CPU.
472 */
473 /*
474 * Initialize the interrupt threads for this CPU
475 */
476 cpu_intr_alloc(cp, NINTR_THREADS);
477
478 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
479 cpu_set_state(cp);
480
481 /*
482 * Add CPU to list of available CPUs. It'll be on the active list
483 * after mp_startup_common().
484 */
485 cpu_add_unit(cp);
486
487 return (cp);
488 }
489
490 /*
491 * Undo what was done in mp_cpu_configure_common
492 */
493 static void
mp_cpu_unconfigure_common(struct cpu * cp,int error)494 mp_cpu_unconfigure_common(struct cpu *cp, int error)
495 {
496 ASSERT(MUTEX_HELD(&cpu_lock));
497
498 /*
499 * Remove the CPU from the list of available CPUs.
500 */
501 cpu_del_unit(cp->cpu_id);
502
503 if (error == ETIMEDOUT) {
504 /*
505 * The cpu was started, but never *seemed* to run any
506 * code in the kernel; it's probably off spinning in its
507 * own private world, though with potential references to
508 * our kmem-allocated IDTs and GDTs (for example).
509 *
510 * Worse still, it may actually wake up some time later,
511 * so rather than guess what it might or might not do, we
512 * leave the fundamental data structures intact.
513 */
514 cp->cpu_flags = 0;
515 return;
516 }
517
518 /*
519 * At this point, the only threads bound to this CPU should
520 * special per-cpu threads: it's idle thread, it's pause threads,
521 * and it's interrupt threads. Clean these up.
522 */
523 cpu_destroy_bound_threads(cp);
524 cp->cpu_idle_thread = NULL;
525
526 /*
527 * Free the interrupt stack.
528 */
529 segkp_release(segkp,
530 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
531 cp->cpu_intr_stack = NULL;
532
533 #ifdef TRAPTRACE
534 /*
535 * Discard the trap trace buffer
536 */
537 {
538 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
539
540 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
541 ttc->ttc_first = (uintptr_t)NULL;
542 }
543 #endif
544
545 hat_cpu_offline(cp);
546
547 ucode_free_space(cp);
548
549 /* Free CPU ID string and brand string. */
550 if (cp->cpu_idstr) {
551 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
552 cp->cpu_idstr = NULL;
553 }
554 if (cp->cpu_brandstr) {
555 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
556 cp->cpu_brandstr = NULL;
557 }
558
559 #if !defined(__xpv)
560 if (cp->cpu_m.mcpu_mwait != NULL) {
561 cpuid_mwait_free(cp);
562 cp->cpu_m.mcpu_mwait = NULL;
563 }
564 #endif
565 cpuid_free_space(cp);
566
567 if (cp->cpu_idt != CPU->cpu_idt)
568 kmem_free(cp->cpu_idt, PAGESIZE);
569 cp->cpu_idt = NULL;
570
571 kmem_free(cp->cpu_m.mcpu_ldt, LDT_CPU_SIZE);
572 cp->cpu_m.mcpu_ldt = NULL;
573 cp->cpu_m.mcpu_ldt_len = 0;
574
575 kmem_free(cp->cpu_gdt, PAGESIZE);
576 cp->cpu_gdt = NULL;
577
578 if (cp->cpu_supp_freqs != NULL) {
579 size_t len = strlen(cp->cpu_supp_freqs) + 1;
580 kmem_free(cp->cpu_supp_freqs, len);
581 cp->cpu_supp_freqs = NULL;
582 }
583
584 teardown_vaddr_for_ppcopy(cp);
585
586 kcpc_hw_fini(cp);
587
588 cp->cpu_dispthread = NULL;
589 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
590
591 cpu_vm_data_destroy(cp);
592
593 xc_fini_cpu(cp);
594 disp_cpu_fini(cp);
595
596 ASSERT(cp != CPU0);
597 bzero(cp, sizeof (*cp));
598 cp->cpu_next_free = cpu_free_list;
599 cpu_free_list = cp;
600 }
601
602 /*
603 * Apply workarounds for known errata, and warn about those that are absent.
604 *
605 * System vendors occasionally create configurations which contain different
606 * revisions of the CPUs that are almost but not exactly the same. At the
607 * time of writing, this meant that their clock rates were the same, their
608 * feature sets were the same, but the required workaround were -not-
609 * necessarily the same. So, this routine is invoked on -every- CPU soon
610 * after starting to make sure that the resulting system contains the most
611 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
612 * system.
613 *
614 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
615 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
616 * prior to acknowledging their readiness to the master, so this routine will
617 * never be executed by multiple CPUs in parallel, thus making updates to
618 * global data safe.
619 *
620 * These workarounds are based on Rev 3.57 of the Revision Guide for
621 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
622 */
623
624 #if defined(OPTERON_ERRATUM_88)
625 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
626 #endif
627
628 #if defined(OPTERON_ERRATUM_91)
629 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
630 #endif
631
632 #if defined(OPTERON_ERRATUM_93)
633 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
634 #endif
635
636 #if defined(OPTERON_ERRATUM_95)
637 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
638 #endif
639
640 #if defined(OPTERON_ERRATUM_100)
641 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
642 #endif
643
644 #if defined(OPTERON_ERRATUM_108)
645 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
646 #endif
647
648 #if defined(OPTERON_ERRATUM_109)
649 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
650 #endif
651
652 #if defined(OPTERON_ERRATUM_121)
653 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
654 #endif
655
656 #if defined(OPTERON_ERRATUM_122)
657 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
658 #endif
659
660 #if defined(OPTERON_ERRATUM_123)
661 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
662 #endif
663
664 #if defined(OPTERON_ERRATUM_131)
665 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
666 #endif
667
668 #if defined(OPTERON_WORKAROUND_6336786)
669 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
670 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
671 #endif
672
673 #if defined(OPTERON_ERRATUM_147)
674 int opteron_erratum_147; /* if non-zero -> at least one cpu has it */
675 #endif
676
677 #if defined(OPTERON_ERRATUM_298)
678 int opteron_erratum_298;
679 #endif
680
681 #if defined(OPTERON_ERRATUM_721)
682 int opteron_erratum_721;
683 #endif
684
685 static void
workaround_warning(cpu_t * cp,uint_t erratum)686 workaround_warning(cpu_t *cp, uint_t erratum)
687 {
688 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
689 cp->cpu_id, erratum);
690 }
691
692 static void
workaround_applied(uint_t erratum)693 workaround_applied(uint_t erratum)
694 {
695 if (erratum > 1000000)
696 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
697 erratum);
698 else
699 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
700 erratum);
701 }
702
703 static void
msr_warning(cpu_t * cp,const char * rw,uint_t msr,int error)704 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
705 {
706 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
707 cp->cpu_id, rw, msr, error);
708 }
709
710 /*
711 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
712 * system.
713 */
714 static uint_t
opteron_get_nnodes(void)715 opteron_get_nnodes(void)
716 {
717 static uint_t nnodes = 0;
718
719 if (nnodes == 0) {
720 #ifdef DEBUG
721 uint_t family;
722
723 /*
724 * This routine uses a PCI config space based mechanism
725 * for retrieving the number of nodes in the system.
726 * Device 24, function 0, offset 0x60 as used here is not
727 * AMD processor architectural, and may not work on processor
728 * families other than those listed below.
729 *
730 * Callers of this routine must ensure that we're running on
731 * a processor which supports this mechanism.
732 * The assertion below is meant to catch calls on unsupported
733 * processors.
734 */
735 family = cpuid_getfamily(CPU);
736 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
737 #endif /* DEBUG */
738
739 /*
740 * Obtain the number of nodes in the system from
741 * bits [6:4] of the Node ID register on node 0.
742 *
743 * The actual node count is NodeID[6:4] + 1
744 *
745 * The Node ID register is accessed via function 0,
746 * offset 0x60. Node 0 is device 24.
747 */
748 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
749 }
750 return (nnodes);
751 }
752
753 uint_t
do_erratum_298(struct cpu * cpu)754 do_erratum_298(struct cpu *cpu)
755 {
756 static int osvwrc = -3;
757 extern int osvw_opteron_erratum(cpu_t *, uint_t);
758
759 /*
760 * L2 Eviction May Occur During Processor Operation To Set
761 * Accessed or Dirty Bit.
762 */
763 if (osvwrc == -3) {
764 osvwrc = osvw_opteron_erratum(cpu, 298);
765 } else {
766 /* osvw return codes should be consistent for all cpus */
767 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
768 }
769
770 switch (osvwrc) {
771 case 0: /* erratum is not present: do nothing */
772 break;
773 case 1: /* erratum is present: BIOS workaround applied */
774 /*
775 * check if workaround is actually in place and issue warning
776 * if not.
777 */
778 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
779 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
780 #if defined(OPTERON_ERRATUM_298)
781 opteron_erratum_298++;
782 #else
783 workaround_warning(cpu, 298);
784 return (1);
785 #endif
786 }
787 break;
788 case -1: /* cannot determine via osvw: check cpuid */
789 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
790 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
791 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
792 #if defined(OPTERON_ERRATUM_298)
793 opteron_erratum_298++;
794 #else
795 workaround_warning(cpu, 298);
796 return (1);
797 #endif
798 }
799 break;
800 }
801 return (0);
802 }
803
804 uint_t
workaround_errata(struct cpu * cpu)805 workaround_errata(struct cpu *cpu)
806 {
807 volatile uint_t missing = 0;
808
809 ASSERT(cpu == CPU);
810
811 /*LINTED*/
812 if (cpuid_opteron_erratum(cpu, 88) > 0) {
813 /*
814 * SWAPGS May Fail To Read Correct GS Base
815 */
816 #if defined(OPTERON_ERRATUM_88)
817 /*
818 * The workaround is an mfence in the relevant assembler code
819 */
820 opteron_erratum_88++;
821 #else
822 workaround_warning(cpu, 88);
823 missing++;
824 #endif
825 }
826
827 if (cpuid_opteron_erratum(cpu, 91) > 0) {
828 /*
829 * Software Prefetches May Report A Page Fault
830 */
831 #if defined(OPTERON_ERRATUM_91)
832 /*
833 * fix is in trap.c
834 */
835 opteron_erratum_91++;
836 #else
837 workaround_warning(cpu, 91);
838 missing++;
839 #endif
840 }
841
842 if (cpuid_opteron_erratum(cpu, 93) > 0) {
843 /*
844 * RSM Auto-Halt Restart Returns to Incorrect RIP
845 */
846 #if defined(OPTERON_ERRATUM_93)
847 /*
848 * fix is in trap.c
849 */
850 opteron_erratum_93++;
851 #else
852 workaround_warning(cpu, 93);
853 missing++;
854 #endif
855 }
856
857 /*LINTED*/
858 if (cpuid_opteron_erratum(cpu, 95) > 0) {
859 /*
860 * RET Instruction May Return to Incorrect EIP
861 */
862 #if defined(OPTERON_ERRATUM_95)
863 #if defined(_LP64)
864 /*
865 * Workaround this by ensuring that 32-bit user code and
866 * 64-bit kernel code never occupy the same address
867 * range mod 4G.
868 */
869 if (_userlimit32 > 0xc0000000ul)
870 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
871
872 /*LINTED*/
873 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
874 opteron_erratum_95++;
875 #endif /* _LP64 */
876 #else
877 workaround_warning(cpu, 95);
878 missing++;
879 #endif
880 }
881
882 if (cpuid_opteron_erratum(cpu, 100) > 0) {
883 /*
884 * Compatibility Mode Branches Transfer to Illegal Address
885 */
886 #if defined(OPTERON_ERRATUM_100)
887 /*
888 * fix is in trap.c
889 */
890 opteron_erratum_100++;
891 #else
892 workaround_warning(cpu, 100);
893 missing++;
894 #endif
895 }
896
897 /*LINTED*/
898 if (cpuid_opteron_erratum(cpu, 108) > 0) {
899 /*
900 * CPUID Instruction May Return Incorrect Model Number In
901 * Some Processors
902 */
903 #if defined(OPTERON_ERRATUM_108)
904 /*
905 * (Our cpuid-handling code corrects the model number on
906 * those processors)
907 */
908 #else
909 workaround_warning(cpu, 108);
910 missing++;
911 #endif
912 }
913
914 /*LINTED*/
915 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
916 /*
917 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
918 */
919 #if defined(OPTERON_ERRATUM_109)
920 /*
921 * The "workaround" is to print a warning to upgrade the BIOS
922 */
923 uint64_t value;
924 const uint_t msr = MSR_AMD_PATCHLEVEL;
925 int err;
926
927 if ((err = checked_rdmsr(msr, &value)) != 0) {
928 msr_warning(cpu, "rd", msr, err);
929 workaround_warning(cpu, 109);
930 missing++;
931 }
932 if (value == 0)
933 opteron_erratum_109++;
934 #else
935 workaround_warning(cpu, 109);
936 missing++;
937 #endif
938 /*CONSTANTCONDITION*/
939 } while (0);
940
941 /*LINTED*/
942 if (cpuid_opteron_erratum(cpu, 121) > 0) {
943 /*
944 * Sequential Execution Across Non_Canonical Boundary Caused
945 * Processor Hang
946 */
947 #if defined(OPTERON_ERRATUM_121)
948 #if defined(_LP64)
949 /*
950 * Erratum 121 is only present in long (64 bit) mode.
951 * Workaround is to include the page immediately before the
952 * va hole to eliminate the possibility of system hangs due to
953 * sequential execution across the va hole boundary.
954 */
955 if (opteron_erratum_121)
956 opteron_erratum_121++;
957 else {
958 if (hole_start) {
959 hole_start -= PAGESIZE;
960 } else {
961 /*
962 * hole_start not yet initialized by
963 * mmu_init. Initialize hole_start
964 * with value to be subtracted.
965 */
966 hole_start = PAGESIZE;
967 }
968 opteron_erratum_121++;
969 }
970 #endif /* _LP64 */
971 #else
972 workaround_warning(cpu, 121);
973 missing++;
974 #endif
975 }
976
977 /*LINTED*/
978 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
979 /*
980 * TLB Flush Filter May Cause Coherency Problem in
981 * Multiprocessor Systems
982 */
983 #if defined(OPTERON_ERRATUM_122)
984 uint64_t value;
985 const uint_t msr = MSR_AMD_HWCR;
986 int error;
987
988 /*
989 * Erratum 122 is only present in MP configurations (multi-core
990 * or multi-processor).
991 */
992 #if defined(__xpv)
993 if (!DOMAIN_IS_INITDOMAIN(xen_info))
994 break;
995 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
996 break;
997 #else
998 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
999 cpuid_get_ncpu_per_chip(cpu) == 1)
1000 break;
1001 #endif
1002 /* disable TLB Flush Filter */
1003
1004 if ((error = checked_rdmsr(msr, &value)) != 0) {
1005 msr_warning(cpu, "rd", msr, error);
1006 workaround_warning(cpu, 122);
1007 missing++;
1008 } else {
1009 value |= (uint64_t)AMD_HWCR_FFDIS;
1010 if ((error = checked_wrmsr(msr, value)) != 0) {
1011 msr_warning(cpu, "wr", msr, error);
1012 workaround_warning(cpu, 122);
1013 missing++;
1014 }
1015 }
1016 opteron_erratum_122++;
1017 #else
1018 workaround_warning(cpu, 122);
1019 missing++;
1020 #endif
1021 /*CONSTANTCONDITION*/
1022 } while (0);
1023
1024 /*LINTED*/
1025 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1026 /*
1027 * Bypassed Reads May Cause Data Corruption of System Hang in
1028 * Dual Core Processors
1029 */
1030 #if defined(OPTERON_ERRATUM_123)
1031 uint64_t value;
1032 const uint_t msr = MSR_AMD_PATCHLEVEL;
1033 int err;
1034
1035 /*
1036 * Erratum 123 applies only to multi-core cpus.
1037 */
1038 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1039 break;
1040 #if defined(__xpv)
1041 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1042 break;
1043 #endif
1044 /*
1045 * The "workaround" is to print a warning to upgrade the BIOS
1046 */
1047 if ((err = checked_rdmsr(msr, &value)) != 0) {
1048 msr_warning(cpu, "rd", msr, err);
1049 workaround_warning(cpu, 123);
1050 missing++;
1051 }
1052 if (value == 0)
1053 opteron_erratum_123++;
1054 #else
1055 workaround_warning(cpu, 123);
1056 missing++;
1057
1058 #endif
1059 /*CONSTANTCONDITION*/
1060 } while (0);
1061
1062 /*LINTED*/
1063 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1064 /*
1065 * Multiprocessor Systems with Four or More Cores May Deadlock
1066 * Waiting for a Probe Response
1067 */
1068 #if defined(OPTERON_ERRATUM_131)
1069 uint64_t nbcfg;
1070 const uint_t msr = MSR_AMD_NB_CFG;
1071 const uint64_t wabits =
1072 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1073 int error;
1074
1075 /*
1076 * Erratum 131 applies to any system with four or more cores.
1077 */
1078 if (opteron_erratum_131)
1079 break;
1080 #if defined(__xpv)
1081 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1082 break;
1083 if (xpv_nr_phys_cpus() < 4)
1084 break;
1085 #else
1086 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1087 break;
1088 #endif
1089 /*
1090 * Print a warning if neither of the workarounds for
1091 * erratum 131 is present.
1092 */
1093 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1094 msr_warning(cpu, "rd", msr, error);
1095 workaround_warning(cpu, 131);
1096 missing++;
1097 } else if ((nbcfg & wabits) == 0) {
1098 opteron_erratum_131++;
1099 } else {
1100 /* cannot have both workarounds set */
1101 ASSERT((nbcfg & wabits) != wabits);
1102 }
1103 #else
1104 workaround_warning(cpu, 131);
1105 missing++;
1106 #endif
1107 /*CONSTANTCONDITION*/
1108 } while (0);
1109
1110 /*
1111 * This isn't really an erratum, but for convenience the
1112 * detection/workaround code lives here and in cpuid_opteron_erratum.
1113 * Note, the technique only is valid on families before 12h and
1114 * certainly doesn't work when we're virtualized. This is checked for in
1115 * the erratum workaround.
1116 */
1117 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1118 #if defined(OPTERON_WORKAROUND_6336786)
1119 /*
1120 * Disable C1-Clock ramping on multi-core/multi-processor
1121 * K8 platforms to guard against TSC drift.
1122 */
1123 if (opteron_workaround_6336786) {
1124 opteron_workaround_6336786++;
1125 #if defined(__xpv)
1126 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1127 xpv_nr_phys_cpus() > 1) ||
1128 opteron_workaround_6336786_UP) {
1129 /*
1130 * XXPV Hmm. We can't walk the Northbridges on
1131 * the hypervisor; so just complain and drive
1132 * on. This probably needs to be fixed in
1133 * the hypervisor itself.
1134 */
1135 opteron_workaround_6336786++;
1136 workaround_warning(cpu, 6336786);
1137 #else /* __xpv */
1138 } else if ((opteron_get_nnodes() *
1139 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1140 opteron_workaround_6336786_UP) {
1141
1142 uint_t node, nnodes;
1143 uint8_t data;
1144
1145 nnodes = opteron_get_nnodes();
1146 for (node = 0; node < nnodes; node++) {
1147 /*
1148 * Clear PMM7[1:0] (function 3, offset 0x87)
1149 * Northbridge device is the node id + 24.
1150 */
1151 data = pci_getb_func(0, node + 24, 3, 0x87);
1152 data &= 0xFC;
1153 pci_putb_func(0, node + 24, 3, 0x87, data);
1154 }
1155 opteron_workaround_6336786++;
1156 #endif /* __xpv */
1157 }
1158 #else
1159 workaround_warning(cpu, 6336786);
1160 missing++;
1161 #endif
1162 }
1163
1164 /*LINTED*/
1165 /*
1166 * Mutex primitives don't work as expected. This is erratum #147 from
1167 * 'Revision Guide for AMD Athlon 64 and AMD Opteron Processors'
1168 * document 25759.
1169 */
1170 if (cpuid_opteron_erratum(cpu, 147) > 0) {
1171 #if defined(OPTERON_ERRATUM_147)
1172 /*
1173 * This problem only occurs with 2 or more cores. If bit in
1174 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1175 * is to patch the semaphone routines with the lfence
1176 * instruction to provide necessary load memory barrier with
1177 * possible subsequent read-modify-write ops.
1178 *
1179 * It is too early in boot to call the patch routine so
1180 * set erratum variable to be done in startup_end().
1181 */
1182 if (opteron_erratum_147) {
1183 opteron_erratum_147++;
1184 #if defined(__xpv)
1185 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1186 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1187 /*
1188 * XXPV Use dom0_msr here when extended
1189 * operations are supported?
1190 */
1191 if (xpv_nr_phys_cpus() > 1)
1192 opteron_erratum_147++;
1193 } else {
1194 /*
1195 * We have no way to tell how many physical
1196 * cpus there are, or even if this processor
1197 * has the problem, so enable the workaround
1198 * unconditionally (at some performance cost).
1199 */
1200 opteron_erratum_147++;
1201 }
1202 #else /* __xpv */
1203 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1204 ((opteron_get_nnodes() *
1205 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1206 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1207 opteron_erratum_147++;
1208 #endif /* __xpv */
1209 }
1210 #else
1211 workaround_warning(cpu, 147);
1212 missing++;
1213 #endif
1214 }
1215
1216 missing += do_erratum_298(cpu);
1217
1218 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1219 #if defined(OPTERON_ERRATUM_721)
1220 on_trap_data_t otd;
1221
1222 if (!on_trap(&otd, OT_DATA_ACCESS))
1223 wrmsr(MSR_AMD_DE_CFG,
1224 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1225 no_trap();
1226
1227 opteron_erratum_721++;
1228 #else
1229 workaround_warning(cpu, 721);
1230 missing++;
1231 #endif
1232 }
1233
1234 #ifdef __xpv
1235 return (0);
1236 #else
1237 return (missing);
1238 #endif
1239 }
1240
1241 void
workaround_errata_end()1242 workaround_errata_end()
1243 {
1244 #if defined(OPTERON_ERRATUM_88)
1245 if (opteron_erratum_88)
1246 workaround_applied(88);
1247 #endif
1248 #if defined(OPTERON_ERRATUM_91)
1249 if (opteron_erratum_91)
1250 workaround_applied(91);
1251 #endif
1252 #if defined(OPTERON_ERRATUM_93)
1253 if (opteron_erratum_93)
1254 workaround_applied(93);
1255 #endif
1256 #if defined(OPTERON_ERRATUM_95)
1257 if (opteron_erratum_95)
1258 workaround_applied(95);
1259 #endif
1260 #if defined(OPTERON_ERRATUM_100)
1261 if (opteron_erratum_100)
1262 workaround_applied(100);
1263 #endif
1264 #if defined(OPTERON_ERRATUM_108)
1265 if (opteron_erratum_108)
1266 workaround_applied(108);
1267 #endif
1268 #if defined(OPTERON_ERRATUM_109)
1269 if (opteron_erratum_109) {
1270 cmn_err(CE_WARN,
1271 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1272 " processor\nerratum 109 was not detected; updating your"
1273 " system's BIOS to a version\ncontaining this"
1274 " microcode patch is HIGHLY recommended or erroneous"
1275 " system\noperation may occur.\n");
1276 }
1277 #endif
1278 #if defined(OPTERON_ERRATUM_121)
1279 if (opteron_erratum_121)
1280 workaround_applied(121);
1281 #endif
1282 #if defined(OPTERON_ERRATUM_122)
1283 if (opteron_erratum_122)
1284 workaround_applied(122);
1285 #endif
1286 #if defined(OPTERON_ERRATUM_123)
1287 if (opteron_erratum_123) {
1288 cmn_err(CE_WARN,
1289 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1290 " processor\nerratum 123 was not detected; updating your"
1291 " system's BIOS to a version\ncontaining this"
1292 " microcode patch is HIGHLY recommended or erroneous"
1293 " system\noperation may occur.\n");
1294 }
1295 #endif
1296 #if defined(OPTERON_ERRATUM_131)
1297 if (opteron_erratum_131) {
1298 cmn_err(CE_WARN,
1299 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1300 " processor\nerratum 131 was not detected; updating your"
1301 " system's BIOS to a version\ncontaining this"
1302 " microcode patch is HIGHLY recommended or erroneous"
1303 " system\noperation may occur.\n");
1304 }
1305 #endif
1306 #if defined(OPTERON_WORKAROUND_6336786)
1307 if (opteron_workaround_6336786)
1308 workaround_applied(6336786);
1309 #endif
1310 #if defined(OPTERON_ERRATUM_147)
1311 if (opteron_erratum_147)
1312 workaround_applied(147);
1313 #endif
1314 #if defined(OPTERON_ERRATUM_298)
1315 if (opteron_erratum_298) {
1316 cmn_err(CE_WARN,
1317 "BIOS microcode patch for AMD 64/Opteron(tm)"
1318 " processor\nerratum 298 was not detected; updating your"
1319 " system's BIOS to a version\ncontaining this"
1320 " microcode patch is HIGHLY recommended or erroneous"
1321 " system\noperation may occur.\n");
1322 }
1323 #endif
1324 #if defined(OPTERON_ERRATUM_721)
1325 if (opteron_erratum_721)
1326 workaround_applied(721);
1327 #endif
1328 }
1329
1330 /*
1331 * The procset_slave and procset_master are used to synchronize
1332 * between the control CPU and the target CPU when starting CPUs.
1333 */
1334 static cpuset_t procset_slave, procset_master;
1335
1336 static void
mp_startup_wait(cpuset_t * sp,processorid_t cpuid)1337 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1338 {
1339 cpuset_t tempset;
1340
1341 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1342 tempset = *(volatile cpuset_t *)sp) {
1343 SMT_PAUSE();
1344 }
1345 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1346 }
1347
1348 static void
mp_startup_signal(cpuset_t * sp,processorid_t cpuid)1349 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1350 {
1351 cpuset_t tempset;
1352
1353 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1354 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1355 tempset = *(volatile cpuset_t *)sp) {
1356 SMT_PAUSE();
1357 }
1358 }
1359
1360 int
mp_start_cpu_common(cpu_t * cp,boolean_t boot)1361 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1362 {
1363 _NOTE(ARGUNUSED(boot));
1364
1365 void *ctx;
1366 int delays;
1367 int error = 0;
1368 cpuset_t tempset;
1369 processorid_t cpuid;
1370 #ifndef __xpv
1371 extern void cpupm_init(cpu_t *);
1372 #endif
1373
1374 ASSERT(cp != NULL);
1375 cpuid = cp->cpu_id;
1376 ctx = mach_cpucontext_alloc(cp);
1377 if (ctx == NULL) {
1378 cmn_err(CE_WARN,
1379 "cpu%d: failed to allocate context", cp->cpu_id);
1380 return (EAGAIN);
1381 }
1382 error = mach_cpu_start(cp, ctx);
1383 if (error != 0) {
1384 cmn_err(CE_WARN,
1385 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1386 mach_cpucontext_free(cp, ctx, error);
1387 return (error);
1388 }
1389
1390 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1391 delays++) {
1392 if (delays == 500) {
1393 /*
1394 * After five seconds, things are probably looking
1395 * a bit bleak - explain the hang.
1396 */
1397 cmn_err(CE_NOTE, "cpu%d: started, "
1398 "but not running in the kernel yet", cpuid);
1399 } else if (delays > 2000) {
1400 /*
1401 * We waited at least 20 seconds, bail ..
1402 */
1403 error = ETIMEDOUT;
1404 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1405 mach_cpucontext_free(cp, ctx, error);
1406 return (error);
1407 }
1408
1409 /*
1410 * wait at least 10ms, then check again..
1411 */
1412 delay(USEC_TO_TICK_ROUNDUP(10000));
1413 tempset = *((volatile cpuset_t *)&procset_slave);
1414 }
1415 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1416
1417 mach_cpucontext_free(cp, ctx, 0);
1418
1419 #ifndef __xpv
1420 if (tsc_gethrtime_enable)
1421 tsc_sync_master(cpuid);
1422 #endif
1423
1424 /*
1425 * At this point, the CPU in question is past the IDENT cpuid phase and
1426 * grabbed the current microcode revision so we can now look for any
1427 * relevant microcode updates it should load. We'll fill out
1428 * cpu_ucode_info for it along with the microcode to load, if any,
1429 * before signaling back to the CPU to continue startup.
1430 */
1431 mp_startup_wait(&procset_slave, cpuid);
1432 ucode_locate(cp);
1433 mp_startup_signal(&procset_master, cpuid);
1434
1435 if (dtrace_cpu_init != NULL) {
1436 (*dtrace_cpu_init)(cpuid);
1437 }
1438
1439 /*
1440 * During CPU DR operations, the cpu_lock is held by current
1441 * (the control) thread. We can't release the cpu_lock here
1442 * because that will break the CPU DR logic.
1443 * On the other hand, CPUPM and processor group initialization
1444 * routines need to access the cpu_lock. So we invoke those
1445 * routines here on behalf of mp_startup_common().
1446 *
1447 * CPUPM and processor group initialization routines depend
1448 * on the cpuid probing results. Wait for mp_startup_common()
1449 * to signal that cpuid probing is done.
1450 */
1451 mp_startup_wait(&procset_slave, cpuid);
1452 #ifndef __xpv
1453 cpupm_init(cp);
1454 #endif
1455 (void) pg_cpu_init(cp, B_FALSE);
1456 cpu_set_state(cp);
1457 mp_startup_signal(&procset_master, cpuid);
1458
1459 return (0);
1460 }
1461
1462 /*
1463 * Start a single cpu, assuming that the kernel context is available
1464 * to successfully start another cpu.
1465 *
1466 * (For example, real mode code is mapped into the right place
1467 * in memory and is ready to be run.)
1468 */
1469 int
start_cpu(processorid_t who)1470 start_cpu(processorid_t who)
1471 {
1472 cpu_t *cp;
1473 int error = 0;
1474 cpuset_t tempset;
1475
1476 ASSERT(who != 0);
1477
1478 /*
1479 * Check if there's at least a Mbyte of kmem available
1480 * before attempting to start the cpu.
1481 */
1482 if (kmem_avail() < 1024 * 1024) {
1483 /*
1484 * Kick off a reap in case that helps us with
1485 * later attempts ..
1486 */
1487 kmem_reap();
1488 return (ENOMEM);
1489 }
1490
1491 /*
1492 * First configure cpu.
1493 */
1494 cp = mp_cpu_configure_common(who, B_TRUE);
1495 ASSERT(cp != NULL);
1496
1497 /*
1498 * Then start cpu.
1499 */
1500 error = mp_start_cpu_common(cp, B_TRUE);
1501 if (error != 0) {
1502 mp_cpu_unconfigure_common(cp, error);
1503 return (error);
1504 }
1505
1506 mutex_exit(&cpu_lock);
1507 tempset = cpu_ready_set;
1508 while (!CPU_IN_SET(tempset, who)) {
1509 drv_usecwait(1);
1510 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1511 }
1512 mutex_enter(&cpu_lock);
1513
1514 return (0);
1515 }
1516
1517 void
start_other_cpus(int cprboot)1518 start_other_cpus(int cprboot)
1519 {
1520 _NOTE(ARGUNUSED(cprboot));
1521
1522 uint_t who;
1523 uint_t bootcpuid = 0;
1524
1525 /*
1526 * Initialize our own cpu_info.
1527 */
1528 init_cpu_info(CPU);
1529
1530 #if !defined(__xpv)
1531 init_cpu_id_gdt(CPU);
1532 #endif
1533
1534 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1535 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1536
1537 /*
1538 * KPTI initialisation happens very early in boot, before logging is
1539 * set up. Output a status message now as the boot CPU comes online.
1540 */
1541 cmn_err(CE_CONT, "?KPTI %s (PCID %s, INVPCID %s)\n",
1542 kpti_enable ? "enabled" : "disabled",
1543 x86_use_pcid == 1 ? "in use" :
1544 (is_x86_feature(x86_featureset, X86FSET_PCID) ? "disabled" :
1545 "not supported"),
1546 x86_use_pcid == 1 && x86_use_invpcid == 1 ? "in use" :
1547 (is_x86_feature(x86_featureset, X86FSET_INVPCID) ? "disabled" :
1548 "not supported"));
1549
1550 /*
1551 * Initialize our syscall handlers
1552 */
1553 init_cpu_syscall(CPU);
1554
1555 /*
1556 * Take the boot cpu out of the mp_cpus set because we know
1557 * it's already running. Add it to the cpu_ready_set for
1558 * precisely the same reason.
1559 */
1560 CPUSET_DEL(mp_cpus, bootcpuid);
1561 CPUSET_ADD(cpu_ready_set, bootcpuid);
1562
1563 /*
1564 * skip the rest of this if
1565 * . only 1 cpu dectected and system isn't hotplug-capable
1566 * . not using MP
1567 */
1568 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1569 use_mp == 0) {
1570 if (use_mp == 0)
1571 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1572 goto done;
1573 }
1574
1575 /*
1576 * perform such initialization as is needed
1577 * to be able to take CPUs on- and off-line.
1578 */
1579 cpu_pause_init();
1580
1581 xc_init_cpu(CPU); /* initialize processor crosscalls */
1582
1583 if (mach_cpucontext_init() != 0)
1584 goto done;
1585
1586 flushes_require_xcalls = 1;
1587
1588 /*
1589 * We lock our affinity to the master CPU to ensure that all slave CPUs
1590 * do their TSC syncs with the same CPU.
1591 */
1592 affinity_set(CPU_CURRENT);
1593
1594 for (who = 0; who < NCPU; who++) {
1595 if (!CPU_IN_SET(mp_cpus, who))
1596 continue;
1597 ASSERT(who != bootcpuid);
1598
1599 mutex_enter(&cpu_lock);
1600 if (start_cpu(who) != 0)
1601 CPUSET_DEL(mp_cpus, who);
1602 cpu_state_change_notify(who, CPU_SETUP);
1603 mutex_exit(&cpu_lock);
1604 }
1605
1606 /* Free the space allocated to hold the microcode file */
1607 ucode_cleanup();
1608
1609 affinity_clear();
1610
1611 mach_cpucontext_fini();
1612
1613 done:
1614 if (get_hwenv() == HW_NATIVE)
1615 workaround_errata_end();
1616 cmi_post_mpstartup();
1617
1618 #if !defined(__xpv)
1619 /*
1620 * Once other CPUs have completed startup procedures, perform
1621 * initialization of hypervisor resources for HMA.
1622 */
1623 hma_init();
1624 #endif
1625
1626 if (use_mp && ncpus != boot_max_ncpus) {
1627 cmn_err(CE_NOTE,
1628 "System detected %d cpus, but "
1629 "only %d cpu(s) were enabled during boot.",
1630 boot_max_ncpus, ncpus);
1631 cmn_err(CE_NOTE,
1632 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1633 "See eeprom(8).");
1634 }
1635 }
1636
1637 int
mp_cpu_configure(int cpuid)1638 mp_cpu_configure(int cpuid)
1639 {
1640 cpu_t *cp;
1641
1642 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1643 return (ENOTSUP);
1644 }
1645
1646 cp = cpu_get(cpuid);
1647 if (cp != NULL) {
1648 return (EALREADY);
1649 }
1650
1651 /*
1652 * Check if there's at least a Mbyte of kmem available
1653 * before attempting to start the cpu.
1654 */
1655 if (kmem_avail() < 1024 * 1024) {
1656 /*
1657 * Kick off a reap in case that helps us with
1658 * later attempts ..
1659 */
1660 kmem_reap();
1661 return (ENOMEM);
1662 }
1663
1664 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1665 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1666
1667 return (cp != NULL ? 0 : EAGAIN);
1668 }
1669
1670 int
mp_cpu_unconfigure(int cpuid)1671 mp_cpu_unconfigure(int cpuid)
1672 {
1673 cpu_t *cp;
1674
1675 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1676 return (ENOTSUP);
1677 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1678 return (EINVAL);
1679 }
1680
1681 cp = cpu_get(cpuid);
1682 if (cp == NULL) {
1683 return (ENODEV);
1684 }
1685 mp_cpu_unconfigure_common(cp, 0);
1686
1687 return (0);
1688 }
1689
1690 /*
1691 * Startup function for 'other' CPUs (besides boot cpu).
1692 * Called from real_mode_start.
1693 *
1694 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1695 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1696 * hat_unload which requires CPU_READY to be set.
1697 */
1698 static void
mp_startup_common(boolean_t boot)1699 mp_startup_common(boolean_t boot)
1700 {
1701 cpu_t *cp = CPU;
1702 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1703 extern void cpu_event_init_cpu(cpu_t *);
1704
1705 /*
1706 * We need to get TSC on this proc synced (i.e., any delta
1707 * from cpu0 accounted for) as soon as we can, because many
1708 * many things use gethrtime/pc_gethrestime, including
1709 * interrupts, cmn_err, etc. Before we can do that, we want to
1710 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1711 * right away. Note that the TSC sync procedure run by
1712 * tsc_sync_{master,slave} will not yield reliable results if caching is
1713 * disabled on either CPU. We rely on code in mpcore.S to guarantee
1714 * that it is enabled before this function is called. Caching has
1715 * already been enabled on the BSP long before APs are started.
1716 */
1717 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1718 cpuid_execpass(cp, CPUID_PASS_PRELUDE, new_x86_featureset);
1719 cpuid_execpass(cp, CPUID_PASS_IDENT, NULL);
1720
1721 /*
1722 * We want to apply any microcode updates before the BASIC cpuid pass,
1723 * but as per the above comment, we want to make sure TSC is synced
1724 * ASAP. Thus we check for TSC support in the boot CPU's feature set
1725 * instead -- this should be fine as we'd expect TSC support to be
1726 * consistent across all CPUs (and certainly for the buggy CPUs we're
1727 * concerned about here).
1728 */
1729 if (boot && get_hwenv() == HW_NATIVE &&
1730 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1731 cpuid_getfamily(CPU) == 6 &&
1732 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1733 is_x86_feature(x86_featureset, X86FSET_TSC)) {
1734 (void) wrmsr(REG_TSC, 0UL);
1735 }
1736
1737 /* Let the control CPU continue into tsc_sync_master() */
1738 mp_startup_signal(&procset_slave, cp->cpu_id);
1739
1740 #ifndef __xpv
1741 if (tsc_gethrtime_enable)
1742 tsc_sync_slave();
1743 #endif
1744
1745 /*
1746 * As with the boot CPU, we may have a more recent update compared to
1747 * whatever the BIOS may have already applied. If so, we want to apply
1748 * it here before the BASIC cpuid pass so that any architecturally
1749 * visible changes (e.g., changed MSR or CPUID bits) happen before we
1750 * start querying the CPU for its capabilities.
1751 *
1752 * Since we're still in the early stages of bringing up this CPU, we're
1753 * limited in what we can do (e.g., no kmem_alloc/free), so after
1754 * reading the current microcode revision we have the control CPU do the
1755 * work of locating the microcode file and setting up the cpu_ucode_info
1756 * structure via ucode_locate(). With that done, we can apply the
1757 * microcode to this CPU (if any) and proceed with the BASIC cpuid pass.
1758 */
1759 ucode_read_rev(cp);
1760 mp_startup_signal(&procset_slave, cp->cpu_id);
1761 mp_startup_wait(&procset_master, cp->cpu_id);
1762 ucode_apply(cp);
1763 cpuid_execpass(cp, CPUID_PASS_BASIC, new_x86_featureset);
1764
1765 /*
1766 * Once this was done from assembly, but it's safer here; if
1767 * it blocks, we need to be able to swtch() to and from, and
1768 * since we get here by calling t_pc, we need to do that call
1769 * before swtch() overwrites it.
1770 */
1771 (void) (*ap_mlsetup)();
1772
1773 #ifndef __xpv
1774 /*
1775 * Program this cpu's PAT
1776 */
1777 pat_sync();
1778 #endif
1779
1780 /*
1781 * Set up TSC_AUX to contain the cpuid for this processor
1782 * for the rdtscp instruction.
1783 */
1784 if (is_x86_feature(new_x86_featureset, X86FSET_TSCP))
1785 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1786
1787 /*
1788 * Initialize this CPU's syscall handlers
1789 */
1790 init_cpu_syscall(cp);
1791
1792 /*
1793 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1794 * highest level at which a routine is permitted to block on
1795 * an adaptive mutex (allows for cpu poke interrupt in case
1796 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1797 * device interrupts that may end up in the hat layer issuing cross
1798 * calls before CPU_READY is set.
1799 */
1800 splx(ipltospl(LOCK_LEVEL));
1801 sti();
1802
1803 /*
1804 * There exists a small subset of systems which expose differing
1805 * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from
1806 * the boot CPU, but is found on a later CPU, the system continues to
1807 * operate as if no MWAIT support is available.
1808 *
1809 * The reverse case, where MWAIT is available on the boot CPU but not
1810 * on a subsequently initialized CPU, is not presently allowed and will
1811 * result in a panic.
1812 */
1813 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1814 is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) {
1815 if (!is_x86_feature(x86_featureset, X86FSET_MWAIT)) {
1816 remove_x86_feature(new_x86_featureset, X86FSET_MWAIT);
1817 } else {
1818 panic("unsupported mixed cpu mwait support detected");
1819 }
1820 }
1821
1822 /*
1823 * We could be more sophisticated here, and just mark the CPU
1824 * as "faulted" but at this point we'll opt for the easier
1825 * answer of dying horribly. Provided the boot cpu is ok,
1826 * the system can be recovered by booting with use_mp set to zero.
1827 */
1828 if (workaround_errata(cp) != 0)
1829 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1830
1831 /*
1832 * We can touch cpu_flags here without acquiring the cpu_lock here
1833 * because the cpu_lock is held by the control CPU which is running
1834 * mp_start_cpu_common().
1835 * Need to clear CPU_QUIESCED flag before calling any function which
1836 * may cause thread context switching, such as kmem_alloc() etc.
1837 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1838 * it's set. So the startup thread may have no chance to switch back
1839 * again if it's switched away with CPU_QUIESCED set.
1840 */
1841 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1842
1843 enable_pcid();
1844
1845 /*
1846 * Setup this processor for XSAVE.
1847 */
1848 if (fp_save_mech == FP_XSAVE) {
1849 xsave_setup_msr(cp);
1850 }
1851
1852 cpuid_execpass(cp, CPUID_PASS_EXTENDED, NULL);
1853 cpuid_execpass(cp, CPUID_PASS_DYNAMIC, NULL);
1854 cpuid_execpass(cp, CPUID_PASS_RESOLVE, NULL);
1855
1856 /*
1857 * Correct cpu_idstr and cpu_brandstr on target CPU after
1858 * CPUID_PASS_DYNAMIC is done.
1859 */
1860 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1861 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1862
1863 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1864
1865 post_startup_cpu_fixups();
1866
1867 cpu_event_init_cpu(cp);
1868
1869 /*
1870 * Enable preemption here so that contention for any locks acquired
1871 * later in mp_startup_common may be preempted if the thread owning
1872 * those locks is continuously executing on other CPUs (for example,
1873 * this CPU must be preemptible to allow other CPUs to pause it during
1874 * their startup phases). It's safe to enable preemption here because
1875 * the CPU state is pretty-much fully constructed.
1876 */
1877 curthread->t_preempt = 0;
1878
1879 /* The base spl should still be at LOCK LEVEL here */
1880 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1881 set_base_spl(); /* Restore the spl to its proper value */
1882
1883 pghw_physid_create(cp);
1884 /*
1885 * Delegate initialization tasks, which need to access the cpu_lock,
1886 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1887 * during CPU DR operations.
1888 */
1889 mp_startup_signal(&procset_slave, cp->cpu_id);
1890 mp_startup_wait(&procset_master, cp->cpu_id);
1891 pg_cmt_cpu_startup(cp);
1892
1893 if (boot) {
1894 mutex_enter(&cpu_lock);
1895 cp->cpu_flags &= ~CPU_OFFLINE;
1896 cpu_enable_intr(cp);
1897 cpu_add_active(cp);
1898 mutex_exit(&cpu_lock);
1899 }
1900
1901 /* Enable interrupts */
1902 (void) spl0();
1903
1904 /*
1905 * Clear the microcode update buffer allocated via ucode_locate(), if
1906 * any, for this CPU.
1907 */
1908 ucode_finish(cp);
1909
1910 /*
1911 * Do a sanity check to make sure this new CPU is a sane thing
1912 * to add to the collection of processors running this system.
1913 *
1914 * XXX Clearly this needs to get more sophisticated, if x86
1915 * systems start to get built out of heterogenous CPUs; as is
1916 * likely to happen once the number of processors in a configuration
1917 * gets large enough.
1918 */
1919 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1920 B_FALSE) {
1921 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1922 print_x86_featureset(new_x86_featureset);
1923 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1924 }
1925
1926 #ifndef __xpv
1927 {
1928 /*
1929 * Set up the CPU module for this CPU. This can't be done
1930 * before this CPU is made CPU_READY, because we may (in
1931 * heterogeneous systems) need to go load another CPU module.
1932 * The act of attempting to load a module may trigger a
1933 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1934 */
1935 cmi_hdl_t hdl;
1936
1937 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1938 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1939 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1940 cmi_mca_init(hdl);
1941 cp->cpu_m.mcpu_cmi_hdl = hdl;
1942 }
1943 }
1944 #endif /* __xpv */
1945
1946 if (boothowto & RB_DEBUG)
1947 kdi_cpu_init();
1948
1949 (void) mach_cpu_create_device_node(cp, NULL);
1950
1951 /*
1952 * Setting the bit in cpu_ready_set must be the last operation in
1953 * processor initialization; the boot CPU will continue to boot once
1954 * it sees this bit set for all active CPUs.
1955 */
1956 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1957
1958 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1959 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1960 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1961 cp->cpu_id);
1962
1963 /*
1964 * Now we are done with the startup thread, so free it up.
1965 */
1966 thread_exit();
1967 /*NOTREACHED*/
1968 }
1969
1970 /*
1971 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1972 */
1973 static void
mp_startup_boot(void)1974 mp_startup_boot(void)
1975 {
1976 mp_startup_common(B_TRUE);
1977 }
1978
1979 /*
1980 * Startup function for hotplug CPUs at runtime.
1981 */
1982 void
mp_startup_hotplug(void)1983 mp_startup_hotplug(void)
1984 {
1985 mp_startup_common(B_FALSE);
1986 }
1987
1988 /*
1989 * Start CPU on user request.
1990 */
1991 /* ARGSUSED */
1992 int
mp_cpu_start(struct cpu * cp)1993 mp_cpu_start(struct cpu *cp)
1994 {
1995 ASSERT(MUTEX_HELD(&cpu_lock));
1996 return (0);
1997 }
1998
1999 /*
2000 * Stop CPU on user request.
2001 */
2002 int
mp_cpu_stop(struct cpu * cp)2003 mp_cpu_stop(struct cpu *cp)
2004 {
2005 extern int cbe_psm_timer_mode;
2006 ASSERT(MUTEX_HELD(&cpu_lock));
2007
2008 #ifdef __xpv
2009 /*
2010 * We can't offline vcpu0.
2011 */
2012 if (cp->cpu_id == 0)
2013 return (EBUSY);
2014 #endif
2015
2016 /*
2017 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
2018 * can't stop it. (This is true only for machines with no TSC.)
2019 */
2020
2021 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
2022 return (EBUSY);
2023
2024 return (0);
2025 }
2026
2027 /*
2028 * Take the specified CPU out of participation in interrupts.
2029 *
2030 * Usually, we hold cpu_lock. But we cannot assert as such due to the
2031 * exception - i_cpr_save_context() - where we have mutual exclusion via a
2032 * separate mechanism.
2033 */
2034 int
cpu_disable_intr(struct cpu * cp)2035 cpu_disable_intr(struct cpu *cp)
2036 {
2037 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
2038 return (EBUSY);
2039
2040 cp->cpu_flags &= ~CPU_ENABLE;
2041 ncpus_intr_enabled--;
2042 return (0);
2043 }
2044
2045 /*
2046 * Allow the specified CPU to participate in interrupts.
2047 */
2048 void
cpu_enable_intr(struct cpu * cp)2049 cpu_enable_intr(struct cpu *cp)
2050 {
2051 ASSERT(MUTEX_HELD(&cpu_lock));
2052 cp->cpu_flags |= CPU_ENABLE;
2053 ncpus_intr_enabled++;
2054 psm_enable_intr(cp->cpu_id);
2055 }
2056
2057 void
mp_cpu_faulted_enter(struct cpu * cp)2058 mp_cpu_faulted_enter(struct cpu *cp)
2059 {
2060 #ifdef __xpv
2061 _NOTE(ARGUNUSED(cp));
2062 #else
2063 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
2064
2065 if (hdl != NULL) {
2066 cmi_hdl_hold(hdl);
2067 } else {
2068 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2069 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2070 }
2071 if (hdl != NULL) {
2072 cmi_faulted_enter(hdl);
2073 cmi_hdl_rele(hdl);
2074 }
2075 #endif
2076 }
2077
2078 void
mp_cpu_faulted_exit(struct cpu * cp)2079 mp_cpu_faulted_exit(struct cpu *cp)
2080 {
2081 #ifdef __xpv
2082 _NOTE(ARGUNUSED(cp));
2083 #else
2084 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
2085
2086 if (hdl != NULL) {
2087 cmi_hdl_hold(hdl);
2088 } else {
2089 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2090 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2091 }
2092 if (hdl != NULL) {
2093 cmi_faulted_exit(hdl);
2094 cmi_hdl_rele(hdl);
2095 }
2096 #endif
2097 }
2098
2099 /*
2100 * The following two routines are used as context operators on threads belonging
2101 * to processes with a private LDT (see sysi86). Due to the rarity of such
2102 * processes, these routines are currently written for best code readability and
2103 * organization rather than speed. We could avoid checking x86_featureset at
2104 * every context switch by installing different context ops, depending on
2105 * x86_featureset, at LDT creation time -- one for each combination of fast
2106 * syscall features.
2107 */
2108
2109 void
cpu_fast_syscall_disable(void)2110 cpu_fast_syscall_disable(void)
2111 {
2112 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2113 is_x86_feature(x86_featureset, X86FSET_SEP))
2114 cpu_sep_disable();
2115 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2116 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2117 cpu_asysc_disable();
2118 }
2119
2120 void
cpu_fast_syscall_enable(void)2121 cpu_fast_syscall_enable(void)
2122 {
2123 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2124 is_x86_feature(x86_featureset, X86FSET_SEP))
2125 cpu_sep_enable();
2126 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2127 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2128 cpu_asysc_enable();
2129 }
2130
2131 static void
cpu_sep_enable(void)2132 cpu_sep_enable(void)
2133 {
2134 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2135 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2136
2137 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2138
2139 CPU->cpu_m.mcpu_fast_syscall_state |= FSS_SEP_ENABLED;
2140 }
2141
2142 static void
cpu_sep_disable(void)2143 cpu_sep_disable(void)
2144 {
2145 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2146 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2147
2148 /*
2149 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2150 * the sysenter or sysexit instruction to trigger a #gp fault.
2151 */
2152 wrmsr(MSR_INTC_SEP_CS, 0);
2153
2154 CPU->cpu_m.mcpu_fast_syscall_state &= ~FSS_SEP_ENABLED;
2155 }
2156
2157 static void
cpu_asysc_enable(void)2158 cpu_asysc_enable(void)
2159 {
2160 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2161 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2162
2163 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2164 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2165
2166 CPU->cpu_m.mcpu_fast_syscall_state |= FSS_ASYSC_ENABLED;
2167 }
2168
2169 static void
cpu_asysc_disable(void)2170 cpu_asysc_disable(void)
2171 {
2172 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2173 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2174
2175 /*
2176 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2177 * executing syscall or sysret with this bit off will incur a #ud trap.
2178 */
2179 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2180 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2181
2182 CPU->cpu_m.mcpu_fast_syscall_state &= ~FSS_ASYSC_ENABLED;
2183 }
2184