1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Digigram VXpocket soundcards
4 *
5 * lowlevel routines for VXpocket soundcards
6 *
7 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/firmware.h>
13 #include <linux/io.h>
14 #include <sound/core.h>
15 #include "vxpocket.h"
16
17
18 static const int vxp_reg_offset[VX_REG_MAX] = {
19 [VX_ICR] = 0x00, // ICR
20 [VX_CVR] = 0x01, // CVR
21 [VX_ISR] = 0x02, // ISR
22 [VX_IVR] = 0x03, // IVR
23 [VX_RXH] = 0x05, // RXH
24 [VX_RXM] = 0x06, // RXM
25 [VX_RXL] = 0x07, // RXL
26 [VX_DMA] = 0x04, // DMA
27 [VX_CDSP] = 0x08, // CDSP
28 [VX_LOFREQ] = 0x09, // LFREQ
29 [VX_HIFREQ] = 0x0a, // HFREQ
30 [VX_DATA] = 0x0b, // DATA
31 [VX_MICRO] = 0x0c, // MICRO
32 [VX_DIALOG] = 0x0d, // DIALOG
33 [VX_CSUER] = 0x0e, // CSUER
34 [VX_RUER] = 0x0f, // RUER
35 };
36
37
vxp_reg_addr(struct vx_core * _chip,int reg)38 static inline unsigned long vxp_reg_addr(struct vx_core *_chip, int reg)
39 {
40 struct snd_vxpocket *chip = to_vxpocket(_chip);
41 return chip->port + vxp_reg_offset[reg];
42 }
43
44 /*
45 * snd_vx_inb - read a byte from the register
46 * @offset: register offset
47 */
vxp_inb(struct vx_core * chip,int offset)48 static unsigned char vxp_inb(struct vx_core *chip, int offset)
49 {
50 return inb(vxp_reg_addr(chip, offset));
51 }
52
53 /*
54 * snd_vx_outb - write a byte on the register
55 * @offset: the register offset
56 * @val: the value to write
57 */
vxp_outb(struct vx_core * chip,int offset,unsigned char val)58 static void vxp_outb(struct vx_core *chip, int offset, unsigned char val)
59 {
60 outb(val, vxp_reg_addr(chip, offset));
61 }
62
63 /*
64 * redefine macros to call directly
65 */
66 #undef vx_inb
67 #define vx_inb(chip,reg) vxp_inb((struct vx_core *)(chip), VX_##reg)
68 #undef vx_outb
69 #define vx_outb(chip,reg,val) vxp_outb((struct vx_core *)(chip), VX_##reg,val)
70
71
72 /*
73 * vx_check_magic - check the magic word on xilinx
74 *
75 * returns zero if a magic word is detected, or a negative error code.
76 */
vx_check_magic(struct vx_core * chip)77 static int vx_check_magic(struct vx_core *chip)
78 {
79 unsigned long end_time = jiffies + HZ / 5;
80 int c;
81 do {
82 c = vx_inb(chip, CDSP);
83 if (c == CDSP_MAGIC)
84 return 0;
85 msleep(10);
86 } while (time_after_eq(end_time, jiffies));
87 dev_err(chip->card->dev, "cannot find xilinx magic word (%x)\n", c);
88 return -EIO;
89 }
90
91
92 /*
93 * vx_reset_dsp - reset the DSP
94 */
95
96 #define XX_DSP_RESET_WAIT_TIME 2 /* ms */
97
vxp_reset_dsp(struct vx_core * _chip)98 static void vxp_reset_dsp(struct vx_core *_chip)
99 {
100 struct snd_vxpocket *chip = to_vxpocket(_chip);
101
102 /* set the reset dsp bit to 1 */
103 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK);
104 vx_inb(chip, CDSP);
105 mdelay(XX_DSP_RESET_WAIT_TIME);
106 /* reset the bit */
107 chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK;
108 vx_outb(chip, CDSP, chip->regCDSP);
109 vx_inb(chip, CDSP);
110 mdelay(XX_DSP_RESET_WAIT_TIME);
111 }
112
113 /*
114 * reset codec bit
115 */
vxp_reset_codec(struct vx_core * _chip)116 static void vxp_reset_codec(struct vx_core *_chip)
117 {
118 struct snd_vxpocket *chip = to_vxpocket(_chip);
119
120 /* Set the reset CODEC bit to 1. */
121 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
122 vx_inb(chip, CDSP);
123 msleep(10);
124 /* Set the reset CODEC bit to 0. */
125 chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
126 vx_outb(chip, CDSP, chip->regCDSP);
127 vx_inb(chip, CDSP);
128 msleep(1);
129 }
130
131 /*
132 * vx_load_xilinx_binary - load the xilinx binary image
133 * the binary image is the binary array converted from the bitstream file.
134 */
vxp_load_xilinx_binary(struct vx_core * _chip,const struct firmware * fw)135 static int vxp_load_xilinx_binary(struct vx_core *_chip, const struct firmware *fw)
136 {
137 struct snd_vxpocket *chip = to_vxpocket(_chip);
138 unsigned int i;
139 int c;
140 int regCSUER, regRUER;
141 const unsigned char *image;
142 unsigned char data;
143
144 /* Switch to programmation mode */
145 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
146 vx_outb(chip, DIALOG, chip->regDIALOG);
147
148 /* Save register CSUER and RUER */
149 regCSUER = vx_inb(chip, CSUER);
150 regRUER = vx_inb(chip, RUER);
151
152 /* reset HF0 and HF1 */
153 vx_outb(chip, ICR, 0);
154
155 /* Wait for answer HF2 equal to 1 */
156 if (vx_check_isr(_chip, ISR_HF2, ISR_HF2, 20) < 0)
157 goto _error;
158
159 /* set HF1 for loading xilinx binary */
160 vx_outb(chip, ICR, ICR_HF1);
161 image = fw->data;
162 for (i = 0; i < fw->size; i++, image++) {
163 data = *image;
164 if (vx_wait_isr_bit(_chip, ISR_TX_EMPTY) < 0)
165 goto _error;
166 vx_outb(chip, TXL, data);
167 /* wait for reading */
168 if (vx_wait_for_rx_full(_chip) < 0)
169 goto _error;
170 c = vx_inb(chip, RXL);
171 if (c != (int)data)
172 dev_err(_chip->card->dev,
173 "vxpocket: load xilinx mismatch at %d: 0x%x != 0x%x\n",
174 i, c, (int)data);
175 }
176
177 /* reset HF1 */
178 vx_outb(chip, ICR, 0);
179
180 /* wait for HF3 */
181 if (vx_check_isr(_chip, ISR_HF3, ISR_HF3, 20) < 0)
182 goto _error;
183
184 /* read the number of bytes received */
185 if (vx_wait_for_rx_full(_chip) < 0)
186 goto _error;
187
188 c = (int)vx_inb(chip, RXH) << 16;
189 c |= (int)vx_inb(chip, RXM) << 8;
190 c |= vx_inb(chip, RXL);
191
192 dev_dbg(_chip->card->dev,
193 "xilinx: dsp size received 0x%x, orig 0x%zx\n", c, fw->size);
194
195 vx_outb(chip, ICR, ICR_HF0);
196
197 /* TEMPO 250ms : wait until Xilinx is downloaded */
198 msleep(300);
199
200 /* test magical word */
201 if (vx_check_magic(_chip) < 0)
202 goto _error;
203
204 /* Restore register 0x0E and 0x0F (thus replacing COR and FCSR) */
205 vx_outb(chip, CSUER, regCSUER);
206 vx_outb(chip, RUER, regRUER);
207
208 /* Reset the Xilinx's signal enabling IO access */
209 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
210 vx_outb(chip, DIALOG, chip->regDIALOG);
211 vx_inb(chip, DIALOG);
212 msleep(10);
213 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
214 vx_outb(chip, DIALOG, chip->regDIALOG);
215 vx_inb(chip, DIALOG);
216
217 /* Reset of the Codec */
218 vxp_reset_codec(_chip);
219 vx_reset_dsp(_chip);
220
221 return 0;
222
223 _error:
224 vx_outb(chip, CSUER, regCSUER);
225 vx_outb(chip, RUER, regRUER);
226 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
227 vx_outb(chip, DIALOG, chip->regDIALOG);
228 return -EIO;
229 }
230
231
232 /*
233 * vxp_load_dsp - load_dsp callback
234 */
vxp_load_dsp(struct vx_core * vx,int index,const struct firmware * fw)235 static int vxp_load_dsp(struct vx_core *vx, int index, const struct firmware *fw)
236 {
237 int err;
238
239 switch (index) {
240 case 0:
241 /* xilinx boot */
242 err = vx_check_magic(vx);
243 if (err < 0)
244 return err;
245 err = snd_vx_load_boot_image(vx, fw);
246 if (err < 0)
247 return err;
248 return 0;
249 case 1:
250 /* xilinx image */
251 return vxp_load_xilinx_binary(vx, fw);
252 case 2:
253 /* DSP boot */
254 return snd_vx_dsp_boot(vx, fw);
255 case 3:
256 /* DSP image */
257 return snd_vx_dsp_load(vx, fw);
258 default:
259 snd_BUG();
260 return -EINVAL;
261 }
262 }
263
264
265 /*
266 * vx_test_and_ack - test and acknowledge interrupt
267 *
268 * called from irq hander, too
269 *
270 * spinlock held!
271 */
vxp_test_and_ack(struct vx_core * _chip)272 static int vxp_test_and_ack(struct vx_core *_chip)
273 {
274 struct snd_vxpocket *chip = to_vxpocket(_chip);
275
276 /* not booted yet? */
277 if (! (_chip->chip_status & VX_STAT_XILINX_LOADED))
278 return -ENXIO;
279
280 if (! (vx_inb(chip, DIALOG) & VXP_DLG_MEMIRQ_MASK))
281 return -EIO;
282
283 /* ok, interrupts generated, now ack it */
284 /* set ACQUIT bit up and down */
285 vx_outb(chip, DIALOG, chip->regDIALOG | VXP_DLG_ACK_MEMIRQ_MASK);
286 /* useless read just to spend some time and maintain
287 * the ACQUIT signal up for a while ( a bus cycle )
288 */
289 vx_inb(chip, DIALOG);
290 vx_outb(chip, DIALOG, chip->regDIALOG & ~VXP_DLG_ACK_MEMIRQ_MASK);
291
292 return 0;
293 }
294
295
296 /*
297 * vx_validate_irq - enable/disable IRQ
298 */
vxp_validate_irq(struct vx_core * _chip,int enable)299 static void vxp_validate_irq(struct vx_core *_chip, int enable)
300 {
301 struct snd_vxpocket *chip = to_vxpocket(_chip);
302
303 /* Set the interrupt enable bit to 1 in CDSP register */
304 if (enable)
305 chip->regCDSP |= VXP_CDSP_VALID_IRQ_MASK;
306 else
307 chip->regCDSP &= ~VXP_CDSP_VALID_IRQ_MASK;
308 vx_outb(chip, CDSP, chip->regCDSP);
309 }
310
311 /*
312 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
313 * @do_write: 0 = read, 1 = set up for DMA write
314 */
vx_setup_pseudo_dma(struct vx_core * _chip,int do_write)315 static void vx_setup_pseudo_dma(struct vx_core *_chip, int do_write)
316 {
317 struct snd_vxpocket *chip = to_vxpocket(_chip);
318
319 /* Interrupt mode and HREQ pin enabled for host transmit / receive data transfers */
320 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
321 /* Reset the pseudo-dma register */
322 vx_inb(chip, ISR);
323 vx_outb(chip, ISR, 0);
324
325 /* Select DMA in read/write transfer mode and in 16-bit accesses */
326 chip->regDIALOG |= VXP_DLG_DMA16_SEL_MASK;
327 chip->regDIALOG |= do_write ? VXP_DLG_DMAWRITE_SEL_MASK : VXP_DLG_DMAREAD_SEL_MASK;
328 vx_outb(chip, DIALOG, chip->regDIALOG);
329
330 }
331
332 /*
333 * vx_release_pseudo_dma - disable the pseudo-DMA mode
334 */
vx_release_pseudo_dma(struct vx_core * _chip)335 static void vx_release_pseudo_dma(struct vx_core *_chip)
336 {
337 struct snd_vxpocket *chip = to_vxpocket(_chip);
338
339 /* Disable DMA and 16-bit accesses */
340 chip->regDIALOG &= ~(VXP_DLG_DMAWRITE_SEL_MASK|
341 VXP_DLG_DMAREAD_SEL_MASK|
342 VXP_DLG_DMA16_SEL_MASK);
343 vx_outb(chip, DIALOG, chip->regDIALOG);
344 /* HREQ pin disabled. */
345 vx_outb(chip, ICR, 0);
346 }
347
348 /*
349 * vx_pseudo_dma_write - write bulk data on pseudo-DMA mode
350 * @count: data length to transfer in bytes
351 *
352 * data size must be aligned to 6 bytes to ensure the 24bit alignment on DSP.
353 * NB: call with a certain lock!
354 */
vxp_dma_write(struct vx_core * chip,struct snd_pcm_runtime * runtime,struct vx_pipe * pipe,int count)355 static void vxp_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
356 struct vx_pipe *pipe, int count)
357 {
358 long port = vxp_reg_addr(chip, VX_DMA);
359 int offset = pipe->hw_ptr;
360 unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
361
362 vx_setup_pseudo_dma(chip, 1);
363 if (offset + count >= pipe->buffer_bytes) {
364 int length = pipe->buffer_bytes - offset;
365 count -= length;
366 length >>= 1; /* in 16bit words */
367 /* Transfer using pseudo-dma. */
368 for (; length > 0; length--) {
369 outw(*addr, port);
370 addr++;
371 }
372 addr = (unsigned short *)runtime->dma_area;
373 pipe->hw_ptr = 0;
374 }
375 pipe->hw_ptr += count;
376 count >>= 1; /* in 16bit words */
377 /* Transfer using pseudo-dma. */
378 for (; count > 0; count--) {
379 outw(*addr, port);
380 addr++;
381 }
382 vx_release_pseudo_dma(chip);
383 }
384
385
386 /*
387 * vx_pseudo_dma_read - read bulk data on pseudo DMA mode
388 * @offset: buffer offset in bytes
389 * @count: data length to transfer in bytes
390 *
391 * the read length must be aligned to 6 bytes, as well as write.
392 * NB: call with a certain lock!
393 */
vxp_dma_read(struct vx_core * chip,struct snd_pcm_runtime * runtime,struct vx_pipe * pipe,int count)394 static void vxp_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
395 struct vx_pipe *pipe, int count)
396 {
397 struct snd_vxpocket *pchip = to_vxpocket(chip);
398 long port = vxp_reg_addr(chip, VX_DMA);
399 int offset = pipe->hw_ptr;
400 unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
401
402 if (snd_BUG_ON(count % 2))
403 return;
404 vx_setup_pseudo_dma(chip, 0);
405 if (offset + count >= pipe->buffer_bytes) {
406 int length = pipe->buffer_bytes - offset;
407 count -= length;
408 length >>= 1; /* in 16bit words */
409 /* Transfer using pseudo-dma. */
410 for (; length > 0; length--)
411 *addr++ = inw(port);
412 addr = (unsigned short *)runtime->dma_area;
413 pipe->hw_ptr = 0;
414 }
415 pipe->hw_ptr += count;
416 count >>= 1; /* in 16bit words */
417 /* Transfer using pseudo-dma. */
418 for (; count > 1; count--)
419 *addr++ = inw(port);
420 /* Disable DMA */
421 pchip->regDIALOG &= ~VXP_DLG_DMAREAD_SEL_MASK;
422 vx_outb(chip, DIALOG, pchip->regDIALOG);
423 /* Read the last word (16 bits) */
424 *addr = inw(port);
425 /* Disable 16-bit accesses */
426 pchip->regDIALOG &= ~VXP_DLG_DMA16_SEL_MASK;
427 vx_outb(chip, DIALOG, pchip->regDIALOG);
428 /* HREQ pin disabled. */
429 vx_outb(chip, ICR, 0);
430 }
431
432
433 /*
434 * write a codec data (24bit)
435 */
vxp_write_codec_reg(struct vx_core * chip,int codec,unsigned int data)436 static void vxp_write_codec_reg(struct vx_core *chip, int codec, unsigned int data)
437 {
438 int i;
439
440 /* Activate access to the corresponding codec register */
441 if (! codec)
442 vx_inb(chip, LOFREQ);
443 else
444 vx_inb(chip, CODEC2);
445
446 /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
447 for (i = 0; i < 24; i++, data <<= 1)
448 vx_outb(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
449
450 /* Terminate access to codec registers */
451 vx_inb(chip, HIFREQ);
452 }
453
454
455 /*
456 * vx_set_mic_boost - set mic boost level (on vxp440 only)
457 * @boost: 0 = 20dB, 1 = +38dB
458 */
vx_set_mic_boost(struct vx_core * chip,int boost)459 void vx_set_mic_boost(struct vx_core *chip, int boost)
460 {
461 struct snd_vxpocket *pchip = to_vxpocket(chip);
462
463 if (chip->chip_status & VX_STAT_IS_STALE)
464 return;
465
466 mutex_lock(&chip->lock);
467 if (pchip->regCDSP & P24_CDSP_MICS_SEL_MASK) {
468 if (boost) {
469 /* boost: 38 dB */
470 pchip->regCDSP &= ~P24_CDSP_MIC20_SEL_MASK;
471 pchip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
472 } else {
473 /* minimum value: 20 dB */
474 pchip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
475 pchip->regCDSP &= ~P24_CDSP_MIC38_SEL_MASK;
476 }
477 vx_outb(chip, CDSP, pchip->regCDSP);
478 }
479 mutex_unlock(&chip->lock);
480 }
481
482 /*
483 * remap the linear value (0-8) to the actual value (0-15)
484 */
vx_compute_mic_level(int level)485 static int vx_compute_mic_level(int level)
486 {
487 switch (level) {
488 case 5: level = 6 ; break;
489 case 6: level = 8 ; break;
490 case 7: level = 11; break;
491 case 8: level = 15; break;
492 default: break ;
493 }
494 return level;
495 }
496
497 /*
498 * vx_set_mic_level - set mic level (on vxpocket only)
499 * @level: the mic level = 0 - 8 (max)
500 */
vx_set_mic_level(struct vx_core * chip,int level)501 void vx_set_mic_level(struct vx_core *chip, int level)
502 {
503 struct snd_vxpocket *pchip = to_vxpocket(chip);
504
505 if (chip->chip_status & VX_STAT_IS_STALE)
506 return;
507
508 mutex_lock(&chip->lock);
509 if (pchip->regCDSP & VXP_CDSP_MIC_SEL_MASK) {
510 level = vx_compute_mic_level(level);
511 vx_outb(chip, MICRO, level);
512 }
513 mutex_unlock(&chip->lock);
514 }
515
516
517 /*
518 * change the input audio source
519 */
vxp_change_audio_source(struct vx_core * _chip,int src)520 static void vxp_change_audio_source(struct vx_core *_chip, int src)
521 {
522 struct snd_vxpocket *chip = to_vxpocket(_chip);
523
524 switch (src) {
525 case VX_AUDIO_SRC_DIGITAL:
526 chip->regCDSP |= VXP_CDSP_DATAIN_SEL_MASK;
527 vx_outb(chip, CDSP, chip->regCDSP);
528 break;
529 case VX_AUDIO_SRC_LINE:
530 chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
531 if (_chip->type == VX_TYPE_VXP440)
532 chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
533 else
534 chip->regCDSP &= ~VXP_CDSP_MIC_SEL_MASK;
535 vx_outb(chip, CDSP, chip->regCDSP);
536 break;
537 case VX_AUDIO_SRC_MIC:
538 chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
539 /* reset mic levels */
540 if (_chip->type == VX_TYPE_VXP440) {
541 chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
542 if (chip->mic_level)
543 chip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
544 else
545 chip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
546 vx_outb(chip, CDSP, chip->regCDSP);
547 } else {
548 chip->regCDSP |= VXP_CDSP_MIC_SEL_MASK;
549 vx_outb(chip, CDSP, chip->regCDSP);
550 vx_outb(chip, MICRO, vx_compute_mic_level(chip->mic_level));
551 }
552 break;
553 }
554 }
555
556 /*
557 * change the clock source
558 * source = INTERNAL_QUARTZ or UER_SYNC
559 */
vxp_set_clock_source(struct vx_core * _chip,int source)560 static void vxp_set_clock_source(struct vx_core *_chip, int source)
561 {
562 struct snd_vxpocket *chip = to_vxpocket(_chip);
563
564 if (source == INTERNAL_QUARTZ)
565 chip->regCDSP &= ~VXP_CDSP_CLOCKIN_SEL_MASK;
566 else
567 chip->regCDSP |= VXP_CDSP_CLOCKIN_SEL_MASK;
568 vx_outb(chip, CDSP, chip->regCDSP);
569 }
570
571
572 /*
573 * reset the board
574 */
vxp_reset_board(struct vx_core * _chip,int cold_reset)575 static void vxp_reset_board(struct vx_core *_chip, int cold_reset)
576 {
577 struct snd_vxpocket *chip = to_vxpocket(_chip);
578
579 chip->regCDSP = 0;
580 chip->regDIALOG = 0;
581 }
582
583
584 /*
585 * callbacks
586 */
587 /* exported */
588 const struct snd_vx_ops snd_vxpocket_ops = {
589 .in8 = vxp_inb,
590 .out8 = vxp_outb,
591 .test_and_ack = vxp_test_and_ack,
592 .validate_irq = vxp_validate_irq,
593 .write_codec = vxp_write_codec_reg,
594 .reset_codec = vxp_reset_codec,
595 .change_audio_source = vxp_change_audio_source,
596 .set_clock_source = vxp_set_clock_source,
597 .load_dsp = vxp_load_dsp,
598 .add_controls = vxp_add_mic_controls,
599 .reset_dsp = vxp_reset_dsp,
600 .reset_board = vxp_reset_board,
601 .dma_write = vxp_dma_write,
602 .dma_read = vxp_dma_read,
603 };
604