1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include <drm/display/drm_dp.h>
40
41 #include "i915_drv.h"
42 #include "i915_reg.h"
43 #include "gvt.h"
44 #include "i915_pvinfo.h"
45 #include "intel_mchbar_regs.h"
46 #include "display/bxt_dpio_phy_regs.h"
47 #include "display/i9xx_plane_regs.h"
48 #include "display/intel_crt_regs.h"
49 #include "display/intel_cursor_regs.h"
50 #include "display/intel_display_types.h"
51 #include "display/intel_dmc_regs.h"
52 #include "display/intel_dp_aux_regs.h"
53 #include "display/intel_dpio_phy.h"
54 #include "display/intel_fbc.h"
55 #include "display/intel_fdi_regs.h"
56 #include "display/intel_pps_regs.h"
57 #include "display/intel_psr_regs.h"
58 #include "display/intel_sprite_regs.h"
59 #include "display/skl_universal_plane_regs.h"
60 #include "display/skl_watermark_regs.h"
61 #include "display/vlv_dsi_pll_regs.h"
62 #include "gt/intel_gt_regs.h"
63 #include <linux/vmalloc.h>
64
65 /* XXX FIXME i915 has changed PP_XXX definition */
66 #define PCH_PP_STATUS _MMIO(0xc7200)
67 #define PCH_PP_CONTROL _MMIO(0xc7204)
68 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
69 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
70 #define PCH_PP_DIVISOR _MMIO(0xc7210)
71
intel_gvt_get_device_type(struct intel_gvt * gvt)72 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
73 {
74 struct drm_i915_private *i915 = gvt->gt->i915;
75
76 if (IS_BROADWELL(i915))
77 return D_BDW;
78 else if (IS_SKYLAKE(i915))
79 return D_SKL;
80 else if (IS_KABYLAKE(i915))
81 return D_KBL;
82 else if (IS_BROXTON(i915))
83 return D_BXT;
84 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
85 return D_CFL;
86
87 return 0;
88 }
89
intel_gvt_match_device(struct intel_gvt * gvt,unsigned long device)90 static bool intel_gvt_match_device(struct intel_gvt *gvt,
91 unsigned long device)
92 {
93 return intel_gvt_get_device_type(gvt) & device;
94 }
95
read_vreg(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)96 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
97 void *p_data, unsigned int bytes)
98 {
99 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
100 }
101
write_vreg(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)102 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
103 void *p_data, unsigned int bytes)
104 {
105 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
106 }
107
intel_gvt_find_mmio_info(struct intel_gvt * gvt,unsigned int offset)108 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
109 unsigned int offset)
110 {
111 struct intel_gvt_mmio_info *e;
112
113 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
114 if (e->offset == offset)
115 return e;
116 }
117 return NULL;
118 }
119
setup_mmio_info(struct intel_gvt * gvt,u32 offset,u32 size,u16 flags,u32 addr_mask,u32 ro_mask,u32 device,gvt_mmio_func read,gvt_mmio_func write)120 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
121 u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
122 gvt_mmio_func read, gvt_mmio_func write)
123 {
124 struct intel_gvt_mmio_info *p;
125 u32 start, end, i;
126
127 if (!intel_gvt_match_device(gvt, device))
128 return 0;
129
130 if (WARN_ON(!IS_ALIGNED(offset, 4)))
131 return -EINVAL;
132
133 start = offset;
134 end = offset + size;
135
136 for (i = start; i < end; i += 4) {
137 p = intel_gvt_find_mmio_info(gvt, i);
138 if (!p) {
139 WARN(1, "assign a handler to a non-tracked mmio %x\n",
140 i);
141 return -ENODEV;
142 }
143 p->ro_mask = ro_mask;
144 gvt->mmio.mmio_attribute[i / 4] = flags;
145 if (read)
146 p->read = read;
147 if (write)
148 p->write = write;
149 }
150 return 0;
151 }
152
153 /**
154 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
155 * @gvt: a GVT device
156 * @offset: register offset
157 *
158 * Returns:
159 * The engine containing the offset within its mmio page.
160 */
161 const struct intel_engine_cs *
intel_gvt_render_mmio_to_engine(struct intel_gvt * gvt,unsigned int offset)162 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
163 {
164 struct intel_engine_cs *engine;
165 enum intel_engine_id id;
166
167 offset &= ~GENMASK(11, 0);
168 for_each_engine(engine, gvt->gt, id)
169 if (engine->mmio_base == offset)
170 return engine;
171
172 return NULL;
173 }
174
175 #define offset_to_fence_num(offset) \
176 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
177
178 #define fence_num_to_offset(num) \
179 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
180
181
enter_failsafe_mode(struct intel_vgpu * vgpu,int reason)182 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
183 {
184 switch (reason) {
185 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
186 pr_err("Detected your guest driver doesn't support GVT-g.\n");
187 break;
188 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
189 pr_err("Graphics resource is not enough for the guest\n");
190 break;
191 case GVT_FAILSAFE_GUEST_ERR:
192 pr_err("GVT Internal error for the guest\n");
193 break;
194 default:
195 break;
196 }
197 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
198 vgpu->failsafe = true;
199 }
200
sanitize_fence_mmio_access(struct intel_vgpu * vgpu,unsigned int fence_num,void * p_data,unsigned int bytes)201 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
202 unsigned int fence_num, void *p_data, unsigned int bytes)
203 {
204 unsigned int max_fence = vgpu_fence_sz(vgpu);
205
206 if (fence_num >= max_fence) {
207 gvt_vgpu_err("access oob fence reg %d/%d\n",
208 fence_num, max_fence);
209
210 /* When guest access oob fence regs without access
211 * pv_info first, we treat guest not supporting GVT,
212 * and we will let vgpu enter failsafe mode.
213 */
214 if (!vgpu->pv_notified)
215 enter_failsafe_mode(vgpu,
216 GVT_FAILSAFE_UNSUPPORTED_GUEST);
217
218 memset(p_data, 0, bytes);
219 return -EINVAL;
220 }
221 return 0;
222 }
223
gamw_echo_dev_rw_ia_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)224 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
225 unsigned int offset, void *p_data, unsigned int bytes)
226 {
227 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
228
229 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) {
230 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
231 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
232 else if (!ips)
233 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
234 else {
235 /* All engines must be enabled together for vGPU,
236 * since we don't know which engine the ppgtt will
237 * bind to when shadowing.
238 */
239 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
240 ips);
241 return -EINVAL;
242 }
243 }
244
245 write_vreg(vgpu, offset, p_data, bytes);
246 return 0;
247 }
248
fence_mmio_read(struct intel_vgpu * vgpu,unsigned int off,void * p_data,unsigned int bytes)249 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
250 void *p_data, unsigned int bytes)
251 {
252 int ret;
253
254 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
255 p_data, bytes);
256 if (ret)
257 return ret;
258 read_vreg(vgpu, off, p_data, bytes);
259 return 0;
260 }
261
fence_mmio_write(struct intel_vgpu * vgpu,unsigned int off,void * p_data,unsigned int bytes)262 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
263 void *p_data, unsigned int bytes)
264 {
265 struct intel_gvt *gvt = vgpu->gvt;
266 unsigned int fence_num = offset_to_fence_num(off);
267 int ret;
268
269 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
270 if (ret)
271 return ret;
272 write_vreg(vgpu, off, p_data, bytes);
273
274 mmio_hw_access_pre(gvt->gt);
275 intel_vgpu_write_fence(vgpu, fence_num,
276 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
277 mmio_hw_access_post(gvt->gt);
278 return 0;
279 }
280
281 #define CALC_MODE_MASK_REG(old, new) \
282 (((new) & GENMASK(31, 16)) \
283 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
284 | ((new) & ((new) >> 16))))
285
mul_force_wake_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)286 static int mul_force_wake_write(struct intel_vgpu *vgpu,
287 unsigned int offset, void *p_data, unsigned int bytes)
288 {
289 u32 old, new;
290 u32 ack_reg_offset;
291
292 old = vgpu_vreg(vgpu, offset);
293 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
294
295 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) {
296 switch (offset) {
297 case FORCEWAKE_RENDER_GEN9_REG:
298 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
299 break;
300 case FORCEWAKE_GT_GEN9_REG:
301 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
302 break;
303 case FORCEWAKE_MEDIA_GEN9_REG:
304 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
305 break;
306 default:
307 /*should not hit here*/
308 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
309 return -EINVAL;
310 }
311 } else {
312 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
313 }
314
315 vgpu_vreg(vgpu, offset) = new;
316 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
317 return 0;
318 }
319
gdrst_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)320 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
321 void *p_data, unsigned int bytes)
322 {
323 intel_engine_mask_t engine_mask = 0;
324 u32 data;
325
326 write_vreg(vgpu, offset, p_data, bytes);
327 data = vgpu_vreg(vgpu, offset);
328
329 if (data & GEN6_GRDOM_FULL) {
330 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
331 engine_mask = ALL_ENGINES;
332 } else {
333 if (data & GEN6_GRDOM_RENDER) {
334 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
335 engine_mask |= BIT(RCS0);
336 }
337 if (data & GEN6_GRDOM_MEDIA) {
338 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
339 engine_mask |= BIT(VCS0);
340 }
341 if (data & GEN6_GRDOM_BLT) {
342 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
343 engine_mask |= BIT(BCS0);
344 }
345 if (data & GEN6_GRDOM_VECS) {
346 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
347 engine_mask |= BIT(VECS0);
348 }
349 if (data & GEN8_GRDOM_MEDIA2) {
350 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
351 engine_mask |= BIT(VCS1);
352 }
353 if (data & GEN9_GRDOM_GUC) {
354 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
355 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
356 }
357 engine_mask &= vgpu->gvt->gt->info.engine_mask;
358 }
359
360 /* vgpu_lock already hold by emulate mmio r/w */
361 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
362
363 /* sw will wait for the device to ack the reset request */
364 vgpu_vreg(vgpu, offset) = 0;
365
366 return 0;
367 }
368
gmbus_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)369 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
370 void *p_data, unsigned int bytes)
371 {
372 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
373 }
374
gmbus_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)375 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
376 void *p_data, unsigned int bytes)
377 {
378 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
379 }
380
pch_pp_control_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)381 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
382 unsigned int offset, void *p_data, unsigned int bytes)
383 {
384 write_vreg(vgpu, offset, p_data, bytes);
385
386 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
388 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
389 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
391
392 } else
393 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
394 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
395 | PP_CYCLE_DELAY_ACTIVE);
396 return 0;
397 }
398
transconf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)399 static int transconf_mmio_write(struct intel_vgpu *vgpu,
400 unsigned int offset, void *p_data, unsigned int bytes)
401 {
402 write_vreg(vgpu, offset, p_data, bytes);
403
404 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
405 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
406 else
407 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
408 return 0;
409 }
410
lcpll_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)411 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
412 void *p_data, unsigned int bytes)
413 {
414 write_vreg(vgpu, offset, p_data, bytes);
415
416 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
417 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
418 else
419 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
420
421 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
422 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
423 else
424 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
425
426 return 0;
427 }
428
dpy_reg_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)429 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
430 void *p_data, unsigned int bytes)
431 {
432 switch (offset) {
433 case 0xe651c:
434 case 0xe661c:
435 case 0xe671c:
436 case 0xe681c:
437 vgpu_vreg(vgpu, offset) = 1 << 17;
438 break;
439 case 0xe6c04:
440 vgpu_vreg(vgpu, offset) = 0x3;
441 break;
442 case 0xe6e1c:
443 vgpu_vreg(vgpu, offset) = 0x2f << 16;
444 break;
445 default:
446 return -EINVAL;
447 }
448
449 read_vreg(vgpu, offset, p_data, bytes);
450 return 0;
451 }
452
453 /*
454 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to
455 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on
456 * setup_virtual_dp_monitor().
457 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled
458 * DPLL. Later guest driver may setup a different DPLLx when setting mode.
459 * So the correct sequence to find DP stream clock is:
460 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x.
461 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate.
462 * Then Refresh rate then can be calculated based on follow equations:
463 * Pixel clock = h_total * v_total * refresh_rate
464 * stream clock = Pixel clock
465 * ls_clk = DP bitrate
466 * Link M/N = strm_clk / ls_clk
467 */
468
bdw_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)469 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
470 {
471 u32 dp_br = 0;
472 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));
473
474 switch (ddi_pll_sel) {
475 case PORT_CLK_SEL_LCPLL_2700:
476 dp_br = 270000 * 2;
477 break;
478 case PORT_CLK_SEL_LCPLL_1350:
479 dp_br = 135000 * 2;
480 break;
481 case PORT_CLK_SEL_LCPLL_810:
482 dp_br = 81000 * 2;
483 break;
484 case PORT_CLK_SEL_SPLL:
485 {
486 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {
487 case SPLL_FREQ_810MHz:
488 dp_br = 81000 * 2;
489 break;
490 case SPLL_FREQ_1350MHz:
491 dp_br = 135000 * 2;
492 break;
493 case SPLL_FREQ_2700MHz:
494 dp_br = 270000 * 2;
495 break;
496 default:
497 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n",
498 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));
499 break;
500 }
501 break;
502 }
503 case PORT_CLK_SEL_WRPLL1:
504 case PORT_CLK_SEL_WRPLL2:
505 {
506 u32 wrpll_ctl;
507 int refclk, n, p, r;
508
509 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1)
510 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));
511 else
512 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));
513
514 switch (wrpll_ctl & WRPLL_REF_MASK) {
515 case WRPLL_REF_PCH_SSC:
516 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc;
517 break;
518 case WRPLL_REF_LCPLL:
519 refclk = 2700000;
520 break;
521 default:
522 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n",
523 vgpu->id, port_name(port), wrpll_ctl);
524 goto out;
525 }
526
527 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK;
528 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
529 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
530
531 dp_br = (refclk * n / 10) / (p * r) * 2;
532 break;
533 }
534 default:
535 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
536 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));
537 break;
538 }
539
540 out:
541 return dp_br;
542 }
543
bxt_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)544 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
545 {
546 u32 dp_br = 0;
547 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
548 enum dpio_phy phy = DPIO_PHY0;
549 enum dpio_channel ch = DPIO_CH0;
550 struct dpll clock = {};
551 u32 temp;
552
553 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */
554 switch (port) {
555 case PORT_A:
556 phy = DPIO_PHY1;
557 ch = DPIO_CH0;
558 break;
559 case PORT_B:
560 phy = DPIO_PHY0;
561 ch = DPIO_CH0;
562 break;
563 case PORT_C:
564 phy = DPIO_PHY0;
565 ch = DPIO_CH1;
566 break;
567 default:
568 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port));
569 goto out;
570 }
571
572 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));
573 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) {
574 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n",
575 vgpu->id, port_name(port), temp);
576 goto out;
577 }
578
579 clock.m1 = 2;
580 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
581 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
582 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
583 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
584 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
585 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,
586 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
587 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,
588 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
589 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,
590 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
591 clock.m = clock.m1 * clock.m2;
592 clock.p = clock.p1 * clock.p2 * 5;
593
594 if (clock.n == 0 || clock.p == 0) {
595 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
596 goto out;
597 }
598
599 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
600 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
601
602 dp_br = clock.dot;
603
604 out:
605 return dp_br;
606 }
607
skl_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)608 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
609 {
610 u32 dp_br = 0;
611 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0;
612
613 /* Find the enabled DPLL for the DDI/PORT */
614 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&
615 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {
616 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &
617 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
618 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
619 } else {
620 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n",
621 vgpu->id, port_name(port));
622 return dp_br;
623 }
624
625 /* Find PLL output frequency from correct DPLL, and get bir rate */
626 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &
627 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >>
628 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) {
629 case DPLL_CTRL1_LINK_RATE_810:
630 dp_br = 81000 * 2;
631 break;
632 case DPLL_CTRL1_LINK_RATE_1080:
633 dp_br = 108000 * 2;
634 break;
635 case DPLL_CTRL1_LINK_RATE_1350:
636 dp_br = 135000 * 2;
637 break;
638 case DPLL_CTRL1_LINK_RATE_1620:
639 dp_br = 162000 * 2;
640 break;
641 case DPLL_CTRL1_LINK_RATE_2160:
642 dp_br = 216000 * 2;
643 break;
644 case DPLL_CTRL1_LINK_RATE_2700:
645 dp_br = 270000 * 2;
646 break;
647 default:
648 dp_br = 0;
649 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n",
650 vgpu->id, port_name(port), dpll_id);
651 }
652
653 return dp_br;
654 }
655
vgpu_update_refresh_rate(struct intel_vgpu * vgpu)656 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
657 {
658 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
659 struct intel_display *display = &dev_priv->display;
660 enum port port;
661 u32 dp_br, link_m, link_n, htotal, vtotal;
662
663 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
664 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &
665 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
666 if (port != PORT_B && port != PORT_D) {
667 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
668 return;
669 }
670
671 /* Calculate DP bitrate from PLL */
672 if (IS_BROADWELL(dev_priv))
673 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port);
674 else if (IS_BROXTON(dev_priv))
675 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port);
676 else
677 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
678
679 /* Get DP link symbol clock M/N */
680 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));
681 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));
682
683 /* Get H/V total from transcoder timing */
684 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
685 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
686
687 if (dp_br && link_n && htotal && vtotal) {
688 u64 pixel_clk = 0;
689 u32 new_rate = 0;
690 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);
691
692 /* Calcuate pixel clock by (ls_clk * M / N) */
693 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);
694 pixel_clk *= MSEC_PER_SEC;
695
696 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */
697 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));
698
699 if (*old_rate != new_rate)
700 *old_rate = new_rate;
701
702 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n",
703 vgpu->id, pipe_name(PIPE_A), new_rate);
704 }
705 }
706
pipeconf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)707 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
708 void *p_data, unsigned int bytes)
709 {
710 u32 data;
711
712 write_vreg(vgpu, offset, p_data, bytes);
713 data = vgpu_vreg(vgpu, offset);
714
715 if (data & TRANSCONF_ENABLE) {
716 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
717 vgpu_update_refresh_rate(vgpu);
718 vgpu_update_vblank_emulation(vgpu, true);
719 } else {
720 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
721 vgpu_update_vblank_emulation(vgpu, false);
722 }
723 return 0;
724 }
725
726 /* sorted in ascending order */
727 static i915_reg_t force_nonpriv_white_list[] = {
728 _MMIO(0xd80),
729 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
730 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
731 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
732 PS_INVOCATION_COUNT, //_MMIO(0x2348)
733 PS_DEPTH_COUNT, //_MMIO(0x2350)
734 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
735 _MMIO(0x2690),
736 _MMIO(0x2694),
737 _MMIO(0x2698),
738 _MMIO(0x2754),
739 _MMIO(0x28a0),
740 _MMIO(0x4de0),
741 _MMIO(0x4de4),
742 _MMIO(0x4dfc),
743 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
744 _MMIO(0x7014),
745 HDC_CHICKEN0,//_MMIO(0x7300)
746 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
747 _MMIO(0x7700),
748 _MMIO(0x7704),
749 _MMIO(0x7708),
750 _MMIO(0x770c),
751 _MMIO(0x83a8),
752 _MMIO(0xb110),
753 _MMIO(0xb118),
754 _MMIO(0xe100),
755 _MMIO(0xe18c),
756 _MMIO(0xe48c),
757 _MMIO(0xe5f4),
758 _MMIO(0x64844),
759 };
760
761 /* a simple bsearch */
in_whitelist(u32 reg)762 static inline bool in_whitelist(u32 reg)
763 {
764 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
765 i915_reg_t *array = force_nonpriv_white_list;
766
767 while (left < right) {
768 int mid = (left + right)/2;
769
770 if (reg > array[mid].reg)
771 left = mid + 1;
772 else if (reg < array[mid].reg)
773 right = mid;
774 else
775 return true;
776 }
777 return false;
778 }
779
force_nonpriv_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)780 static int force_nonpriv_write(struct intel_vgpu *vgpu,
781 unsigned int offset, void *p_data, unsigned int bytes)
782 {
783 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
784 const struct intel_engine_cs *engine =
785 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
786
787 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
788 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
789 vgpu->id, offset, bytes);
790 return -EINVAL;
791 }
792
793 if (!in_whitelist(reg_nonpriv) &&
794 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
795 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
796 vgpu->id, reg_nonpriv, offset);
797 } else
798 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
799
800 return 0;
801 }
802
ddi_buf_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)803 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
804 void *p_data, unsigned int bytes)
805 {
806 write_vreg(vgpu, offset, p_data, bytes);
807
808 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
809 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
810 } else {
811 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
812 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
813 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
814 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
815 }
816 return 0;
817 }
818
fdi_rx_iir_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)819 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
820 unsigned int offset, void *p_data, unsigned int bytes)
821 {
822 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
823 return 0;
824 }
825
826 #define FDI_LINK_TRAIN_PATTERN1 0
827 #define FDI_LINK_TRAIN_PATTERN2 1
828
fdi_auto_training_started(struct intel_vgpu * vgpu)829 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
830 {
831 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
832 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
833 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
834
835 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
836 (rx_ctl & FDI_RX_ENABLE) &&
837 (rx_ctl & FDI_AUTO_TRAINING) &&
838 (tx_ctl & DP_TP_CTL_ENABLE) &&
839 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
840 return 1;
841 else
842 return 0;
843 }
844
check_fdi_rx_train_status(struct intel_vgpu * vgpu,enum pipe pipe,unsigned int train_pattern)845 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
846 enum pipe pipe, unsigned int train_pattern)
847 {
848 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
849 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
850 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
851 unsigned int fdi_iir_check_bits;
852
853 fdi_rx_imr = FDI_RX_IMR(pipe);
854 fdi_tx_ctl = FDI_TX_CTL(pipe);
855 fdi_rx_ctl = FDI_RX_CTL(pipe);
856
857 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
858 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
859 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
860 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
861 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
862 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
863 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
864 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
865 } else {
866 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
867 return -EINVAL;
868 }
869
870 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
871 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
872
873 /* If imr bit has been masked */
874 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
875 return 0;
876
877 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
878 == fdi_tx_check_bits)
879 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
880 == fdi_rx_check_bits))
881 return 1;
882 else
883 return 0;
884 }
885
886 #define INVALID_INDEX (~0U)
887
calc_index(unsigned int offset,i915_reg_t _start,i915_reg_t _next,i915_reg_t _end)888 static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
889 i915_reg_t _next, i915_reg_t _end)
890 {
891 u32 start = i915_mmio_reg_offset(_start);
892 u32 next = i915_mmio_reg_offset(_next);
893 u32 end = i915_mmio_reg_offset(_end);
894 u32 stride = next - start;
895
896 if (offset < start || offset > end)
897 return INVALID_INDEX;
898 offset -= start;
899 return offset / stride;
900 }
901
902 #define FDI_RX_CTL_TO_PIPE(offset) \
903 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
904
905 #define FDI_TX_CTL_TO_PIPE(offset) \
906 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
907
908 #define FDI_RX_IMR_TO_PIPE(offset) \
909 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
910
update_fdi_rx_iir_status(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)911 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
912 unsigned int offset, void *p_data, unsigned int bytes)
913 {
914 i915_reg_t fdi_rx_iir;
915 unsigned int index;
916 int ret;
917
918 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
919 index = FDI_RX_CTL_TO_PIPE(offset);
920 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
921 index = FDI_TX_CTL_TO_PIPE(offset);
922 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
923 index = FDI_RX_IMR_TO_PIPE(offset);
924 else {
925 gvt_vgpu_err("Unsupported registers %x\n", offset);
926 return -EINVAL;
927 }
928
929 write_vreg(vgpu, offset, p_data, bytes);
930
931 fdi_rx_iir = FDI_RX_IIR(index);
932
933 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
934 if (ret < 0)
935 return ret;
936 if (ret)
937 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
938
939 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
940 if (ret < 0)
941 return ret;
942 if (ret)
943 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
944
945 if (offset == _FDI_RXA_CTL)
946 if (fdi_auto_training_started(vgpu))
947 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
948 DP_TP_STATUS_AUTOTRAIN_DONE;
949 return 0;
950 }
951
952 #define DP_TP_CTL_TO_PORT(offset) \
953 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
954
dp_tp_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)955 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
956 void *p_data, unsigned int bytes)
957 {
958 i915_reg_t status_reg;
959 unsigned int index;
960 u32 data;
961
962 write_vreg(vgpu, offset, p_data, bytes);
963
964 index = DP_TP_CTL_TO_PORT(offset);
965 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
966 if (data == 0x2) {
967 status_reg = DP_TP_STATUS(index);
968 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
969 }
970 return 0;
971 }
972
dp_tp_status_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)973 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
974 unsigned int offset, void *p_data, unsigned int bytes)
975 {
976 u32 reg_val;
977 u32 sticky_mask;
978
979 reg_val = *((u32 *)p_data);
980 sticky_mask = GENMASK(27, 26) | (1 << 24);
981
982 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
983 (vgpu_vreg(vgpu, offset) & sticky_mask);
984 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
985 return 0;
986 }
987
pch_adpa_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)988 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
989 unsigned int offset, void *p_data, unsigned int bytes)
990 {
991 u32 data;
992
993 write_vreg(vgpu, offset, p_data, bytes);
994 data = vgpu_vreg(vgpu, offset);
995
996 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
997 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
998 return 0;
999 }
1000
south_chicken2_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1001 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
1002 unsigned int offset, void *p_data, unsigned int bytes)
1003 {
1004 u32 data;
1005
1006 write_vreg(vgpu, offset, p_data, bytes);
1007 data = vgpu_vreg(vgpu, offset);
1008
1009 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
1010 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
1011 else
1012 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
1013 return 0;
1014 }
1015
1016 #define DSPSURF_TO_PIPE(display, offset) \
1017 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
1018
pri_surf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1019 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1020 void *p_data, unsigned int bytes)
1021 {
1022 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1023 struct intel_display *display = &dev_priv->display;
1024 u32 pipe = DSPSURF_TO_PIPE(display, offset);
1025 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
1026
1027 write_vreg(vgpu, offset, p_data, bytes);
1028 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
1029
1030 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
1031
1032 if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)
1033 intel_vgpu_trigger_virtual_event(vgpu, event);
1034 else
1035 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1036
1037 return 0;
1038 }
1039
1040 #define SPRSURF_TO_PIPE(offset) \
1041 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
1042
spr_surf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1043 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1044 void *p_data, unsigned int bytes)
1045 {
1046 u32 pipe = SPRSURF_TO_PIPE(offset);
1047 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
1048
1049 write_vreg(vgpu, offset, p_data, bytes);
1050 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1051
1052 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
1053 intel_vgpu_trigger_virtual_event(vgpu, event);
1054 else
1055 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1056
1057 return 0;
1058 }
1059
reg50080_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1060 static int reg50080_mmio_write(struct intel_vgpu *vgpu,
1061 unsigned int offset, void *p_data,
1062 unsigned int bytes)
1063 {
1064 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1065 struct intel_display *display = &dev_priv->display;
1066 enum pipe pipe = REG_50080_TO_PIPE(offset);
1067 enum plane_id plane = REG_50080_TO_PLANE(offset);
1068 int event = SKL_FLIP_EVENT(pipe, plane);
1069
1070 write_vreg(vgpu, offset, p_data, bytes);
1071 if (plane == PLANE_PRIMARY) {
1072 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
1073 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
1074 } else {
1075 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1076 }
1077
1078 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
1079 intel_vgpu_trigger_virtual_event(vgpu, event);
1080 else
1081 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1082
1083 return 0;
1084 }
1085
trigger_aux_channel_interrupt(struct intel_vgpu * vgpu,unsigned int reg)1086 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
1087 unsigned int reg)
1088 {
1089 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1090 enum intel_gvt_event_type event;
1091
1092 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
1093 event = AUX_CHANNEL_A;
1094 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||
1095 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
1096 event = AUX_CHANNEL_B;
1097 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||
1098 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
1099 event = AUX_CHANNEL_C;
1100 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||
1101 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
1102 event = AUX_CHANNEL_D;
1103 else {
1104 drm_WARN_ON(&dev_priv->drm, true);
1105 return -EINVAL;
1106 }
1107
1108 intel_vgpu_trigger_virtual_event(vgpu, event);
1109 return 0;
1110 }
1111
dp_aux_ch_ctl_trans_done(struct intel_vgpu * vgpu,u32 value,unsigned int reg,int len,bool data_valid)1112 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
1113 unsigned int reg, int len, bool data_valid)
1114 {
1115 /* mark transaction done */
1116 value |= DP_AUX_CH_CTL_DONE;
1117 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
1118 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
1119
1120 if (data_valid)
1121 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
1122 else
1123 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
1124
1125 /* message size */
1126 value &= ~(0xf << 20);
1127 value |= (len << 20);
1128 vgpu_vreg(vgpu, reg) = value;
1129
1130 if (value & DP_AUX_CH_CTL_INTERRUPT)
1131 return trigger_aux_channel_interrupt(vgpu, reg);
1132 return 0;
1133 }
1134
dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data * dpcd,u8 t)1135 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
1136 u8 t)
1137 {
1138 if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) {
1139 /* training pattern 1 for CR */
1140 /* set LANE0_CR_DONE, LANE1_CR_DONE */
1141 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE |
1142 DP_LANE_CR_DONE << 4;
1143 /* set LANE2_CR_DONE, LANE3_CR_DONE */
1144 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE |
1145 DP_LANE_CR_DONE << 4;
1146 } else if ((t & DP_TRAINING_PATTERN_MASK) ==
1147 DP_TRAINING_PATTERN_2) {
1148 /* training pattern 2 for EQ */
1149 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
1150 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1151 DP_LANE_CHANNEL_EQ_DONE << 4;
1152 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1153 DP_LANE_SYMBOL_LOCKED << 4;
1154 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
1155 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1156 DP_LANE_CHANNEL_EQ_DONE << 4;
1157 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1158 DP_LANE_SYMBOL_LOCKED << 4;
1159 /* set INTERLANE_ALIGN_DONE */
1160 dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |=
1161 DP_INTERLANE_ALIGN_DONE;
1162 } else if ((t & DP_TRAINING_PATTERN_MASK) ==
1163 DP_TRAINING_PATTERN_DISABLE) {
1164 /* finish link training */
1165 /* set sink status as synchronized */
1166 dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS |
1167 DP_RECEIVE_PORT_1_STATUS;
1168 }
1169 }
1170
1171 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1172
1173 #define dpy_is_valid_port(port) \
1174 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
1175
dp_aux_ch_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1176 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
1177 unsigned int offset, void *p_data, unsigned int bytes)
1178 {
1179 struct intel_vgpu_display *display = &vgpu->display;
1180 int msg, addr, ctrl, op, len;
1181 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
1182 struct intel_vgpu_dpcd_data *dpcd = NULL;
1183 struct intel_vgpu_port *port = NULL;
1184 u32 data;
1185
1186 if (!dpy_is_valid_port(port_index)) {
1187 gvt_vgpu_err("Unsupported DP port access!\n");
1188 return 0;
1189 }
1190
1191 write_vreg(vgpu, offset, p_data, bytes);
1192 data = vgpu_vreg(vgpu, offset);
1193
1194 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 &&
1195 offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {
1196 /* SKL DPB/C/D aux ctl register changed */
1197 return 0;
1198 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
1199 offset != i915_mmio_reg_offset(port_index ?
1200 PCH_DP_AUX_CH_CTL(port_index) :
1201 DP_AUX_CH_CTL(port_index))) {
1202 /* write to the data registers */
1203 return 0;
1204 }
1205
1206 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
1207 /* just want to clear the sticky bits */
1208 vgpu_vreg(vgpu, offset) = 0;
1209 return 0;
1210 }
1211
1212 port = &display->ports[port_index];
1213 dpcd = port->dpcd;
1214
1215 /* read out message from DATA1 register */
1216 msg = vgpu_vreg(vgpu, offset + 4);
1217 addr = (msg >> 8) & 0xffff;
1218 ctrl = (msg >> 24) & 0xff;
1219 len = msg & 0xff;
1220 op = ctrl >> 4;
1221
1222 if (op == DP_AUX_NATIVE_WRITE) {
1223 int t;
1224 u8 buf[16];
1225
1226 if ((addr + len + 1) >= DPCD_SIZE) {
1227 /*
1228 * Write request exceeds what we supported,
1229 * DCPD spec: When a Source Device is writing a DPCD
1230 * address not supported by the Sink Device, the Sink
1231 * Device shall reply with AUX NACK and “M” equal to
1232 * zero.
1233 */
1234
1235 /* NAK the write */
1236 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
1237 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
1238 return 0;
1239 }
1240
1241 /*
1242 * Write request format: Headr (command + address + size) occupies
1243 * 4 bytes, followed by (len + 1) bytes of data. See details at
1244 * intel_dp_aux_transfer().
1245 */
1246 if ((len + 1 + 4) > AUX_BURST_SIZE) {
1247 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1248 return -EINVAL;
1249 }
1250
1251 /* unpack data from vreg to buf */
1252 for (t = 0; t < 4; t++) {
1253 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
1254
1255 buf[t * 4] = (r >> 24) & 0xff;
1256 buf[t * 4 + 1] = (r >> 16) & 0xff;
1257 buf[t * 4 + 2] = (r >> 8) & 0xff;
1258 buf[t * 4 + 3] = r & 0xff;
1259 }
1260
1261 /* write to virtual DPCD */
1262 if (dpcd && dpcd->data_valid) {
1263 for (t = 0; t <= len; t++) {
1264 int p = addr + t;
1265
1266 dpcd->data[p] = buf[t];
1267 /* check for link training */
1268 if (p == DP_TRAINING_PATTERN_SET)
1269 dp_aux_ch_ctl_link_training(dpcd,
1270 buf[t]);
1271 }
1272 }
1273
1274 /* ACK the write */
1275 vgpu_vreg(vgpu, offset + 4) = 0;
1276 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1277 dpcd && dpcd->data_valid);
1278 return 0;
1279 }
1280
1281 if (op == DP_AUX_NATIVE_READ) {
1282 int idx, i, ret = 0;
1283
1284 if ((addr + len + 1) >= DPCD_SIZE) {
1285 /*
1286 * read request exceeds what we supported
1287 * DPCD spec: A Sink Device receiving a Native AUX CH
1288 * read request for an unsupported DPCD address must
1289 * reply with an AUX ACK and read data set equal to
1290 * zero instead of replying with AUX NACK.
1291 */
1292
1293 /* ACK the READ*/
1294 vgpu_vreg(vgpu, offset + 4) = 0;
1295 vgpu_vreg(vgpu, offset + 8) = 0;
1296 vgpu_vreg(vgpu, offset + 12) = 0;
1297 vgpu_vreg(vgpu, offset + 16) = 0;
1298 vgpu_vreg(vgpu, offset + 20) = 0;
1299
1300 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1301 true);
1302 return 0;
1303 }
1304
1305 for (idx = 1; idx <= 5; idx++) {
1306 /* clear the data registers */
1307 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1308 }
1309
1310 /*
1311 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1312 */
1313 if ((len + 2) > AUX_BURST_SIZE) {
1314 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1315 return -EINVAL;
1316 }
1317
1318 /* read from virtual DPCD to vreg */
1319 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1320 if (dpcd && dpcd->data_valid) {
1321 for (i = 1; i <= (len + 1); i++) {
1322 int t;
1323
1324 t = dpcd->data[addr + i - 1];
1325 t <<= (24 - 8 * (i % 4));
1326 ret |= t;
1327
1328 if ((i % 4 == 3) || (i == (len + 1))) {
1329 vgpu_vreg(vgpu, offset +
1330 (i / 4 + 1) * 4) = ret;
1331 ret = 0;
1332 }
1333 }
1334 }
1335 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1336 dpcd && dpcd->data_valid);
1337 return 0;
1338 }
1339
1340 /* i2c transaction starts */
1341 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1342
1343 if (data & DP_AUX_CH_CTL_INTERRUPT)
1344 trigger_aux_channel_interrupt(vgpu, offset);
1345 return 0;
1346 }
1347
mbctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1348 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1349 void *p_data, unsigned int bytes)
1350 {
1351 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1352 write_vreg(vgpu, offset, p_data, bytes);
1353 return 0;
1354 }
1355
vga_control_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1356 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1357 void *p_data, unsigned int bytes)
1358 {
1359 bool vga_disable;
1360
1361 write_vreg(vgpu, offset, p_data, bytes);
1362 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1363
1364 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1365 vga_disable ? "Disable" : "Enable");
1366 return 0;
1367 }
1368
read_virtual_sbi_register(struct intel_vgpu * vgpu,unsigned int sbi_offset)1369 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1370 unsigned int sbi_offset)
1371 {
1372 struct intel_vgpu_display *display = &vgpu->display;
1373 int num = display->sbi.number;
1374 int i;
1375
1376 for (i = 0; i < num; ++i)
1377 if (display->sbi.registers[i].offset == sbi_offset)
1378 break;
1379
1380 if (i == num)
1381 return 0;
1382
1383 return display->sbi.registers[i].value;
1384 }
1385
write_virtual_sbi_register(struct intel_vgpu * vgpu,unsigned int offset,u32 value)1386 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1387 unsigned int offset, u32 value)
1388 {
1389 struct intel_vgpu_display *display = &vgpu->display;
1390 int num = display->sbi.number;
1391 int i;
1392
1393 for (i = 0; i < num; ++i) {
1394 if (display->sbi.registers[i].offset == offset)
1395 break;
1396 }
1397
1398 if (i == num) {
1399 if (num == SBI_REG_MAX) {
1400 gvt_vgpu_err("SBI caching meets maximum limits\n");
1401 return;
1402 }
1403 display->sbi.number++;
1404 }
1405
1406 display->sbi.registers[i].offset = offset;
1407 display->sbi.registers[i].value = value;
1408 }
1409
sbi_data_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1410 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1411 void *p_data, unsigned int bytes)
1412 {
1413 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1414 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1415 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1416 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1417 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1418 sbi_offset);
1419 }
1420 read_vreg(vgpu, offset, p_data, bytes);
1421 return 0;
1422 }
1423
sbi_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1424 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1425 void *p_data, unsigned int bytes)
1426 {
1427 u32 data;
1428
1429 write_vreg(vgpu, offset, p_data, bytes);
1430 data = vgpu_vreg(vgpu, offset);
1431
1432 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1433 data |= SBI_READY;
1434
1435 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1436 data |= SBI_RESPONSE_SUCCESS;
1437
1438 vgpu_vreg(vgpu, offset) = data;
1439
1440 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1441 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1442 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1443 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1444
1445 write_virtual_sbi_register(vgpu, sbi_offset,
1446 vgpu_vreg_t(vgpu, SBI_DATA));
1447 }
1448 return 0;
1449 }
1450
1451 #define _vgtif_reg(x) \
1452 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1453
pvinfo_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1454 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1455 void *p_data, unsigned int bytes)
1456 {
1457 bool invalid_read = false;
1458
1459 read_vreg(vgpu, offset, p_data, bytes);
1460
1461 switch (offset) {
1462 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1463 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1464 invalid_read = true;
1465 break;
1466 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1467 _vgtif_reg(avail_rs.fence_num):
1468 if (offset + bytes >
1469 _vgtif_reg(avail_rs.fence_num) + 4)
1470 invalid_read = true;
1471 break;
1472 case 0x78010: /* vgt_caps */
1473 case 0x7881c:
1474 break;
1475 default:
1476 invalid_read = true;
1477 break;
1478 }
1479 if (invalid_read)
1480 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1481 offset, bytes, *(u32 *)p_data);
1482 vgpu->pv_notified = true;
1483 return 0;
1484 }
1485
handle_g2v_notification(struct intel_vgpu * vgpu,int notification)1486 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1487 {
1488 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1489 struct intel_vgpu_mm *mm;
1490 u64 *pdps;
1491
1492 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1493
1494 switch (notification) {
1495 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1496 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1497 fallthrough;
1498 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1499 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1500 return PTR_ERR_OR_ZERO(mm);
1501 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1502 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1503 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1504 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1505 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1506 case 1: /* Remove this in guest driver. */
1507 break;
1508 default:
1509 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1510 }
1511 return 0;
1512 }
1513
send_display_ready_uevent(struct intel_vgpu * vgpu,int ready)1514 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1515 {
1516 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj;
1517 char *env[3] = {NULL, NULL, NULL};
1518 char vmid_str[20];
1519 char display_ready_str[20];
1520
1521 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1522 env[0] = display_ready_str;
1523
1524 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1525 env[1] = vmid_str;
1526
1527 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1528 }
1529
pvinfo_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1530 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1531 void *p_data, unsigned int bytes)
1532 {
1533 u32 data = *(u32 *)p_data;
1534 bool invalid_write = false;
1535
1536 switch (offset) {
1537 case _vgtif_reg(display_ready):
1538 send_display_ready_uevent(vgpu, data ? 1 : 0);
1539 break;
1540 case _vgtif_reg(g2v_notify):
1541 handle_g2v_notification(vgpu, data);
1542 break;
1543 /* add xhot and yhot to handled list to avoid error log */
1544 case _vgtif_reg(cursor_x_hot):
1545 case _vgtif_reg(cursor_y_hot):
1546 case _vgtif_reg(pdp[0].lo):
1547 case _vgtif_reg(pdp[0].hi):
1548 case _vgtif_reg(pdp[1].lo):
1549 case _vgtif_reg(pdp[1].hi):
1550 case _vgtif_reg(pdp[2].lo):
1551 case _vgtif_reg(pdp[2].hi):
1552 case _vgtif_reg(pdp[3].lo):
1553 case _vgtif_reg(pdp[3].hi):
1554 case _vgtif_reg(execlist_context_descriptor_lo):
1555 case _vgtif_reg(execlist_context_descriptor_hi):
1556 break;
1557 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1558 invalid_write = true;
1559 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1560 break;
1561 default:
1562 invalid_write = true;
1563 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1564 offset, bytes, data);
1565 break;
1566 }
1567
1568 if (!invalid_write)
1569 write_vreg(vgpu, offset, p_data, bytes);
1570
1571 return 0;
1572 }
1573
pf_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1574 static int pf_write(struct intel_vgpu *vgpu,
1575 unsigned int offset, void *p_data, unsigned int bytes)
1576 {
1577 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1578 u32 val = *(u32 *)p_data;
1579
1580 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1581 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1582 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
1583 drm_WARN_ONCE(&i915->drm, true,
1584 "VM(%d): guest is trying to scaling a plane\n",
1585 vgpu->id);
1586 return 0;
1587 }
1588
1589 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1590 }
1591
power_well_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1592 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1593 unsigned int offset, void *p_data, unsigned int bytes)
1594 {
1595 write_vreg(vgpu, offset, p_data, bytes);
1596
1597 if (vgpu_vreg(vgpu, offset) &
1598 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1599 vgpu_vreg(vgpu, offset) |=
1600 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1601 else
1602 vgpu_vreg(vgpu, offset) &=
1603 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1604 return 0;
1605 }
1606
gen9_dbuf_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1607 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1608 unsigned int offset, void *p_data, unsigned int bytes)
1609 {
1610 write_vreg(vgpu, offset, p_data, bytes);
1611
1612 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1613 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1614 else
1615 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1616
1617 return 0;
1618 }
1619
fpga_dbg_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1620 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1621 unsigned int offset, void *p_data, unsigned int bytes)
1622 {
1623 write_vreg(vgpu, offset, p_data, bytes);
1624
1625 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1626 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1627 return 0;
1628 }
1629
dma_ctrl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1630 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1631 void *p_data, unsigned int bytes)
1632 {
1633 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1634 u32 mode;
1635
1636 write_vreg(vgpu, offset, p_data, bytes);
1637 mode = vgpu_vreg(vgpu, offset);
1638
1639 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1640 drm_WARN_ONCE(&i915->drm, 1,
1641 "VM(%d): iGVT-g doesn't support GuC\n",
1642 vgpu->id);
1643 return 0;
1644 }
1645
1646 return 0;
1647 }
1648
gen9_trtte_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1649 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1650 void *p_data, unsigned int bytes)
1651 {
1652 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1653 u32 trtte = *(u32 *)p_data;
1654
1655 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1656 drm_WARN(&i915->drm, 1,
1657 "VM(%d): Use physical address for TRTT!\n",
1658 vgpu->id);
1659 return -EINVAL;
1660 }
1661 write_vreg(vgpu, offset, p_data, bytes);
1662
1663 return 0;
1664 }
1665
gen9_trtt_chicken_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1666 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1667 void *p_data, unsigned int bytes)
1668 {
1669 write_vreg(vgpu, offset, p_data, bytes);
1670 return 0;
1671 }
1672
dpll_status_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1673 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1674 void *p_data, unsigned int bytes)
1675 {
1676 u32 v = 0;
1677
1678 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1679 v |= (1 << 0);
1680
1681 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1682 v |= (1 << 8);
1683
1684 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1685 v |= (1 << 16);
1686
1687 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1688 v |= (1 << 24);
1689
1690 vgpu_vreg(vgpu, offset) = v;
1691
1692 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1693 }
1694
mailbox_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1695 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1696 void *p_data, unsigned int bytes)
1697 {
1698 u32 value = *(u32 *)p_data;
1699 u32 cmd = value & 0xff;
1700 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1701
1702 switch (cmd) {
1703 case GEN9_PCODE_READ_MEM_LATENCY:
1704 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1705 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1706 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1707 IS_COMETLAKE(vgpu->gvt->gt->i915)) {
1708 /**
1709 * "Read memory latency" command on gen9.
1710 * Below memory latency values are read
1711 * from skylake platform.
1712 */
1713 if (!*data0)
1714 *data0 = 0x1e1a1100;
1715 else
1716 *data0 = 0x61514b3d;
1717 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) {
1718 /**
1719 * "Read memory latency" command on gen9.
1720 * Below memory latency values are read
1721 * from Broxton MRB.
1722 */
1723 if (!*data0)
1724 *data0 = 0x16080707;
1725 else
1726 *data0 = 0x16161616;
1727 }
1728 break;
1729 case SKL_PCODE_CDCLK_CONTROL:
1730 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1731 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1732 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1733 IS_COMETLAKE(vgpu->gvt->gt->i915))
1734 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1735 break;
1736 case GEN6_PCODE_READ_RC6VIDS:
1737 *data0 |= 0x1;
1738 break;
1739 }
1740
1741 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1742 vgpu->id, value, *data0);
1743 /**
1744 * PCODE_READY clear means ready for pcode read/write,
1745 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1746 * always emulate as pcode read/write success and ready for access
1747 * anytime, since we don't touch real physical registers here.
1748 */
1749 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1750 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1751 }
1752
hws_pga_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1753 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1754 void *p_data, unsigned int bytes)
1755 {
1756 u32 value = *(u32 *)p_data;
1757 const struct intel_engine_cs *engine =
1758 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1759
1760 if (value != 0 &&
1761 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1762 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1763 offset, value);
1764 return -EINVAL;
1765 }
1766
1767 /*
1768 * Need to emulate all the HWSP register write to ensure host can
1769 * update the VM CSB status correctly. Here listed registers can
1770 * support BDW, SKL or other platforms with same HWSP registers.
1771 */
1772 if (unlikely(!engine)) {
1773 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1774 offset);
1775 return -EINVAL;
1776 }
1777 vgpu->hws_pga[engine->id] = value;
1778 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1779 vgpu->id, value, offset);
1780
1781 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1782 }
1783
skl_power_well_ctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1784 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1785 unsigned int offset, void *p_data, unsigned int bytes)
1786 {
1787 u32 v = *(u32 *)p_data;
1788
1789 if (IS_BROXTON(vgpu->gvt->gt->i915))
1790 v &= (1 << 31) | (1 << 29);
1791 else
1792 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1793 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1794 v |= (v >> 1);
1795
1796 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1797 }
1798
skl_lcpll_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1799 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1800 void *p_data, unsigned int bytes)
1801 {
1802 u32 v = *(u32 *)p_data;
1803
1804 /* other bits are MBZ. */
1805 v &= (1 << 31) | (1 << 30);
1806 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1807
1808 vgpu_vreg(vgpu, offset) = v;
1809
1810 return 0;
1811 }
1812
bxt_de_pll_enable_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1813 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1814 unsigned int offset, void *p_data, unsigned int bytes)
1815 {
1816 u32 v = *(u32 *)p_data;
1817
1818 if (v & BXT_DE_PLL_PLL_ENABLE)
1819 v |= BXT_DE_PLL_LOCK;
1820
1821 vgpu_vreg(vgpu, offset) = v;
1822
1823 return 0;
1824 }
1825
bxt_port_pll_enable_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1826 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1827 unsigned int offset, void *p_data, unsigned int bytes)
1828 {
1829 u32 v = *(u32 *)p_data;
1830
1831 if (v & PORT_PLL_ENABLE)
1832 v |= PORT_PLL_LOCK;
1833
1834 vgpu_vreg(vgpu, offset) = v;
1835
1836 return 0;
1837 }
1838
bxt_phy_ctl_family_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1839 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1840 unsigned int offset, void *p_data, unsigned int bytes)
1841 {
1842 u32 v = *(u32 *)p_data;
1843 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1844
1845 switch (offset) {
1846 case _PHY_CTL_FAMILY_EDP:
1847 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1848 break;
1849 case _PHY_CTL_FAMILY_DDI:
1850 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1851 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1852 break;
1853 }
1854
1855 vgpu_vreg(vgpu, offset) = v;
1856
1857 return 0;
1858 }
1859
bxt_port_tx_dw3_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1860 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1861 unsigned int offset, void *p_data, unsigned int bytes)
1862 {
1863 u32 v = vgpu_vreg(vgpu, offset);
1864
1865 v &= ~UNIQUE_TRANGE_EN_METHOD;
1866
1867 vgpu_vreg(vgpu, offset) = v;
1868
1869 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1870 }
1871
bxt_pcs_dw12_grp_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1872 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1873 unsigned int offset, void *p_data, unsigned int bytes)
1874 {
1875 u32 v = *(u32 *)p_data;
1876
1877 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1878 vgpu_vreg(vgpu, offset - 0x600) = v;
1879 vgpu_vreg(vgpu, offset - 0x800) = v;
1880 } else {
1881 vgpu_vreg(vgpu, offset - 0x400) = v;
1882 vgpu_vreg(vgpu, offset - 0x600) = v;
1883 }
1884
1885 vgpu_vreg(vgpu, offset) = v;
1886
1887 return 0;
1888 }
1889
bxt_gt_disp_pwron_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1890 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1891 unsigned int offset, void *p_data, unsigned int bytes)
1892 {
1893 u32 v = *(u32 *)p_data;
1894
1895 if (v & BIT(0)) {
1896 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1897 ~PHY_RESERVED;
1898 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1899 PHY_POWER_GOOD;
1900 }
1901
1902 if (v & BIT(1)) {
1903 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1904 ~PHY_RESERVED;
1905 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1906 PHY_POWER_GOOD;
1907 }
1908
1909
1910 vgpu_vreg(vgpu, offset) = v;
1911
1912 return 0;
1913 }
1914
edp_psr_imr_iir_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1915 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1916 unsigned int offset, void *p_data, unsigned int bytes)
1917 {
1918 vgpu_vreg(vgpu, offset) = 0;
1919 return 0;
1920 }
1921
1922 /*
1923 * FixMe:
1924 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1925 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1926 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1927 * these MI_BATCH_BUFFER.
1928 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1929 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1930 * The performance is still expected to be low, will need further improvement.
1931 */
bxt_ppat_low_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1932 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1933 void *p_data, unsigned int bytes)
1934 {
1935 u64 pat =
1936 GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1937 GEN8_PPAT(1, 0) |
1938 GEN8_PPAT(2, 0) |
1939 GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1940 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1941 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1942 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1943 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1944
1945 vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1946
1947 return 0;
1948 }
1949
guc_status_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1950 static int guc_status_read(struct intel_vgpu *vgpu,
1951 unsigned int offset, void *p_data,
1952 unsigned int bytes)
1953 {
1954 /* keep MIA_IN_RESET before clearing */
1955 read_vreg(vgpu, offset, p_data, bytes);
1956 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1957 return 0;
1958 }
1959
mmio_read_from_hw(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1960 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1961 unsigned int offset, void *p_data, unsigned int bytes)
1962 {
1963 struct intel_gvt *gvt = vgpu->gvt;
1964 const struct intel_engine_cs *engine =
1965 intel_gvt_render_mmio_to_engine(gvt, offset);
1966
1967 /**
1968 * Read HW reg in following case
1969 * a. the offset isn't a ring mmio
1970 * b. the offset's ring is running on hw.
1971 * c. the offset is ring time stamp mmio
1972 */
1973
1974 if (!engine ||
1975 vgpu == gvt->scheduler.engine_owner[engine->id] ||
1976 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1977 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
1978 mmio_hw_access_pre(gvt->gt);
1979 vgpu_vreg(vgpu, offset) =
1980 intel_uncore_read(gvt->gt->uncore, _MMIO(offset));
1981 mmio_hw_access_post(gvt->gt);
1982 }
1983
1984 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1985 }
1986
elsp_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1987 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1988 void *p_data, unsigned int bytes)
1989 {
1990 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1991 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1992 struct intel_vgpu_execlist *execlist;
1993 u32 data = *(u32 *)p_data;
1994 int ret = 0;
1995
1996 if (drm_WARN_ON(&i915->drm, !engine))
1997 return -EINVAL;
1998
1999 /*
2000 * Due to d3_entered is used to indicate skipping PPGTT invalidation on
2001 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after
2002 * vGPU reset if in resuming.
2003 * In S0ix exit, the device power state also transite from D3 to D0 as
2004 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After
2005 * S0ix exit, all engines continue to work. However the d3_entered
2006 * remains set which will break next vGPU reset logic (miss the expected
2007 * PPGTT invalidation).
2008 * Engines can only work in D0. Thus the 1st elsp write gives GVT a
2009 * chance to clear d3_entered.
2010 */
2011 if (vgpu->d3_entered)
2012 vgpu->d3_entered = false;
2013
2014 execlist = &vgpu->submission.execlist[engine->id];
2015
2016 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
2017 if (execlist->elsp_dwords.index == 3) {
2018 ret = intel_vgpu_submit_execlist(vgpu, engine);
2019 if(ret)
2020 gvt_vgpu_err("fail submit workload on ring %s\n",
2021 engine->name);
2022 }
2023
2024 ++execlist->elsp_dwords.index;
2025 execlist->elsp_dwords.index &= 0x3;
2026 return ret;
2027 }
2028
ring_mode_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2029 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2030 void *p_data, unsigned int bytes)
2031 {
2032 u32 data = *(u32 *)p_data;
2033 const struct intel_engine_cs *engine =
2034 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
2035 bool enable_execlist;
2036 int ret;
2037
2038 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
2039 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2040 IS_COMETLAKE(vgpu->gvt->gt->i915))
2041 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
2042 write_vreg(vgpu, offset, p_data, bytes);
2043
2044 if (IS_MASKED_BITS_ENABLED(data, 1)) {
2045 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2046 return 0;
2047 }
2048
2049 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2050 IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
2051 IS_MASKED_BITS_ENABLED(data, 2)) {
2052 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2053 return 0;
2054 }
2055
2056 /* when PPGTT mode enabled, we will check if guest has called
2057 * pvinfo, if not, we will treat this guest as non-gvtg-aware
2058 * guest, and stop emulating its cfg space, mmio, gtt, etc.
2059 */
2060 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
2061 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
2062 !vgpu->pv_notified) {
2063 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2064 return 0;
2065 }
2066 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
2067 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
2068 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
2069
2070 gvt_dbg_core("EXECLIST %s on ring %s\n",
2071 (enable_execlist ? "enabling" : "disabling"),
2072 engine->name);
2073
2074 if (!enable_execlist)
2075 return 0;
2076
2077 ret = intel_vgpu_select_submission_ops(vgpu,
2078 engine->mask,
2079 INTEL_VGPU_EXECLIST_SUBMISSION);
2080 if (ret)
2081 return ret;
2082
2083 intel_vgpu_start_schedule(vgpu);
2084 }
2085 return 0;
2086 }
2087
gvt_reg_tlb_control_handler(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2088 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
2089 unsigned int offset, void *p_data, unsigned int bytes)
2090 {
2091 unsigned int id = 0;
2092
2093 write_vreg(vgpu, offset, p_data, bytes);
2094 vgpu_vreg(vgpu, offset) = 0;
2095
2096 switch (offset) {
2097 case 0x4260:
2098 id = RCS0;
2099 break;
2100 case 0x4264:
2101 id = VCS0;
2102 break;
2103 case 0x4268:
2104 id = VCS1;
2105 break;
2106 case 0x426c:
2107 id = BCS0;
2108 break;
2109 case 0x4270:
2110 id = VECS0;
2111 break;
2112 default:
2113 return -EINVAL;
2114 }
2115 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
2116
2117 return 0;
2118 }
2119
ring_reset_ctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2120 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
2121 unsigned int offset, void *p_data, unsigned int bytes)
2122 {
2123 u32 data;
2124
2125 write_vreg(vgpu, offset, p_data, bytes);
2126 data = vgpu_vreg(vgpu, offset);
2127
2128 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
2129 data |= RESET_CTL_READY_TO_RESET;
2130 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
2131 data &= ~RESET_CTL_READY_TO_RESET;
2132
2133 vgpu_vreg(vgpu, offset) = data;
2134 return 0;
2135 }
2136
csfe_chicken1_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2137 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
2138 unsigned int offset, void *p_data,
2139 unsigned int bytes)
2140 {
2141 u32 data = *(u32 *)p_data;
2142
2143 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2144 write_vreg(vgpu, offset, p_data, bytes);
2145
2146 if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
2147 IS_MASKED_BITS_ENABLED(data, 0x8))
2148 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2149
2150 return 0;
2151 }
2152
2153 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
2154 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
2155 s, f, am, rm, d, r, w); \
2156 if (ret) \
2157 return ret; \
2158 } while (0)
2159
2160 #define MMIO_DH(reg, d, r, w) \
2161 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2162
2163 #define MMIO_DFH(reg, d, f, r, w) \
2164 MMIO_F(reg, 4, f, 0, 0, d, r, w)
2165
2166 #define MMIO_GM(reg, d, r, w) \
2167 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2168
2169 #define MMIO_GM_RDR(reg, d, r, w) \
2170 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2171
2172 #define MMIO_RO(reg, d, f, rm, r, w) \
2173 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2174
2175 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
2176 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2177 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
2178 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
2179 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
2180 if (HAS_ENGINE(gvt->gt, VCS1)) \
2181 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
2182 } while (0)
2183
2184 #define MMIO_RING_DFH(prefix, d, f, r, w) \
2185 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2186
2187 #define MMIO_RING_GM(prefix, d, r, w) \
2188 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2189
2190 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
2191 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2192
2193 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
2194 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2195
init_generic_mmio_info(struct intel_gvt * gvt)2196 static int init_generic_mmio_info(struct intel_gvt *gvt)
2197 {
2198 struct drm_i915_private *dev_priv = gvt->gt->i915;
2199 struct intel_display *display = &dev_priv->display;
2200 int ret;
2201
2202 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
2203 intel_vgpu_reg_imr_handler);
2204
2205 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
2206 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
2207 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
2208
2209 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
2210
2211
2212 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
2213 gamw_echo_dev_rw_ia_write);
2214
2215 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2216 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2217 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2218
2219 #define RING_REG(base) _MMIO((base) + 0x28)
2220 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2221 #undef RING_REG
2222
2223 #define RING_REG(base) _MMIO((base) + 0x134)
2224 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2225 #undef RING_REG
2226
2227 #define RING_REG(base) _MMIO((base) + 0x6c)
2228 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
2229 #undef RING_REG
2230 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
2231
2232 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
2233 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
2234 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
2235
2236 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
2237 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
2238 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
2239 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
2240 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
2241
2242 /* RING MODE */
2243 #define RING_REG(base) _MMIO((base) + 0x29c)
2244 MMIO_RING_DFH(RING_REG, D_ALL,
2245 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
2246 ring_mode_mmio_write);
2247 #undef RING_REG
2248
2249 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2250 NULL, NULL);
2251 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2252 NULL, NULL);
2253 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
2254 mmio_read_from_hw, NULL);
2255 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
2256 mmio_read_from_hw, NULL);
2257
2258 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2259 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2260 NULL, NULL);
2261 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2262 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2263 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2264
2265 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2266 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2267 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2268 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
2269 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2270 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2271 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
2272 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2273 NULL, NULL);
2274 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2275 NULL, NULL);
2276 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
2277 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
2278 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
2279 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
2280 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
2281 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
2282 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2283 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2284 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2285 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2286
2287 /* display */
2288 MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,
2289 pipeconf_mmio_write);
2290 MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,
2291 pipeconf_mmio_write);
2292 MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,
2293 pipeconf_mmio_write);
2294 MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,
2295 pipeconf_mmio_write);
2296 MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2297 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2298 reg50080_mmio_write);
2299 MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2300 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2301 reg50080_mmio_write);
2302 MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2303 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2304 reg50080_mmio_write);
2305 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2306 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2307 reg50080_mmio_write);
2308 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2309 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2310 reg50080_mmio_write);
2311 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2312 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2313 reg50080_mmio_write);
2314
2315 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2316 gmbus_mmio_write);
2317 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2318
2319 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2320 dp_aux_ch_ctl_mmio_write);
2321 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2322 dp_aux_ch_ctl_mmio_write);
2323 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2324 dp_aux_ch_ctl_mmio_write);
2325
2326 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2327
2328 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2329 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2330
2331 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2332 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2333 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2334 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2335 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2336 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2337 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2338 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2339 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2340 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2341 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2342 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2343 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2344 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2345 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2346 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2347
2348 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2349 PORTA_HOTPLUG_STATUS_MASK
2350 | PORTB_HOTPLUG_STATUS_MASK
2351 | PORTC_HOTPLUG_STATUS_MASK
2352 | PORTD_HOTPLUG_STATUS_MASK,
2353 NULL, NULL);
2354
2355 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2356 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2357 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2358 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2359 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2360
2361 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
2362 dp_aux_ch_ctl_mmio_write);
2363
2364 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2365 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2366 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2367 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2368 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2369
2370 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2371 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2372 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2373 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2374 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2375
2376 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2377 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2378 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2379 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2380 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2381
2382 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2383 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2384 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2385 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2386
2387 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2388 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2389 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2390 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2391 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2392 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2393 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2394 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2395 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2396 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2397 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2398 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2399 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2400
2401 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2402 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2403 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2404
2405 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2406 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2407
2408 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2409 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2410
2411 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2412 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2413 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2414 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2415 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2416 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2417
2418 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2419 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2420 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2421 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2422
2423 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2424 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2425 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2426
2427 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2428 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2429 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2430 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2431 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2432 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2433 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2434 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2435 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2436 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2437 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2438 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2439 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2440 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2441 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2442 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2443 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2444
2445 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2446 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
2447 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2448 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2449 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2450 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2451 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2452 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2453 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2454 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2455 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2456
2457 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2458 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2459 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2460
2461 return 0;
2462 }
2463
init_bdw_mmio_info(struct intel_gvt * gvt)2464 static int init_bdw_mmio_info(struct intel_gvt *gvt)
2465 {
2466 int ret;
2467
2468 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2469 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2470 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2471
2472 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2473 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2474 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2475
2476 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2477 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2478 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2479
2480 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2481 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2482 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2483
2484 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2485 intel_vgpu_reg_imr_handler);
2486 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2487 intel_vgpu_reg_ier_handler);
2488 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2489 intel_vgpu_reg_iir_handler);
2490
2491 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2492 intel_vgpu_reg_imr_handler);
2493 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2494 intel_vgpu_reg_ier_handler);
2495 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2496 intel_vgpu_reg_iir_handler);
2497
2498 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2499 intel_vgpu_reg_imr_handler);
2500 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2501 intel_vgpu_reg_ier_handler);
2502 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2503 intel_vgpu_reg_iir_handler);
2504
2505 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2506 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2507 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2508
2509 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2510 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2511 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2512
2513 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2514 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2515 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2516
2517 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2518 intel_vgpu_reg_master_irq_handler);
2519
2520 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
2521 mmio_read_from_hw, NULL);
2522
2523 #define RING_REG(base) _MMIO((base) + 0xd0)
2524 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2525 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2526 ring_reset_ctl_write);
2527 #undef RING_REG
2528
2529 #define RING_REG(base) _MMIO((base) + 0x230)
2530 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2531 #undef RING_REG
2532
2533 #define RING_REG(base) _MMIO((base) + 0x234)
2534 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
2535 NULL, NULL);
2536 #undef RING_REG
2537
2538 #define RING_REG(base) _MMIO((base) + 0x244)
2539 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2540 #undef RING_REG
2541
2542 #define RING_REG(base) _MMIO((base) + 0x370)
2543 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2544 #undef RING_REG
2545
2546 #define RING_REG(base) _MMIO((base) + 0x3a0)
2547 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2548 #undef RING_REG
2549
2550 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2551
2552 #define RING_REG(base) _MMIO((base) + 0x270)
2553 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2554 #undef RING_REG
2555
2556 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2557
2558 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2559
2560 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2561 NULL, NULL);
2562 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2563 NULL, NULL);
2564 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2565
2566 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2567 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2568 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2569 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2570 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2571
2572 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
2573 D_BDW_PLUS, NULL, force_nonpriv_write);
2574
2575 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2576
2577 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2578
2579 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2580 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2581 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2582 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2583
2584 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2585
2586 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2587 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2588 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2589 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2590 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2591 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2592 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2593 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2594 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2595 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2596 return 0;
2597 }
2598
init_skl_mmio_info(struct intel_gvt * gvt)2599 static int init_skl_mmio_info(struct intel_gvt *gvt)
2600 {
2601 int ret;
2602
2603 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2604 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2605 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2606 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
2607 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2608 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2609
2610 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2611 dp_aux_ch_ctl_mmio_write);
2612 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2613 dp_aux_ch_ctl_mmio_write);
2614 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2615 dp_aux_ch_ctl_mmio_write);
2616
2617 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2618
2619 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2620
2621 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2622 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2623 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2624 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2625 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2626 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2627
2628 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2629 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2630 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2631 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2632 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2633 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2634
2635 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2636 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2637 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2638 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2639 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2640 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2641
2642 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2643 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2644 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2645 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2646 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2647 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2648
2649 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2650 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2651 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2652 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2653
2654 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2656 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2657 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2658
2659 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2660 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2661 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2662 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2663
2664 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2665 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2666 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2667
2668 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2669 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2670 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2671
2672 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2673 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2674 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2675
2676 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2677 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2678 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2679
2680 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2681 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2682 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2683
2684 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2685 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2686 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2687 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2688
2689 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2691 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2692 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2693
2694 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2696 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2697 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2698
2699 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2700 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2701 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2703
2704 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2705 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2706 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2707 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2708
2709 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2710 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2711 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2712 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2713
2714 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2715 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2716 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2717 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2718
2719 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2720 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2721 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2722 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2723
2724 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2725 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2726 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2727 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2728
2729 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2730
2731 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2732 NULL, NULL);
2733 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2734 NULL, NULL);
2735
2736 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
2737 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2738 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2739 NULL, NULL);
2740
2741 /* TRTT */
2742 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2743 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2744 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2745 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2746 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2747 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
2748 NULL, gen9_trtte_write);
2749 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
2750 NULL, gen9_trtt_chicken_write);
2751
2752 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2753 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2754
2755 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
2756 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2757 NULL, csfe_chicken1_mmio_write);
2758 #undef CSFE_CHICKEN1_REG
2759 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2760 NULL, NULL);
2761 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2762 NULL, NULL);
2763
2764 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
2765 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2766
2767 return 0;
2768 }
2769
init_bxt_mmio_info(struct intel_gvt * gvt)2770 static int init_bxt_mmio_info(struct intel_gvt *gvt)
2771 {
2772 int ret;
2773
2774 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
2775 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
2776 NULL, bxt_phy_ctl_family_write);
2777 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
2778 NULL, bxt_phy_ctl_family_write);
2779 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
2780 NULL, bxt_port_pll_enable_write);
2781 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
2782 NULL, bxt_port_pll_enable_write);
2783 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
2784 bxt_port_pll_enable_write);
2785
2786 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
2787 NULL, bxt_pcs_dw12_grp_write);
2788 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
2789 bxt_port_tx_dw3_read, NULL);
2790 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
2791 NULL, bxt_pcs_dw12_grp_write);
2792 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
2793 bxt_port_tx_dw3_read, NULL);
2794 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
2795 NULL, bxt_pcs_dw12_grp_write);
2796 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
2797 bxt_port_tx_dw3_read, NULL);
2798 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
2799 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
2800 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2801 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
2802 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2803 0, 0, D_BXT, NULL, NULL);
2804 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2805 0, 0, D_BXT, NULL, NULL);
2806 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2807 0, 0, D_BXT, NULL, NULL);
2808 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2809 0, 0, D_BXT, NULL, NULL);
2810
2811 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2812
2813 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
2814
2815 return 0;
2816 }
2817
find_mmio_block(struct intel_gvt * gvt,unsigned int offset)2818 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2819 unsigned int offset)
2820 {
2821 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2822 int num = gvt->mmio.num_mmio_block;
2823 int i;
2824
2825 for (i = 0; i < num; i++, block++) {
2826 if (offset >= i915_mmio_reg_offset(block->offset) &&
2827 offset < i915_mmio_reg_offset(block->offset) + block->size)
2828 return block;
2829 }
2830 return NULL;
2831 }
2832
2833 /**
2834 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2835 * @gvt: GVT device
2836 *
2837 * This function is called at the driver unloading stage, to clean up the MMIO
2838 * information table of GVT device
2839 *
2840 */
intel_gvt_clean_mmio_info(struct intel_gvt * gvt)2841 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2842 {
2843 struct hlist_node *tmp;
2844 struct intel_gvt_mmio_info *e;
2845 int i;
2846
2847 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2848 kfree(e);
2849
2850 kfree(gvt->mmio.mmio_block);
2851 gvt->mmio.mmio_block = NULL;
2852 gvt->mmio.num_mmio_block = 0;
2853
2854 vfree(gvt->mmio.mmio_attribute);
2855 gvt->mmio.mmio_attribute = NULL;
2856 }
2857
handle_mmio(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2858 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2859 u32 size)
2860 {
2861 struct intel_gvt *gvt = iter->data;
2862 struct intel_gvt_mmio_info *info, *p;
2863 u32 start, end, i;
2864
2865 if (WARN_ON(!IS_ALIGNED(offset, 4)))
2866 return -EINVAL;
2867
2868 start = offset;
2869 end = offset + size;
2870
2871 for (i = start; i < end; i += 4) {
2872 p = intel_gvt_find_mmio_info(gvt, i);
2873 if (p) {
2874 WARN(1, "dup mmio definition offset %x\n", i);
2875
2876 /* We return -EEXIST here to make GVT-g load fail.
2877 * So duplicated MMIO can be found as soon as
2878 * possible.
2879 */
2880 return -EEXIST;
2881 }
2882
2883 info = kzalloc(sizeof(*info), GFP_KERNEL);
2884 if (!info)
2885 return -ENOMEM;
2886
2887 info->offset = i;
2888 info->read = intel_vgpu_default_mmio_read;
2889 info->write = intel_vgpu_default_mmio_write;
2890 INIT_HLIST_NODE(&info->node);
2891 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
2892 gvt->mmio.num_tracked_mmio++;
2893 }
2894 return 0;
2895 }
2896
handle_mmio_block(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2897 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter,
2898 u32 offset, u32 size)
2899 {
2900 struct intel_gvt *gvt = iter->data;
2901 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2902 void *ret;
2903
2904 ret = krealloc(block,
2905 (gvt->mmio.num_mmio_block + 1) * sizeof(*block),
2906 GFP_KERNEL);
2907 if (!ret)
2908 return -ENOMEM;
2909
2910 gvt->mmio.mmio_block = block = ret;
2911
2912 block += gvt->mmio.num_mmio_block;
2913
2914 memset(block, 0, sizeof(*block));
2915
2916 block->offset = _MMIO(offset);
2917 block->size = size;
2918
2919 gvt->mmio.num_mmio_block++;
2920
2921 return 0;
2922 }
2923
handle_mmio_cb(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2924 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2925 u32 size)
2926 {
2927 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))
2928 return handle_mmio(iter, offset, size);
2929 else
2930 return handle_mmio_block(iter, offset, size);
2931 }
2932
init_mmio_info(struct intel_gvt * gvt)2933 static int init_mmio_info(struct intel_gvt *gvt)
2934 {
2935 struct intel_gvt_mmio_table_iter iter = {
2936 .i915 = gvt->gt->i915,
2937 .data = gvt,
2938 .handle_mmio_cb = handle_mmio_cb,
2939 };
2940
2941 return intel_gvt_iterate_mmio_table(&iter);
2942 }
2943
init_mmio_block_handlers(struct intel_gvt * gvt)2944 static int init_mmio_block_handlers(struct intel_gvt *gvt)
2945 {
2946 struct gvt_mmio_block *block;
2947
2948 block = find_mmio_block(gvt, VGT_PVINFO_PAGE);
2949 if (!block) {
2950 WARN(1, "fail to assign handlers to mmio block %x\n",
2951 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset));
2952 return -ENODEV;
2953 }
2954
2955 block->read = pvinfo_mmio_read;
2956 block->write = pvinfo_mmio_write;
2957
2958 return 0;
2959 }
2960
2961 /**
2962 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2963 * @gvt: GVT device
2964 *
2965 * This function is called at the initialization stage, to setup the MMIO
2966 * information table for GVT device
2967 *
2968 * Returns:
2969 * zero on success, negative if failed.
2970 */
intel_gvt_setup_mmio_info(struct intel_gvt * gvt)2971 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2972 {
2973 struct intel_gvt_device_info *info = &gvt->device_info;
2974 struct drm_i915_private *i915 = gvt->gt->i915;
2975 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2976 int ret;
2977
2978 gvt->mmio.mmio_attribute = vzalloc(size);
2979 if (!gvt->mmio.mmio_attribute)
2980 return -ENOMEM;
2981
2982 ret = init_mmio_info(gvt);
2983 if (ret)
2984 goto err;
2985
2986 ret = init_mmio_block_handlers(gvt);
2987 if (ret)
2988 goto err;
2989
2990 ret = init_generic_mmio_info(gvt);
2991 if (ret)
2992 goto err;
2993
2994 if (IS_BROADWELL(i915)) {
2995 ret = init_bdw_mmio_info(gvt);
2996 if (ret)
2997 goto err;
2998 } else if (IS_SKYLAKE(i915) ||
2999 IS_KABYLAKE(i915) ||
3000 IS_COFFEELAKE(i915) ||
3001 IS_COMETLAKE(i915)) {
3002 ret = init_bdw_mmio_info(gvt);
3003 if (ret)
3004 goto err;
3005 ret = init_skl_mmio_info(gvt);
3006 if (ret)
3007 goto err;
3008 } else if (IS_BROXTON(i915)) {
3009 ret = init_bdw_mmio_info(gvt);
3010 if (ret)
3011 goto err;
3012 ret = init_skl_mmio_info(gvt);
3013 if (ret)
3014 goto err;
3015 ret = init_bxt_mmio_info(gvt);
3016 if (ret)
3017 goto err;
3018 }
3019
3020 return 0;
3021 err:
3022 intel_gvt_clean_mmio_info(gvt);
3023 return ret;
3024 }
3025
3026 /**
3027 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3028 * @gvt: a GVT device
3029 * @handler: the handler
3030 * @data: private data given to handler
3031 *
3032 * Returns:
3033 * Zero on success, negative error code if failed.
3034 */
intel_gvt_for_each_tracked_mmio(struct intel_gvt * gvt,int (* handler)(struct intel_gvt * gvt,u32 offset,void * data),void * data)3035 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3036 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3037 void *data)
3038 {
3039 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3040 struct intel_gvt_mmio_info *e;
3041 int i, j, ret;
3042
3043 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3044 ret = handler(gvt, e->offset, data);
3045 if (ret)
3046 return ret;
3047 }
3048
3049 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3050 /* pvinfo data doesn't come from hw mmio */
3051 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3052 continue;
3053
3054 for (j = 0; j < block->size; j += 4) {
3055 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data);
3056 if (ret)
3057 return ret;
3058 }
3059 }
3060 return 0;
3061 }
3062
3063 /**
3064 * intel_vgpu_default_mmio_read - default MMIO read handler
3065 * @vgpu: a vGPU
3066 * @offset: access offset
3067 * @p_data: data return buffer
3068 * @bytes: access data length
3069 *
3070 * Returns:
3071 * Zero on success, negative error code if failed.
3072 */
intel_vgpu_default_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3073 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3074 void *p_data, unsigned int bytes)
3075 {
3076 read_vreg(vgpu, offset, p_data, bytes);
3077 return 0;
3078 }
3079
3080 /**
3081 * intel_vgpu_default_mmio_write() - default MMIO write handler
3082 * @vgpu: a vGPU
3083 * @offset: access offset
3084 * @p_data: write data buffer
3085 * @bytes: access data length
3086 *
3087 * Returns:
3088 * Zero on success, negative error code if failed.
3089 */
intel_vgpu_default_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3090 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3091 void *p_data, unsigned int bytes)
3092 {
3093 write_vreg(vgpu, offset, p_data, bytes);
3094 return 0;
3095 }
3096
3097 /**
3098 * intel_vgpu_mask_mmio_write - write mask register
3099 * @vgpu: a vGPU
3100 * @offset: access offset
3101 * @p_data: write data buffer
3102 * @bytes: access data length
3103 *
3104 * Returns:
3105 * Zero on success, negative error code if failed.
3106 */
intel_vgpu_mask_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3107 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3108 void *p_data, unsigned int bytes)
3109 {
3110 u32 mask, old_vreg;
3111
3112 old_vreg = vgpu_vreg(vgpu, offset);
3113 write_vreg(vgpu, offset, p_data, bytes);
3114 mask = vgpu_vreg(vgpu, offset) >> 16;
3115 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3116 (vgpu_vreg(vgpu, offset) & mask);
3117
3118 return 0;
3119 }
3120
3121 /**
3122 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3123 * force-nopriv register
3124 *
3125 * @gvt: a GVT device
3126 * @offset: register offset
3127 *
3128 * Returns:
3129 * True if the register is in force-nonpriv whitelist;
3130 * False if outside;
3131 */
intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt * gvt,unsigned int offset)3132 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3133 unsigned int offset)
3134 {
3135 return in_whitelist(offset);
3136 }
3137
3138 /**
3139 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3140 * @vgpu: a vGPU
3141 * @offset: register offset
3142 * @pdata: data buffer
3143 * @bytes: data length
3144 * @is_read: read or write
3145 *
3146 * Returns:
3147 * Zero on success, negative error code if failed.
3148 */
intel_vgpu_mmio_reg_rw(struct intel_vgpu * vgpu,unsigned int offset,void * pdata,unsigned int bytes,bool is_read)3149 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3150 void *pdata, unsigned int bytes, bool is_read)
3151 {
3152 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
3153 struct intel_gvt *gvt = vgpu->gvt;
3154 struct intel_gvt_mmio_info *mmio_info;
3155 struct gvt_mmio_block *mmio_block;
3156 gvt_mmio_func func;
3157 int ret;
3158
3159 if (drm_WARN_ON(&i915->drm, bytes > 8))
3160 return -EINVAL;
3161
3162 /*
3163 * Handle special MMIO blocks.
3164 */
3165 mmio_block = find_mmio_block(gvt, offset);
3166 if (mmio_block) {
3167 func = is_read ? mmio_block->read : mmio_block->write;
3168 if (func)
3169 return func(vgpu, offset, pdata, bytes);
3170 goto default_rw;
3171 }
3172
3173 /*
3174 * Normal tracked MMIOs.
3175 */
3176 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
3177 if (!mmio_info) {
3178 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3179 goto default_rw;
3180 }
3181
3182 if (is_read)
3183 return mmio_info->read(vgpu, offset, pdata, bytes);
3184 else {
3185 u64 ro_mask = mmio_info->ro_mask;
3186 u32 old_vreg = 0;
3187 u64 data = 0;
3188
3189 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3190 old_vreg = vgpu_vreg(vgpu, offset);
3191 }
3192
3193 if (likely(!ro_mask))
3194 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3195 else if (!~ro_mask) {
3196 gvt_vgpu_err("try to write RO reg %x\n", offset);
3197 return 0;
3198 } else {
3199 /* keep the RO bits in the virtual register */
3200 memcpy(&data, pdata, bytes);
3201 data &= ~ro_mask;
3202 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3203 ret = mmio_info->write(vgpu, offset, &data, bytes);
3204 }
3205
3206 /* higher 16bits of mode ctl regs are mask bits for change */
3207 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3208 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3209
3210 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3211 | (vgpu_vreg(vgpu, offset) & mask);
3212 }
3213 }
3214
3215 return ret;
3216
3217 default_rw:
3218 return is_read ?
3219 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3220 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3221 }
3222
intel_gvt_restore_fence(struct intel_gvt * gvt)3223 void intel_gvt_restore_fence(struct intel_gvt *gvt)
3224 {
3225 struct intel_vgpu *vgpu;
3226 int i, id;
3227
3228 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3229 mmio_hw_access_pre(gvt->gt);
3230 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3231 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
3232 mmio_hw_access_post(gvt->gt);
3233 }
3234 }
3235
mmio_pm_restore_handler(struct intel_gvt * gvt,u32 offset,void * data)3236 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data)
3237 {
3238 struct intel_vgpu *vgpu = data;
3239 struct drm_i915_private *dev_priv = gvt->gt->i915;
3240
3241 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
3242 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));
3243
3244 return 0;
3245 }
3246
intel_gvt_restore_mmio(struct intel_gvt * gvt)3247 void intel_gvt_restore_mmio(struct intel_gvt *gvt)
3248 {
3249 struct intel_vgpu *vgpu;
3250 int id;
3251
3252 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3253 mmio_hw_access_pre(gvt->gt);
3254 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
3255 mmio_hw_access_post(gvt->gt);
3256 }
3257 }
3258