1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_VMAC_HW_H 27 #define _HXGE_VMAC_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define VMAC_BASE_ADDR 0X00100000 34 35 #define VMAC_RST (VMAC_BASE_ADDR + 0x0) 36 #define VMAC_TX_CFG (VMAC_BASE_ADDR + 0x8) 37 #define VMAC_RX_CFG (VMAC_BASE_ADDR + 0x10) 38 #define VMAC_TX_STAT (VMAC_BASE_ADDR + 0x20) 39 #define VMAC_TX_MSK (VMAC_BASE_ADDR + 0x28) 40 #define VMAC_RX_STAT (VMAC_BASE_ADDR + 0x30) 41 #define VMAC_RX_MSK (VMAC_BASE_ADDR + 0x38) 42 #define VMAC_TX_STAT_MIRROR (VMAC_BASE_ADDR + 0x40) 43 #define VMAC_RX_STAT_MIRROR (VMAC_BASE_ADDR + 0x48) 44 #define VMAC_TX_FRAME_CNT (VMAC_BASE_ADDR + 0x100) 45 #define VMAC_TX_BYTE_CNT (VMAC_BASE_ADDR + 0x108) 46 #define VMAC_RX_FRAME_CNT (VMAC_BASE_ADDR + 0x120) 47 #define VMAC_RX_BYTE_CNT (VMAC_BASE_ADDR + 0x128) 48 #define VMAC_RX_DROP_FR_CNT (VMAC_BASE_ADDR + 0x130) 49 #define VMAC_RX_DROP_BYTE_CNT (VMAC_BASE_ADDR + 0x138) 50 #define VMAC_RX_CRC_CNT (VMAC_BASE_ADDR + 0x140) 51 #define VMAC_RX_PAUSE_CNT (VMAC_BASE_ADDR + 0x148) 52 #define VMAC_RX_BCAST_FR_CNT (VMAC_BASE_ADDR + 0x150) 53 #define VMAC_RX_MCAST_FR_CNT (VMAC_BASE_ADDR + 0x158) 54 55 56 /* 57 * Register: VmacRst 58 * VMAC Software Reset Command 59 * Description: 60 * Fields: 61 * Write a '1' to reset Rx VMAC; auto clears. This brings rx vmac 62 * to power on reset state. 63 * Write a '1' to reset Tx VMAC; auto clears. This brings tx vmac 64 * to power on reset state. 65 */ 66 typedef union { 67 uint64_t value; 68 struct { 69 #if defined(_BIG_ENDIAN) 70 uint32_t rsrvd:32; 71 uint32_t rsrvd_l:23; 72 uint32_t rx_reset:1; 73 uint32_t rsrvd1:7; 74 uint32_t tx_reset:1; 75 #else 76 uint32_t tx_reset:1; 77 uint32_t rsrvd1:7; 78 uint32_t rx_reset:1; 79 uint32_t rsrvd_l:23; 80 uint32_t rsrvd:32; 81 #endif 82 } bits; 83 } vmac_rst_t; 84 85 86 /* 87 * Register: VmacTxCfg 88 * Tx VMAC Configuration 89 * Description: 90 * Fields: 91 * Maximum length of any total transfer gathered by Tx VMAC, 92 * including packet data, header, crc, transmit header and any 93 * pad bytes. Default value of 0x2422 represents 9220 bytes of 94 * packet data, ethernet header, and crc, 14 bytes maximum pad, 95 * and 16 bytes transmit header = 9250 (0x2422). 96 * Enable padding of short packet to meet minimum frame length of 97 * 64 bytes. Software should note that if txPad functionality is 98 * used to pad runt packets to minimum length, that crcInsert 99 * functionality (below) must also be used to provide the packet 100 * with correct L2 crc. 101 * 1: Enable generation and appending of FCS to the packets. 0: 102 * Disable generation and appending of FCS to the packets. 103 * Enable Tx VMAC. Write a '1' to enable Tx VMAC; write a '0' to 104 * disable it. This bit also propagates as vmacTdcEn to the TDC 105 * block. In TDC, the vmacTdcEn bit disables the RTab state 106 * machine. Hence, the transmission from that blade would be 107 * stopped and be queued, but no packets would be dropped. Thus, 108 * the VMAC can only be enabled/disabled at packet boundary. The 109 * VMAC will not send out portion of a packet. The currently 110 * processed packet will continue to be sent out when Tx VMAC is 111 * disabled. 112 */ 113 typedef union { 114 uint64_t value; 115 struct { 116 #if defined(_BIG_ENDIAN) 117 uint32_t rsrvd:32; 118 uint32_t tx_max_frame_length:14; 119 uint32_t rsrvd1:15; 120 uint32_t tx_pad:1; 121 uint32_t crc_insert:1; 122 uint32_t tx_en:1; 123 #else 124 uint32_t tx_en:1; 125 uint32_t crc_insert:1; 126 uint32_t tx_pad:1; 127 uint32_t rsrvd1:15; 128 uint32_t tx_max_frame_length:14; 129 uint32_t rsrvd:32; 130 #endif 131 } bits; 132 } vmac_tx_cfg_t; 133 134 135 /* 136 * Register: VmacRxCfg 137 * Rx VMAC Configuration 138 * Description: MAC address and length in Type/Length field are 139 * checked in PFC. 140 * Fields: 141 * Maximum length of a frame accepted by Rx/Tx VMAC. Only packets 142 * with length between 64 bytes and maxFrameLength will be 143 * accepted by Rx/Tx VMAC. This length indicates just the packet 144 * length excluding the packet header, crc, and any pad bytes. 145 * Maximum value is 9K (9*1024) 146 * enable packets from the same blade to loopback 147 * Enable acceptance of all Unicast packets for L2 destination 148 * address, ie, allow all Unicast packets to pass the L2 149 * filtering. 150 * Enable acceptance of all multi-cast packets, ie, allow all 151 * multi-cast packets to pass the L2 filtering. 152 * Enable the passing through of flow control frames. 153 * Enable the stripping of FCS field in the packets. 154 * Disable of FCS checking. When enable, packets with incorrect 155 * FCS value are dropped by Rx VMAC. 156 * Enable rx VMAC. Write a '1' to enable rx VMAC; write a '0' to 157 * disable it. The VMAC will begin to accept packet at the 158 * detection of the SOP (start of packet). When disable, the 159 * currently processed packet will continue to be accepted. 160 */ 161 typedef union { 162 uint64_t value; 163 struct { 164 #if defined(_BIG_ENDIAN) 165 uint32_t rsrvd:32; 166 uint32_t rx_max_frame_length:14; 167 uint32_t reserved:11; 168 uint32_t loopback:1; 169 uint32_t promiscuous_mode:1; 170 uint32_t promiscuous_group:1; 171 uint32_t pass_flow_ctrl_fr:1; 172 uint32_t strip_crc:1; 173 uint32_t crc_check_disable:1; 174 uint32_t rx_en:1; 175 #else 176 uint32_t rx_en:1; 177 uint32_t crc_check_disable:1; 178 uint32_t strip_crc:1; 179 uint32_t pass_flow_ctrl_fr:1; 180 uint32_t promiscuous_group:1; 181 uint32_t promiscuous_mode:1; 182 uint32_t loopback:1; 183 uint32_t reserved:11; 184 uint32_t rx_max_frame_length:14; 185 uint32_t rsrvd:32; 186 #endif 187 } bits; 188 } vmac_rx_cfg_t; 189 190 191 /* 192 * Register: VmacTxStat 193 * Tx VMAC Status Register 194 * Description: A new interrupt will be generated only if Tx VMAC is 195 * enabled by vmacTxCfg::txEn=1. Disabling Tx VMAC does not affect 196 * currently-existing Ldf state. Writing this register affects 197 * vmacTxStatMirror register bits also the same way. 198 * Fields: 199 * Indicates that counter of byte transmitted has exceeded the 200 * max value. 201 * Indicates that counter of frame transmitted has exceeded the 202 * max value. 203 * A frame has been successfully transmitted. 204 */ 205 typedef union { 206 uint64_t value; 207 struct { 208 #if defined(_BIG_ENDIAN) 209 uint32_t rsrvd:32; 210 uint32_t rsrvd_l:29; 211 uint32_t tx_byte_cnt_overflow:1; 212 uint32_t tx_frame_cnt_overflow:1; 213 uint32_t frame_tx:1; 214 #else 215 uint32_t frame_tx:1; 216 uint32_t tx_frame_cnt_overflow:1; 217 uint32_t tx_byte_cnt_overflow:1; 218 uint32_t rsrvd_l:29; 219 uint32_t rsrvd:32; 220 #endif 221 } bits; 222 } vmac_tx_stat_t; 223 224 225 /* 226 * Register: VmacTxMsk 227 * Tx VMAC Status Mask 228 * Description: masking vmacTxStat from interrupt. 229 * Fields: 230 * 1: mask interrupt due to overflow of counter of byte 231 * transmitted 232 * 1: mask interrupt due to overflow of counter of frame 233 * transmitted 234 * 1: mask interrupt due to successful transmition of frame. 235 */ 236 typedef union { 237 uint64_t value; 238 struct { 239 #if defined(_BIG_ENDIAN) 240 uint32_t rsrvd:32; 241 uint32_t rsrvd_l:29; 242 uint32_t tx_byte_cnt_overflow_msk:1; 243 uint32_t tx_frame_cnt_overflow_msk:1; 244 uint32_t frame_tx_msk:1; 245 #else 246 uint32_t frame_tx_msk:1; 247 uint32_t tx_frame_cnt_overflow_msk:1; 248 uint32_t tx_byte_cnt_overflow_msk:1; 249 uint32_t rsrvd_l:29; 250 uint32_t rsrvd:32; 251 #endif 252 } bits; 253 } vmac_tx_msk_t; 254 255 256 /* 257 * Register: VmacRxStat 258 * Rx VMAC Status Register 259 * Description: Overflow indicators are read-only registers; Read off 260 * the counters to clear. A new interrupt will be generated only if 261 * Rx VMAC is enabled by vmacRxCfg::rxEn=1. Disabling Rx VMAC does 262 * not affect currently-existing Ldf state. Writing this register 263 * affects vmacRxStatMirror register bits also the same way. 264 * Fields: 265 * Indicates that the counter for broadcast packets has exceeded 266 * the max value. 267 * Indicates that the counter for multicast packets has exceeded 268 * the max value. 269 * Indicates that the counter for pause packets has exceeded the 270 * max value. 271 * Indicates that the counter for packets with mismatched FCS has 272 * exceeded the max value. 273 * Indicates that counter of dropped byte has exceeded the max 274 * value. 275 * Indicates that counter of dropped frame has exceeded the max 276 * value. 277 * Indicates that counter of byte received has exceeded the max 278 * value. 279 * Indicates that counter of frame received has exceeded the max 280 * value. 281 * A valid frame has been successfully received. 282 */ 283 typedef union { 284 uint64_t value; 285 struct { 286 #if defined(_BIG_ENDIAN) 287 uint32_t rsrvd:32; 288 uint32_t rsrvd_l:23; 289 uint32_t bcast_cnt_overflow:1; 290 uint32_t mcast_cnt_overflow:1; 291 uint32_t pause_cnt_overflow:1; 292 uint32_t crc_err_cnt_overflow:1; 293 uint32_t rx_drop_byte_cnt_overflow:1; 294 uint32_t rx_drop_frame_cnt_overflow:1; 295 uint32_t rx_byte_cnt_overflow:1; 296 uint32_t rx_frame_cnt_overflow:1; 297 uint32_t frame_rx:1; 298 #else 299 uint32_t frame_rx:1; 300 uint32_t rx_frame_cnt_overflow:1; 301 uint32_t rx_byte_cnt_overflow:1; 302 uint32_t rx_drop_frame_cnt_overflow:1; 303 uint32_t rx_drop_byte_cnt_overflow:1; 304 uint32_t crc_err_cnt_overflow:1; 305 uint32_t pause_cnt_overflow:1; 306 uint32_t mcast_cnt_overflow:1; 307 uint32_t bcast_cnt_overflow:1; 308 uint32_t rsrvd_l:23; 309 uint32_t rsrvd:32; 310 #endif 311 } bits; 312 } vmac_rx_stat_t; 313 314 315 /* 316 * Register: VmacRxMsk 317 * Rx VMAC Status Mask 318 * Description: 319 * Fields: 320 * 1: mask interrupt due to overflow of the counter for broadcast 321 * packets 322 * 1: mask interrupt due to overflow of the counter for multicast 323 * packets 324 * 1: mask interrupt due to overflow of the counter for pause 325 * packets 326 * 1: mask interrupt due to overflow of the counter for packets 327 * with mismatched FCS the max value. 328 * 1: mask interrupt due to overflow of dropped byte counter 329 * 1: mask interrupt due to overflow of dropped frame counter 330 * 1: mask interrupt due to overflow of received byte counter 331 * 1: mask interrupt due to overflow of received frame counter 332 * 1: mask interrupt due to a valid frame has been successfully 333 * received. 334 */ 335 typedef union { 336 uint64_t value; 337 struct { 338 #if defined(_BIG_ENDIAN) 339 uint32_t rsrvd:32; 340 uint32_t rsrvd_l:23; 341 uint32_t bcast_cnt_overflow_msk:1; 342 uint32_t mcast_cnt_overflow_msk:1; 343 uint32_t pause_cnt_overflow_msk:1; 344 uint32_t crc_err_cnt_overflow_msk:1; 345 uint32_t rx_drop_byte_cnt_overflow_msk:1; 346 uint32_t rx_drop_frame_cnt_overflow_msk:1; 347 uint32_t rx_byte_cnt_overflow_msk:1; 348 uint32_t rx_frame_cnt_overflow_msk:1; 349 uint32_t frame_rx_msk:1; 350 #else 351 uint32_t frame_rx_msk:1; 352 uint32_t rx_frame_cnt_overflow_msk:1; 353 uint32_t rx_byte_cnt_overflow_msk:1; 354 uint32_t rx_drop_frame_cnt_overflow_msk:1; 355 uint32_t rx_drop_byte_cnt_overflow_msk:1; 356 uint32_t crc_err_cnt_overflow_msk:1; 357 uint32_t pause_cnt_overflow_msk:1; 358 uint32_t mcast_cnt_overflow_msk:1; 359 uint32_t bcast_cnt_overflow_msk:1; 360 uint32_t rsrvd_l:23; 361 uint32_t rsrvd:32; 362 #endif 363 } bits; 364 } vmac_rx_msk_t; 365 366 367 /* 368 * Register: VmacTxStatMirror 369 * Tx VMAC Status Mirror Register 370 * Description: Write a 1 to this register to force the corresponding 371 * interrupt. Reading this register returns the current Tx interrupt 372 * status which would be the same as reading the vmacTxStat register. 373 * The bits are cleared by writing 1 to the corresponding register 374 * bit in the vmacTxStat register. ie, bit 0 of this register is 375 * cleared by writing 1 to bit 0 in the vmacTxStat register. 376 * 377 * Fields: 378 * 1 : Force tx byte counter overflow interrupt generation 379 * 1 : Force tx frame counter overflow interrupt generation 380 * 1 : Force frame transmitted interrupt generation 381 */ 382 typedef union { 383 uint64_t value; 384 struct { 385 #if defined(_BIG_ENDIAN) 386 uint32_t rsrvd:32; 387 uint32_t rsrvd_l:29; 388 uint32_t force_tx_byte_cnt_overflow:1; 389 uint32_t force_tx_frame_cnt_overflow:1; 390 uint32_t force_frame_tx:1; 391 #else 392 uint32_t force_frame_tx:1; 393 uint32_t force_tx_frame_cnt_overflow:1; 394 uint32_t force_tx_byte_cnt_overflow:1; 395 uint32_t rsrvd_l:29; 396 uint32_t rsrvd:32; 397 #endif 398 } bits; 399 } vmac_tx_stat_mirror_t; 400 401 402 /* 403 * Register: VmacRxStatMirror 404 * Rx VMAC Status Mirror Register 405 * Description: Write a 1 to this register to force the corresponding 406 * interrupt. Reading this register returns the current Rx interrupt 407 * status which would be the same as reading the vmacRxStat register. 408 * The bits are cleared by writing 1 to the corresponding register 409 * bit in the vmacRxStat register. ie, bit 0 of this register is 410 * cleared by writing 1 to bit 0 in the vmacRxStat register. 411 * Fields: 412 * 1 : Force broadcast frame counter overflow interrupt 413 * generation 414 * 1 : Force multicast frame counter overflow interrupt 415 * generation 416 * 1 : Force pause frame counter overflow interrupt generation 417 * 1 : Force crc error counter overflow interrupt generation 418 * 1 : Force dropped frames byte counter overflow interrupt 419 * generation 420 * 1 : Force dropped frame counter overflow interrupt generation 421 * 1 : Force rx byte counter overflow interrupt generation 422 * 1 : Force rx frame counter overflow interrupt generation 423 * 1 : Force frame received interrupt generation 424 */ 425 typedef union { 426 uint64_t value; 427 struct { 428 #if defined(_BIG_ENDIAN) 429 uint32_t rsrvd:32; 430 uint32_t rsrvd_l:23; 431 uint32_t force_bcast_cnt_overflow:1; 432 uint32_t force_mcast_cnt_overflow:1; 433 uint32_t force_pause_cnt_overflow:1; 434 uint32_t force_crc_err_cnt_overflow:1; 435 uint32_t force_rx_drop_byte_cnt_overflow:1; 436 uint32_t force_rx_drop_frame_cnt_overflow:1; 437 uint32_t force_rx_byte_cnt_overflow:1; 438 uint32_t force_rx_frame_cnt_overflow:1; 439 uint32_t force_frame_rx:1; 440 #else 441 uint32_t force_frame_rx:1; 442 uint32_t force_rx_frame_cnt_overflow:1; 443 uint32_t force_rx_byte_cnt_overflow:1; 444 uint32_t force_rx_drop_frame_cnt_overflow:1; 445 uint32_t force_rx_drop_byte_cnt_overflow:1; 446 uint32_t force_crc_err_cnt_overflow:1; 447 uint32_t force_pause_cnt_overflow:1; 448 uint32_t force_mcast_cnt_overflow:1; 449 uint32_t force_bcast_cnt_overflow:1; 450 uint32_t rsrvd_l:23; 451 uint32_t rsrvd:32; 452 #endif 453 } bits; 454 } vmac_rx_stat_mirror_t; 455 456 457 /* 458 * Register: VmacTxFrameCnt 459 * VMAC transmitted frame counter 460 * Description: 461 * Fields: 462 * Indicates the number of frames transmitted by Tx VMAC. The 463 * counter will saturate at max value. The counter is stalled 464 * when Tx VMAC is disabled by vmacTxCfg::txEn=0 465 */ 466 typedef union { 467 uint64_t value; 468 struct { 469 #if defined(_BIG_ENDIAN) 470 uint32_t rsrvd:32; 471 uint32_t tx_frame_cnt:32; 472 #else 473 uint32_t tx_frame_cnt:32; 474 uint32_t rsrvd:32; 475 #endif 476 } bits; 477 } vmac_tx_frame_cnt_t; 478 479 480 /* 481 * Register: VmacTxByteCnt 482 * VMAC transmitted byte counter 483 * Description: 484 * Fields: 485 * Indicates the number of byte (octet) of data transmitted by Tx 486 * VMAC. This counter counts all the bytes of the incoming data 487 * including packet header, packet data, crc, and pad bytes. The 488 * counter will saturate at max value. The counter is stalled 489 * when Tx VMAC is disabled by vmacTxCfg::txEn=0 490 */ 491 typedef union { 492 uint64_t value; 493 struct { 494 #if defined(_BIG_ENDIAN) 495 uint32_t rsrvd:32; 496 uint32_t tx_byte_cnt:32; 497 #else 498 uint32_t tx_byte_cnt:32; 499 uint32_t rsrvd:32; 500 #endif 501 } bits; 502 } vmac_tx_byte_cnt_t; 503 504 505 /* 506 * Register: VmacRxFrameCnt 507 * VMAC received frame counter 508 * Description: 509 * Fields: 510 * Indicates the number of frame received by Rx VMAC. The counter 511 * will saturate at max value. The counter is stalled when Rx 512 * VMAC is disabled by vmacRxCfg::rxEn=0. 513 */ 514 typedef union { 515 uint64_t value; 516 struct { 517 #if defined(_BIG_ENDIAN) 518 uint32_t rsrvd:32; 519 uint32_t rx_frame_cnt:32; 520 #else 521 uint32_t rx_frame_cnt:32; 522 uint32_t rsrvd:32; 523 #endif 524 } bits; 525 } vmac_rx_frame_cnt_t; 526 527 528 /* 529 * Register: VmacRxByteCnt 530 * VMAC received byte counter 531 * Description: 532 * Fields: 533 * Indicates the number of bytes (octet) of data received by Rx 534 * VMAC including any error frames. The counter will saturate at 535 * max value. The counter is stalled when Rx VMAC is disabled by 536 * vmacRxCfg::rxEn=0. 537 */ 538 typedef union { 539 uint64_t value; 540 struct { 541 #if defined(_BIG_ENDIAN) 542 uint32_t rsrvd:32; 543 uint32_t rx_byte_cnt:32; 544 #else 545 uint32_t rx_byte_cnt:32; 546 uint32_t rsrvd:32; 547 #endif 548 } bits; 549 } vmac_rx_byte_cnt_t; 550 551 552 /* 553 * Register: VmacRxDropFrCnt 554 * VMAC dropped frame counter 555 * Description: 556 * Fields: 557 * Indicates the number of frame dropped by Rx VMAC. The counter 558 * will This counter increments for every frame dropped for the 559 * following: - crc mismatch & crc check is enabled - failed the 560 * L2 address match & Vmac is not in promiscuous mode - pause 561 * packet & Vmac is not programmed to pass these frames The 562 * counter will saturate at max value. The counter is stalled 563 * when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 564 */ 565 typedef union { 566 uint64_t value; 567 struct { 568 #if defined(_BIG_ENDIAN) 569 uint32_t rsrvd:32; 570 uint32_t rx_drop_frame_cnt:32; 571 #else 572 uint32_t rx_drop_frame_cnt:32; 573 uint32_t rsrvd:32; 574 #endif 575 } bits; 576 } vmac_rx_drop_fr_cnt_t; 577 578 579 /* 580 * Register: VmacRxDropByteCnt 581 * VMAC dropped byte counter 582 * Description: 583 * Fields: 584 * Indicates the number of byte of data dropped by Rx VMAC. 585 * Frames are dropped for one of the follg conditions : - crc 586 * mismatch & crc check is enabled - failed the L2 address match 587 * & Vmac is not in promiscuous mode - pause packet & Vmac is not 588 * programmed to pass these frames The counter will saturate at 589 * max value. The counter is stalled when Rx VMAC is disabled by 590 * vmacRxCfg::rxEn=0. 591 */ 592 typedef union { 593 uint64_t value; 594 struct { 595 #if defined(_BIG_ENDIAN) 596 uint32_t rsrvd:32; 597 uint32_t rx_drop_byte_cnt:32; 598 #else 599 uint32_t rx_drop_byte_cnt:32; 600 uint32_t rsrvd:32; 601 #endif 602 } bits; 603 } vmac_rx_drop_byte_cnt_t; 604 605 606 /* 607 * Register: VmacRxCrcCnt 608 * VMAC received CRC error frame counter 609 * Description: 610 * Fields: 611 * Indicates the number of frames with invalid CRC. When NMAC 612 * truncates a packet, it asserts crcError indication to VMAC 613 * which then counts it towards CRC error. Thus the VMAC crc 614 * error counter reflects the CRC mismatches on all the packets 615 * going out of RxMAC while the NMAC crc error counter reflects 616 * the CRC mismatches on all the packets coming into RxMAC. The 617 * counter will saturate at max value The counter is stalled when 618 * Rx VMAC is disabled by vmacRxCfg::rxEn=0. 619 */ 620 typedef union { 621 uint64_t value; 622 struct { 623 #if defined(_BIG_ENDIAN) 624 uint32_t rsrvd:32; 625 uint32_t rx_crc_cnt:32; 626 #else 627 uint32_t rx_crc_cnt:32; 628 uint32_t rsrvd:32; 629 #endif 630 } bits; 631 } vmac_rx_crc_cnt_t; 632 633 634 /* 635 * Register: VmacRxPauseCnt 636 * VMAC received pause frame counter 637 * Description: 638 * Fields: 639 * Count the number of pause frames received by Rx VMAC. The 640 * counter is stalled when Rx VMAC is disabled by 641 * vmacRxCfg::rxEn=0. 642 */ 643 typedef union { 644 uint64_t value; 645 struct { 646 #if defined(_BIG_ENDIAN) 647 uint32_t rsrvd:32; 648 uint32_t rx_pause_cnt:32; 649 #else 650 uint32_t rx_pause_cnt:32; 651 uint32_t rsrvd:32; 652 #endif 653 } bits; 654 } vmac_rx_pause_cnt_t; 655 656 657 /* 658 * Register: VmacRxBcastFrCnt 659 * VMAC received broadcast frame counter 660 * Description: 661 * Fields: 662 * Indicates the number of broadcast frames received The counter 663 * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 664 */ 665 typedef union { 666 uint64_t value; 667 struct { 668 #if defined(_BIG_ENDIAN) 669 uint32_t rsrvd:32; 670 uint32_t rx_bcast_fr_cnt:32; 671 #else 672 uint32_t rx_bcast_fr_cnt:32; 673 uint32_t rsrvd:32; 674 #endif 675 } bits; 676 } vmac_rx_bcast_fr_cnt_t; 677 678 679 /* 680 * Register: VmacRxMcastFrCnt 681 * VMAC received multicast frame counter 682 * Description: 683 * Fields: 684 * Indicates the number of multicast frames received The counter 685 * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 686 */ 687 typedef union { 688 uint64_t value; 689 struct { 690 #if defined(_BIG_ENDIAN) 691 uint32_t rsrvd:32; 692 uint32_t rx_mcast_fr_cnt:32; 693 #else 694 uint32_t rx_mcast_fr_cnt:32; 695 uint32_t rsrvd:32; 696 #endif 697 } bits; 698 } vmac_rx_mcast_fr_cnt_t; 699 700 701 #ifdef __cplusplus 702 } 703 #endif 704 705 #endif /* _HXGE_VMAC_HW_H */ 706