1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dml1_display_rq_dlg_calc.h" 27 #include "display_mode_lib.h" 28 29 #include "dml_inline_defs.h" 30 31 /* 32 * NOTE: 33 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 34 * 35 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 36 * ways. Unless there is something clearly wrong with it the code should 37 * remain as-is as it provides us with a guarantee from HW that it is correct. 38 */ 39 40 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 41 { 42 unsigned int ret_val = 1; 43 44 if (source_format == dm_444_16) { 45 if (!is_chroma) 46 ret_val = 2; 47 } else if (source_format == dm_444_32) { 48 if (!is_chroma) 49 ret_val = 4; 50 } else if (source_format == dm_444_64) { 51 if (!is_chroma) 52 ret_val = 8; 53 } else if (source_format == dm_420_8) { 54 if (is_chroma) 55 ret_val = 2; 56 else 57 ret_val = 1; 58 } else if (source_format == dm_420_10) { 59 if (is_chroma) 60 ret_val = 4; 61 else 62 ret_val = 2; 63 } 64 return ret_val; 65 } 66 67 static bool is_dual_plane(enum source_format_class source_format) 68 { 69 bool ret_val = 0; 70 71 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 72 ret_val = 1; 73 74 return ret_val; 75 } 76 77 static void get_blk256_size( 78 unsigned int *blk256_width, 79 unsigned int *blk256_height, 80 unsigned int bytes_per_element) 81 { 82 if (bytes_per_element == 1) { 83 *blk256_width = 16; 84 *blk256_height = 16; 85 } else if (bytes_per_element == 2) { 86 *blk256_width = 16; 87 *blk256_height = 8; 88 } else if (bytes_per_element == 4) { 89 *blk256_width = 8; 90 *blk256_height = 8; 91 } else if (bytes_per_element == 8) { 92 *blk256_width = 8; 93 *blk256_height = 4; 94 } 95 } 96 97 static double get_refcyc_per_delivery( 98 struct display_mode_lib *mode_lib, 99 double refclk_freq_in_mhz, 100 double pclk_freq_in_mhz, 101 unsigned int recout_width, 102 double vratio, 103 double hscale_pixel_rate, 104 unsigned int delivery_width, 105 unsigned int req_per_swath_ub) 106 { 107 (void)mode_lib; 108 double refcyc_per_delivery = 0.0; 109 110 if (vratio <= 1.0) { 111 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 112 / pclk_freq_in_mhz / (double) req_per_swath_ub; 113 } else { 114 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 115 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 116 } 117 118 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz); 119 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz); 120 DTRACE("DLG: %s: recout_width = %d", __func__, recout_width); 121 DTRACE("DLG: %s: vratio = %3.2f", __func__, vratio); 122 DTRACE("DLG: %s: req_per_swath_ub = %d", __func__, req_per_swath_ub); 123 DTRACE("DLG: %s: refcyc_per_delivery= %3.2f", __func__, refcyc_per_delivery); 124 125 return refcyc_per_delivery; 126 127 } 128 129 static double get_vratio_pre( 130 struct display_mode_lib *mode_lib, 131 unsigned int max_num_sw, 132 unsigned int max_partial_sw, 133 unsigned int swath_height, 134 double vinit, 135 double l_sw) 136 { 137 (void)mode_lib; 138 double prefill = dml_floor(vinit, 1); 139 double vratio_pre = 1.0; 140 141 vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw; 142 143 if (swath_height > 4) { 144 double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0); 145 146 if (tmp0 > vratio_pre) 147 vratio_pre = tmp0; 148 } 149 150 DTRACE("DLG: %s: max_num_sw = %0d", __func__, max_num_sw); 151 DTRACE("DLG: %s: max_partial_sw = %0d", __func__, max_partial_sw); 152 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height); 153 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit); 154 DTRACE("DLG: %s: vratio_pre = %3.2f", __func__, vratio_pre); 155 156 if (vratio_pre < 1.0) { 157 DTRACE("WARNING_DLG: %s: vratio_pre=%3.2f < 1.0, set to 1.0", __func__, vratio_pre); 158 vratio_pre = 1.0; 159 } 160 161 if (vratio_pre > 4.0) { 162 DTRACE( 163 "WARNING_DLG: %s: vratio_pre=%3.2f > 4.0 (max scaling ratio). set to 4.0", 164 __func__, 165 vratio_pre); 166 vratio_pre = 4.0; 167 } 168 169 return vratio_pre; 170 } 171 172 static void get_swath_need( 173 struct display_mode_lib *mode_lib, 174 unsigned int *max_num_sw, 175 unsigned int *max_partial_sw, 176 unsigned int swath_height, 177 double vinit) 178 { 179 (void)mode_lib; 180 double prefill = dml_floor(vinit, 1); 181 unsigned int max_partial_sw_int; 182 183 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height); 184 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit); 185 186 ASSERT(prefill > 0.0 && prefill <= 8.0); 187 188 *max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 */ 189 max_partial_sw_int = 190 (prefill == 1) ? 191 (swath_height - 1) : 192 ((unsigned int) (prefill - 2.0) % swath_height); 193 *max_partial_sw = (max_partial_sw_int < 1) ? 1 : max_partial_sw_int; /* ensure minimum of 1 is used */ 194 195 DTRACE("DLG: %s: max_num_sw = %0d", __func__, *max_num_sw); 196 DTRACE("DLG: %s: max_partial_sw = %0d", __func__, *max_partial_sw); 197 } 198 199 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 200 { 201 if (tile_size == dm_256k_tile) 202 return (256 * 1024); 203 else if (tile_size == dm_64k_tile) 204 return (64 * 1024); 205 else 206 return (4 * 1024); 207 } 208 209 static void extract_rq_sizing_regs( 210 struct display_mode_lib *mode_lib, 211 struct _vcs_dpi_display_data_rq_regs_st *rq_regs, 212 const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing) 213 { 214 DTRACE("DLG: %s: rq_sizing param", __func__); 215 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 216 217 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; 218 219 if (rq_sizing->min_chunk_bytes == 0) 220 rq_regs->min_chunk_size = 0; 221 else 222 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; 223 224 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; 225 if (rq_sizing->min_meta_chunk_bytes == 0) 226 rq_regs->min_meta_chunk_size = 0; 227 else 228 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; 229 230 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; 231 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; 232 } 233 234 void dml1_extract_rq_regs( 235 struct display_mode_lib *mode_lib, 236 struct _vcs_dpi_display_rq_regs_st *rq_regs, 237 const struct _vcs_dpi_display_rq_params_st *rq_param) 238 { 239 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 240 unsigned int detile_buf_plane1_addr = 0; 241 242 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 243 if (rq_param->yuv420) 244 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 245 246 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 247 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 248 249 /* TODO: take the max between luma, chroma chunk size? 250 * okay for now, as we are setting chunk_bytes to 8kb anyways 251 */ 252 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */ 253 rq_regs->drq_expansion_mode = 0; 254 } else { 255 rq_regs->drq_expansion_mode = 2; 256 } 257 rq_regs->prq_expansion_mode = 1; 258 rq_regs->mrq_expansion_mode = 1; 259 rq_regs->crq_expansion_mode = 1; 260 261 if (rq_param->yuv420) { 262 if ((double) rq_param->misc.rq_l.stored_swath_bytes 263 / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 264 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */ 265 } else { 266 detile_buf_plane1_addr = dml_round_to_multiple( 267 (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 268 256, 269 0) / 64.0; /* 2/3 to chroma */ 270 } 271 } 272 rq_regs->plane1_base_address = detile_buf_plane1_addr; 273 } 274 275 static void handle_det_buf_split( 276 struct display_mode_lib *mode_lib, 277 struct _vcs_dpi_display_rq_params_st *rq_param, 278 const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param) 279 { 280 unsigned int total_swath_bytes = 0; 281 unsigned int swath_bytes_l = 0; 282 unsigned int swath_bytes_c = 0; 283 unsigned int full_swath_bytes_packed_l = 0; 284 unsigned int full_swath_bytes_packed_c = 0; 285 bool req128_l = 0; 286 bool req128_c = 0; 287 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 288 bool surf_vert = (pipe_src_param->source_scan == dm_vert); 289 unsigned int log2_swath_height_l = 0; 290 unsigned int log2_swath_height_c = 0; 291 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 292 293 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 294 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 295 296 if (rq_param->yuv420_10bpc) { 297 full_swath_bytes_packed_l = dml_round_to_multiple( 298 rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 299 256, 300 1) + 256; 301 full_swath_bytes_packed_c = dml_round_to_multiple( 302 rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 303 256, 304 1) + 256; 305 } 306 307 if (rq_param->yuv420) { 308 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 309 310 if (total_swath_bytes <= detile_buf_size_in_bytes) { /*full 256b request */ 311 req128_l = 0; 312 req128_c = 0; 313 swath_bytes_l = full_swath_bytes_packed_l; 314 swath_bytes_c = full_swath_bytes_packed_c; 315 } else { /*128b request (for luma only for yuv420 8bpc) */ 316 req128_l = 1; 317 req128_c = 0; 318 swath_bytes_l = full_swath_bytes_packed_l / 2; 319 swath_bytes_c = full_swath_bytes_packed_c; 320 } 321 322 /* Bug workaround, luma and chroma req size needs to be the same. (see: DEGVIDCN10-137) 323 * TODO: Remove after rtl fix 324 */ 325 if (req128_l == 1) { 326 req128_c = 1; 327 DTRACE("DLG: %s: bug workaround DEGVIDCN10-137", __func__); 328 } 329 330 /* Note: assumption, the config that pass in will fit into 331 * the detiled buffer. 332 */ 333 } else { 334 total_swath_bytes = 2 * full_swath_bytes_packed_l; 335 336 if (total_swath_bytes <= detile_buf_size_in_bytes) 337 req128_l = 0; 338 else 339 req128_l = 1; 340 341 swath_bytes_l = total_swath_bytes; 342 swath_bytes_c = 0; 343 } 344 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 345 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 346 347 if (surf_linear) { 348 log2_swath_height_l = 0; 349 log2_swath_height_c = 0; 350 } else { 351 unsigned int swath_height_l; 352 unsigned int swath_height_c; 353 354 if (!surf_vert) { 355 swath_height_l = rq_param->misc.rq_l.blk256_height; 356 swath_height_c = rq_param->misc.rq_c.blk256_height; 357 } else { 358 swath_height_l = rq_param->misc.rq_l.blk256_width; 359 swath_height_c = rq_param->misc.rq_c.blk256_width; 360 } 361 362 if (swath_height_l > 0) 363 log2_swath_height_l = dml_log2(swath_height_l); 364 365 if (req128_l && log2_swath_height_l > 0) 366 log2_swath_height_l -= 1; 367 368 if (swath_height_c > 0) 369 log2_swath_height_c = dml_log2(swath_height_c); 370 371 if (req128_c && log2_swath_height_c > 0) 372 log2_swath_height_c -= 1; 373 } 374 375 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 376 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 377 378 DTRACE("DLG: %s: req128_l = %0d", __func__, req128_l); 379 DTRACE("DLG: %s: req128_c = %0d", __func__, req128_c); 380 DTRACE("DLG: %s: full_swath_bytes_packed_l = %0d", __func__, full_swath_bytes_packed_l); 381 DTRACE("DLG: %s: full_swath_bytes_packed_c = %0d", __func__, full_swath_bytes_packed_c); 382 } 383 384 /* Need refactor. */ 385 static void dml1_rq_dlg_get_row_heights( 386 struct display_mode_lib *mode_lib, 387 unsigned int *o_dpte_row_height, 388 unsigned int *o_meta_row_height, 389 unsigned int vp_width, 390 unsigned int data_pitch, 391 int source_format, 392 int tiling, 393 int macro_tile_size, 394 int source_scan, 395 int is_chroma) 396 { 397 bool surf_linear = (tiling == dm_sw_linear); 398 bool surf_vert = (source_scan == dm_vert); 399 400 unsigned int bytes_per_element = get_bytes_per_element( 401 (enum source_format_class) source_format, 402 is_chroma); 403 unsigned int log2_bytes_per_element = dml_log2(bytes_per_element); 404 unsigned int blk256_width = 0; 405 unsigned int blk256_height = 0; 406 407 unsigned int log2_blk256_height; 408 unsigned int blk_bytes; 409 unsigned int log2_blk_bytes; 410 unsigned int log2_blk_height; 411 unsigned int log2_blk_width; 412 unsigned int log2_meta_req_bytes; 413 unsigned int log2_meta_req_height; 414 unsigned int log2_meta_req_width; 415 unsigned int log2_meta_row_height; 416 unsigned int log2_vmpg_bytes; 417 unsigned int dpte_buf_in_pte_reqs; 418 unsigned int log2_vmpg_height; 419 unsigned int log2_vmpg_width; 420 unsigned int log2_dpte_req_height_ptes; 421 unsigned int log2_dpte_req_width_ptes; 422 unsigned int log2_dpte_req_height; 423 unsigned int log2_dpte_req_width; 424 unsigned int log2_dpte_row_height_linear; 425 unsigned int log2_dpte_row_height; 426 unsigned int dpte_req_width; 427 428 if (surf_linear) { 429 blk256_width = 256; 430 blk256_height = 1; 431 } else { 432 get_blk256_size(&blk256_width, &blk256_height, bytes_per_element); 433 } 434 435 log2_blk256_height = dml_log2((double) blk256_height); 436 blk_bytes = surf_linear ? 437 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 438 log2_blk_bytes = dml_log2((double) blk_bytes); 439 log2_blk_height = 0; 440 log2_blk_width = 0; 441 442 /* remember log rule 443 * "+" in log is multiply 444 * "-" in log is divide 445 * "/2" is like square root 446 * blk is vertical biased 447 */ 448 if (tiling != dm_sw_linear) 449 log2_blk_height = log2_blk256_height 450 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 451 else 452 log2_blk_height = 0; /* blk height of 1 */ 453 454 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 455 456 /* ------- */ 457 /* meta */ 458 /* ------- */ 459 log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */ 460 461 /* each 64b meta request for dcn is 8x8 meta elements and 462 * a meta element covers one 256b block of the data surface. 463 */ 464 log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 */ 465 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 466 - log2_meta_req_height; 467 log2_meta_row_height = 0; 468 469 /* the dimensions of a meta row are meta_row_width x meta_row_height in elements. 470 * calculate upper bound of the meta_row_width 471 */ 472 if (!surf_vert) 473 log2_meta_row_height = log2_meta_req_height; 474 else 475 log2_meta_row_height = log2_meta_req_width; 476 477 *o_meta_row_height = 1 << log2_meta_row_height; 478 479 /* ------ */ 480 /* dpte */ 481 /* ------ */ 482 log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 483 dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 484 485 log2_vmpg_height = 0; 486 log2_vmpg_width = 0; 487 log2_dpte_req_height_ptes = 0; 488 log2_dpte_req_width_ptes = 0; 489 log2_dpte_req_height = 0; 490 log2_dpte_req_width = 0; 491 log2_dpte_row_height_linear = 0; 492 log2_dpte_row_height = 0; 493 dpte_req_width = 0; /* 64b dpte req width in data element */ 494 495 if (surf_linear) 496 log2_vmpg_height = 0; /* one line high */ 497 else 498 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 499 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 500 501 /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */ 502 if (log2_blk_bytes <= log2_vmpg_bytes) 503 log2_dpte_req_height_ptes = 0; 504 else if (log2_blk_height - log2_vmpg_height >= 2) 505 log2_dpte_req_height_ptes = 2; 506 else 507 log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height; 508 log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes; 509 510 ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */ 511 (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */ 512 (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */ 513 514 /* the dpte request dimensions in data elements is dpte_req_width x dpte_req_height 515 * log2_wmpg_width is how much 1 pte represent, now trying to calculate how much 64b pte req represent 516 */ 517 log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 518 log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 519 dpte_req_width = 1 << log2_dpte_req_width; 520 521 /* calculate pitch dpte row buffer can hold 522 * round the result down to a power of two. 523 */ 524 if (surf_linear) { 525 log2_dpte_row_height_linear = dml_floor( 526 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 527 1); 528 529 ASSERT(log2_dpte_row_height_linear >= 3); 530 531 if (log2_dpte_row_height_linear > 7) 532 log2_dpte_row_height_linear = 7; 533 534 log2_dpte_row_height = log2_dpte_row_height_linear; 535 } else { 536 /* the upper bound of the dpte_row_width without dependency on viewport position follows. */ 537 if (!surf_vert) 538 log2_dpte_row_height = log2_dpte_req_height; 539 else 540 log2_dpte_row_height = 541 (log2_blk_width < log2_dpte_req_width) ? 542 log2_blk_width : log2_dpte_req_width; 543 } 544 545 /* From programming guide: 546 * There is a special case of saving only half of ptes returned due to buffer space limits. 547 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16 548 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb). 549 */ 550 if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12 551 && log2_blk_bytes >= 16) 552 log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */ 553 554 *o_dpte_row_height = 1 << log2_dpte_row_height; 555 } 556 557 static void get_surf_rq_param( 558 struct display_mode_lib *mode_lib, 559 struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing_param, 560 struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param, 561 struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param, 562 const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param, 563 bool is_chroma) 564 { 565 unsigned int vp_width = 0; 566 unsigned int vp_height = 0; 567 unsigned int data_pitch = 0; 568 unsigned int meta_pitch = 0; 569 unsigned int ppe = 1; 570 bool surf_linear; 571 bool surf_vert; 572 unsigned int bytes_per_element; 573 unsigned int log2_bytes_per_element; 574 unsigned int blk256_width; 575 unsigned int blk256_height; 576 unsigned int log2_blk256_width; 577 unsigned int log2_blk256_height; 578 unsigned int blk_bytes; 579 unsigned int log2_blk_bytes; 580 unsigned int log2_blk_height; 581 unsigned int log2_blk_width; 582 unsigned int log2_meta_req_bytes; 583 unsigned int log2_meta_req_height; 584 unsigned int log2_meta_req_width; 585 unsigned int meta_req_width; 586 unsigned int meta_req_height; 587 unsigned int log2_meta_row_height; 588 unsigned int meta_row_width_ub; 589 unsigned int log2_meta_chunk_bytes; 590 unsigned int log2_meta_chunk_height; 591 unsigned int log2_meta_chunk_width; 592 unsigned int log2_min_meta_chunk_bytes; 593 unsigned int min_meta_chunk_width; 594 unsigned int meta_chunk_width; 595 unsigned int meta_chunk_per_row_int; 596 unsigned int meta_row_remainder; 597 unsigned int meta_chunk_threshold; 598 unsigned int meta_blk_bytes; 599 unsigned int meta_blk_height; 600 unsigned int meta_blk_width; 601 unsigned int meta_surface_bytes; 602 unsigned int vmpg_bytes; 603 unsigned int meta_pte_req_per_frame_ub; 604 unsigned int meta_pte_bytes_per_frame_ub; 605 unsigned int log2_vmpg_bytes; 606 unsigned int dpte_buf_in_pte_reqs; 607 unsigned int log2_vmpg_height; 608 unsigned int log2_vmpg_width; 609 unsigned int log2_dpte_req_height_ptes; 610 unsigned int log2_dpte_req_width_ptes; 611 unsigned int log2_dpte_req_height; 612 unsigned int log2_dpte_req_width; 613 unsigned int log2_dpte_row_height_linear; 614 unsigned int log2_dpte_row_height; 615 unsigned int log2_dpte_group_width; 616 unsigned int dpte_row_width_ub; 617 unsigned int dpte_row_height; 618 unsigned int dpte_req_height; 619 unsigned int dpte_req_width; 620 unsigned int dpte_group_width; 621 unsigned int log2_dpte_group_bytes; 622 unsigned int log2_dpte_group_length; 623 unsigned int func_meta_row_height, func_dpte_row_height; 624 625 /* TODO check if ppe apply for both luma and chroma in 422 case */ 626 if (is_chroma) { 627 vp_width = pipe_src_param->viewport_width_c / ppe; 628 vp_height = pipe_src_param->viewport_height_c; 629 data_pitch = pipe_src_param->data_pitch_c; 630 meta_pitch = pipe_src_param->meta_pitch_c; 631 } else { 632 vp_width = pipe_src_param->viewport_width / ppe; 633 vp_height = pipe_src_param->viewport_height; 634 data_pitch = pipe_src_param->data_pitch; 635 meta_pitch = pipe_src_param->meta_pitch; 636 } 637 638 rq_sizing_param->chunk_bytes = 8192; 639 640 if (rq_sizing_param->chunk_bytes == 64 * 1024) 641 rq_sizing_param->min_chunk_bytes = 0; 642 else 643 rq_sizing_param->min_chunk_bytes = 1024; 644 645 rq_sizing_param->meta_chunk_bytes = 2048; 646 rq_sizing_param->min_meta_chunk_bytes = 256; 647 648 rq_sizing_param->mpte_group_bytes = 2048; 649 650 surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 651 surf_vert = (pipe_src_param->source_scan == dm_vert); 652 653 bytes_per_element = get_bytes_per_element( 654 (enum source_format_class) pipe_src_param->source_format, 655 is_chroma); 656 log2_bytes_per_element = dml_log2(bytes_per_element); 657 blk256_width = 0; 658 blk256_height = 0; 659 660 if (surf_linear) { 661 blk256_width = 256 / bytes_per_element; 662 blk256_height = 1; 663 } else { 664 get_blk256_size(&blk256_width, &blk256_height, bytes_per_element); 665 } 666 667 DTRACE("DLG: %s: surf_linear = %d", __func__, surf_linear); 668 DTRACE("DLG: %s: surf_vert = %d", __func__, surf_vert); 669 DTRACE("DLG: %s: blk256_width = %d", __func__, blk256_width); 670 DTRACE("DLG: %s: blk256_height = %d", __func__, blk256_height); 671 672 log2_blk256_width = dml_log2((double) blk256_width); 673 log2_blk256_height = dml_log2((double) blk256_height); 674 blk_bytes = 675 surf_linear ? 256 : get_blk_size_bytes( 676 (enum source_macro_tile_size) pipe_src_param->macro_tile_size); 677 log2_blk_bytes = dml_log2((double) blk_bytes); 678 log2_blk_height = 0; 679 log2_blk_width = 0; 680 681 /* remember log rule 682 * "+" in log is multiply 683 * "-" in log is divide 684 * "/2" is like square root 685 * blk is vertical biased 686 */ 687 if (pipe_src_param->sw_mode != dm_sw_linear) 688 log2_blk_height = log2_blk256_height 689 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 690 else 691 log2_blk_height = 0; /* blk height of 1 */ 692 693 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 694 695 if (!surf_vert) { 696 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 697 + blk256_width; 698 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 699 } else { 700 rq_dlg_param->swath_width_ub = dml_round_to_multiple( 701 vp_height - 1, 702 blk256_height, 703 1) + blk256_height; 704 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 705 } 706 707 if (!surf_vert) 708 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 709 * bytes_per_element; 710 else 711 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 712 * bytes_per_element; 713 714 rq_misc_param->blk256_height = blk256_height; 715 rq_misc_param->blk256_width = blk256_width; 716 717 /* ------- */ 718 /* meta */ 719 /* ------- */ 720 log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */ 721 722 /* each 64b meta request for dcn is 8x8 meta elements and 723 * a meta element covers one 256b block of the data surface. 724 */ 725 log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 byte, each byte represent 1 blk256 */ 726 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 727 - log2_meta_req_height; 728 meta_req_width = 1 << log2_meta_req_width; 729 meta_req_height = 1 << log2_meta_req_height; 730 log2_meta_row_height = 0; 731 meta_row_width_ub = 0; 732 733 /* the dimensions of a meta row are meta_row_width x meta_row_height in elements. 734 * calculate upper bound of the meta_row_width 735 */ 736 if (!surf_vert) { 737 log2_meta_row_height = log2_meta_req_height; 738 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 739 + meta_req_width; 740 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 741 } else { 742 log2_meta_row_height = log2_meta_req_width; 743 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 744 + meta_req_height; 745 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 746 } 747 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 748 749 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 750 log2_meta_chunk_height = log2_meta_row_height; 751 752 /*full sized meta chunk width in unit of data elements */ 753 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 754 - log2_meta_chunk_height; 755 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 756 min_meta_chunk_width = 1 757 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 758 - log2_meta_chunk_height); 759 meta_chunk_width = 1 << log2_meta_chunk_width; 760 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 761 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 762 meta_chunk_threshold = 0; 763 meta_blk_bytes = 4096; 764 meta_blk_height = blk256_height * 64; 765 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 766 meta_surface_bytes = meta_pitch 767 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) 768 + meta_blk_height) * bytes_per_element / 256; 769 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 770 meta_pte_req_per_frame_ub = (dml_round_to_multiple( 771 meta_surface_bytes - vmpg_bytes, 772 8 * vmpg_bytes, 773 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 774 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; /*64B mpte request */ 775 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 776 777 DTRACE("DLG: %s: meta_blk_height = %d", __func__, meta_blk_height); 778 DTRACE("DLG: %s: meta_blk_width = %d", __func__, meta_blk_width); 779 DTRACE("DLG: %s: meta_surface_bytes = %d", __func__, meta_surface_bytes); 780 DTRACE("DLG: %s: meta_pte_req_per_frame_ub = %d", __func__, meta_pte_req_per_frame_ub); 781 DTRACE("DLG: %s: meta_pte_bytes_per_frame_ub = %d", __func__, meta_pte_bytes_per_frame_ub); 782 783 if (!surf_vert) 784 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 785 else 786 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 787 788 if (meta_row_remainder <= meta_chunk_threshold) 789 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 790 else 791 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 792 793 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 794 795 /* ------ */ 796 /* dpte */ 797 /* ------ */ 798 log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 799 dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 800 801 log2_vmpg_height = 0; 802 log2_vmpg_width = 0; 803 log2_dpte_req_height_ptes = 0; 804 log2_dpte_req_width_ptes = 0; 805 log2_dpte_req_height = 0; 806 log2_dpte_req_width = 0; 807 log2_dpte_row_height_linear = 0; 808 log2_dpte_row_height = 0; 809 log2_dpte_group_width = 0; 810 dpte_row_width_ub = 0; 811 dpte_row_height = 0; 812 dpte_req_height = 0; /* 64b dpte req height in data element */ 813 dpte_req_width = 0; /* 64b dpte req width in data element */ 814 dpte_group_width = 0; 815 log2_dpte_group_bytes = 0; 816 log2_dpte_group_length = 0; 817 818 if (surf_linear) 819 log2_vmpg_height = 0; /* one line high */ 820 else 821 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 822 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 823 824 /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */ 825 if (log2_blk_bytes <= log2_vmpg_bytes) 826 log2_dpte_req_height_ptes = 0; 827 else if (log2_blk_height - log2_vmpg_height >= 2) 828 log2_dpte_req_height_ptes = 2; 829 else 830 log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height; 831 log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes; 832 833 /* Ensure we only have the 3 shapes */ 834 ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */ 835 (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */ 836 (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */ 837 838 /* The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 839 * log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 840 * That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 841 */ 842 log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 843 log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 844 dpte_req_height = 1 << log2_dpte_req_height; 845 dpte_req_width = 1 << log2_dpte_req_width; 846 847 /* calculate pitch dpte row buffer can hold 848 * round the result down to a power of two. 849 */ 850 if (surf_linear) { 851 log2_dpte_row_height_linear = dml_floor( 852 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 853 1); 854 855 ASSERT(log2_dpte_row_height_linear >= 3); 856 857 if (log2_dpte_row_height_linear > 7) 858 log2_dpte_row_height_linear = 7; 859 860 log2_dpte_row_height = log2_dpte_row_height_linear; 861 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 862 863 /* For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 864 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 865 */ 866 dpte_row_width_ub = dml_round_to_multiple( 867 data_pitch * dpte_row_height - 1, 868 dpte_req_width, 869 1) + dpte_req_width; 870 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 871 } else { 872 /* for tiled mode, row height is the same as req height and row store up to vp size upper bound */ 873 if (!surf_vert) { 874 log2_dpte_row_height = log2_dpte_req_height; 875 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 876 + dpte_req_width; 877 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 878 } else { 879 log2_dpte_row_height = 880 (log2_blk_width < log2_dpte_req_width) ? 881 log2_blk_width : log2_dpte_req_width; 882 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 883 + dpte_req_height; 884 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 885 } 886 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 887 } 888 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; 889 890 /* From programming guide: 891 * There is a special case of saving only half of ptes returned due to buffer space limits. 892 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16 893 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb). 894 */ 895 if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12 896 && log2_blk_bytes >= 16) { 897 log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */ 898 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 899 } 900 901 /* the dpte_group_bytes is reduced for the specific case of vertical 902 * access of a tile surface that has dpte request of 8x1 ptes. 903 */ 904 if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) /*reduced, in this case, will have page fault within a group */ 905 rq_sizing_param->dpte_group_bytes = 512; 906 else 907 /*full size */ 908 rq_sizing_param->dpte_group_bytes = 2048; 909 910 /*since pte request size is 64byte, the number of data pte requests per full sized group is as follows. */ 911 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 912 log2_dpte_group_length = log2_dpte_group_bytes - 6; /*length in 64b requests */ 913 914 /* full sized data pte group width in elements */ 915 if (!surf_vert) 916 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 917 else 918 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 919 920 dpte_group_width = 1 << log2_dpte_group_width; 921 922 /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 923 * the upper bound for the dpte groups per row is as follows. 924 */ 925 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( 926 (double) dpte_row_width_ub / dpte_group_width, 927 1); 928 929 dml1_rq_dlg_get_row_heights( 930 mode_lib, 931 &func_dpte_row_height, 932 &func_meta_row_height, 933 vp_width, 934 data_pitch, 935 pipe_src_param->source_format, 936 pipe_src_param->sw_mode, 937 pipe_src_param->macro_tile_size, 938 pipe_src_param->source_scan, 939 is_chroma); 940 941 /* Just a check to make sure this function and the new one give the same 942 * result. The standalone get_row_heights() function is based off of the 943 * code in this function so the same changes need to be made to both. 944 */ 945 if (rq_dlg_param->meta_row_height != func_meta_row_height) { 946 DTRACE( 947 "MISMATCH: rq_dlg_param->meta_row_height = %d", 948 rq_dlg_param->meta_row_height); 949 DTRACE("MISMATCH: func_meta_row_height = %d", func_meta_row_height); 950 ASSERT(0); 951 } 952 953 if (rq_dlg_param->dpte_row_height != func_dpte_row_height) { 954 DTRACE( 955 "MISMATCH: rq_dlg_param->dpte_row_height = %d", 956 rq_dlg_param->dpte_row_height); 957 DTRACE("MISMATCH: func_dpte_row_height = %d", func_dpte_row_height); 958 ASSERT(0); 959 } 960 } 961 962 void dml1_rq_dlg_get_rq_params( 963 struct display_mode_lib *mode_lib, 964 struct _vcs_dpi_display_rq_params_st *rq_param, 965 const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param) 966 { 967 /* get param for luma surface */ 968 rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 969 || pipe_src_param->source_format == dm_420_10; 970 rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; 971 972 get_surf_rq_param( 973 mode_lib, 974 &(rq_param->sizing.rq_l), 975 &(rq_param->dlg.rq_l), 976 &(rq_param->misc.rq_l), 977 pipe_src_param, 978 0); 979 980 if (is_dual_plane((enum source_format_class) pipe_src_param->source_format)) { 981 /* get param for chroma surface */ 982 get_surf_rq_param( 983 mode_lib, 984 &(rq_param->sizing.rq_c), 985 &(rq_param->dlg.rq_c), 986 &(rq_param->misc.rq_c), 987 pipe_src_param, 988 1); 989 } 990 991 /* calculate how to split the det buffer space between luma and chroma */ 992 handle_det_buf_split(mode_lib, rq_param, pipe_src_param); 993 print__rq_params_st(mode_lib, rq_param); 994 } 995 996 /* Note: currently taken in as is. 997 * Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 998 */ 999 void dml1_rq_dlg_get_dlg_params( 1000 struct display_mode_lib *mode_lib, 1001 struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs, 1002 struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs, 1003 const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param, 1004 const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param, 1005 const struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param, 1006 const bool cstate_en, 1007 const bool pstate_en, 1008 const bool vm_en, 1009 const bool iflip_en) 1010 { 1011 /* Timing */ 1012 unsigned int htotal = e2e_pipe_param->pipe.dest.htotal; 1013 unsigned int hblank_end = e2e_pipe_param->pipe.dest.hblank_end; 1014 unsigned int vblank_start = e2e_pipe_param->pipe.dest.vblank_start; 1015 unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; 1016 bool interlaced = e2e_pipe_param->pipe.dest.interlaced; 1017 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 1018 1019 double pclk_freq_in_mhz = e2e_pipe_param->pipe.dest.pixel_rate_mhz; 1020 double refclk_freq_in_mhz = e2e_pipe_param->clks_cfg.refclk_mhz; 1021 double dppclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dppclk_mhz; 1022 double dispclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dispclk_mhz; 1023 1024 double ref_freq_to_pix_freq; 1025 double prefetch_xy_calc_in_dcfclk; 1026 double min_dcfclk_mhz; 1027 double t_calc_us; 1028 double min_ttu_vblank; 1029 double min_dst_y_ttu_vblank; 1030 unsigned int dlg_vblank_start; 1031 bool dcc_en; 1032 bool dual_plane; 1033 bool mode_422; 1034 unsigned int access_dir; 1035 unsigned int bytes_per_element_l; 1036 unsigned int bytes_per_element_c; 1037 unsigned int vp_height_l; 1038 unsigned int vp_width_l; 1039 unsigned int vp_height_c; 1040 unsigned int vp_width_c; 1041 unsigned int htaps_l; 1042 unsigned int htaps_c; 1043 double hratios_l; 1044 double hratios_c; 1045 double vratio_l; 1046 double vratio_c; 1047 double line_time_in_us; 1048 double vinit_l; 1049 double vinit_c; 1050 double vinit_bot_l; 1051 double vinit_bot_c; 1052 unsigned int swath_height_l; 1053 unsigned int swath_width_ub_l; 1054 unsigned int dpte_bytes_per_row_ub_l; 1055 unsigned int dpte_groups_per_row_ub_l; 1056 unsigned int meta_pte_bytes_per_frame_ub_l; 1057 unsigned int meta_bytes_per_row_ub_l; 1058 unsigned int swath_height_c; 1059 unsigned int swath_width_ub_c; 1060 unsigned int dpte_bytes_per_row_ub_c; 1061 unsigned int dpte_groups_per_row_ub_c; 1062 unsigned int meta_chunks_per_row_ub_l; 1063 unsigned int vupdate_offset; 1064 unsigned int vupdate_width; 1065 unsigned int vready_offset; 1066 unsigned int dppclk_delay_subtotal; 1067 unsigned int dispclk_delay_subtotal; 1068 unsigned int pixel_rate_delay_subtotal; 1069 unsigned int vstartup_start; 1070 unsigned int dst_x_after_scaler; 1071 unsigned int dst_y_after_scaler; 1072 double line_wait; 1073 double line_o; 1074 double line_setup; 1075 double line_calc; 1076 double dst_y_prefetch; 1077 double t_pre_us; 1078 unsigned int vm_bytes; 1079 unsigned int meta_row_bytes; 1080 unsigned int max_num_sw_l; 1081 unsigned int max_num_sw_c; 1082 unsigned int max_partial_sw_l; 1083 unsigned int max_partial_sw_c; 1084 double max_vinit_l; 1085 double max_vinit_c; 1086 unsigned int lsw_l; 1087 unsigned int lsw_c; 1088 unsigned int sw_bytes_ub_l; 1089 unsigned int sw_bytes_ub_c; 1090 unsigned int sw_bytes; 1091 unsigned int dpte_row_bytes; 1092 double prefetch_bw; 1093 double flip_bw; 1094 double t_vm_us; 1095 double t_r0_us; 1096 double dst_y_per_vm_vblank; 1097 double dst_y_per_row_vblank; 1098 double min_dst_y_per_vm_vblank; 1099 double min_dst_y_per_row_vblank; 1100 double lsw; 1101 double vratio_pre_l; 1102 double vratio_pre_c; 1103 unsigned int req_per_swath_ub_l; 1104 unsigned int req_per_swath_ub_c; 1105 unsigned int meta_row_height_l; 1106 unsigned int swath_width_pixels_ub_l; 1107 unsigned int swath_width_pixels_ub_c; 1108 unsigned int scaler_rec_in_width_l; 1109 unsigned int scaler_rec_in_width_c; 1110 unsigned int dpte_row_height_l; 1111 unsigned int dpte_row_height_c; 1112 double hscale_pixel_rate_l; 1113 double hscale_pixel_rate_c; 1114 double min_hratio_fact_l; 1115 double min_hratio_fact_c; 1116 double refcyc_per_line_delivery_pre_l; 1117 double refcyc_per_line_delivery_pre_c; 1118 double refcyc_per_line_delivery_l; 1119 double refcyc_per_line_delivery_c; 1120 double refcyc_per_req_delivery_pre_l; 1121 double refcyc_per_req_delivery_pre_c; 1122 double refcyc_per_req_delivery_l; 1123 double refcyc_per_req_delivery_c; 1124 double refcyc_per_req_delivery_pre_cur0; 1125 double refcyc_per_req_delivery_cur0; 1126 unsigned int full_recout_width; 1127 double hratios_cur0; 1128 unsigned int cur0_src_width; 1129 enum cursor_bpp cur0_bpp; 1130 unsigned int cur0_req_size; 1131 unsigned int cur0_req_width; 1132 double cur0_width_ub; 1133 double cur0_req_per_width; 1134 double hactive_cur0; 1135 1136 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 1137 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 1138 1139 DTRACE("DLG: %s: cstate_en = %d", __func__, cstate_en); 1140 DTRACE("DLG: %s: pstate_en = %d", __func__, pstate_en); 1141 DTRACE("DLG: %s: vm_en = %d", __func__, vm_en); 1142 DTRACE("DLG: %s: iflip_en = %d", __func__, iflip_en); 1143 1144 /* ------------------------- */ 1145 /* Section 1.5.2.1: OTG dependent Params */ 1146 /* ------------------------- */ 1147 DTRACE("DLG: %s: dppclk_freq_in_mhz = %3.2f", __func__, dppclk_freq_in_mhz); 1148 DTRACE("DLG: %s: dispclk_freq_in_mhz = %3.2f", __func__, dispclk_freq_in_mhz); 1149 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz); 1150 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz); 1151 DTRACE("DLG: %s: interlaced = %d", __func__, interlaced); 1152 1153 ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 1154 ASSERT(ref_freq_to_pix_freq < 4.0); 1155 disp_dlg_regs->ref_freq_to_pix_freq = 1156 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 1157 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 1158 * dml_pow(2, 8)); 1159 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 1160 * (double) ref_freq_to_pix_freq); 1161 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 1162 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */ 1163 1164 prefetch_xy_calc_in_dcfclk = 24.0; /* TODO: ip_param */ 1165 min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; 1166 t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz; 1167 min_ttu_vblank = dlg_sys_param->t_urg_wm_us; 1168 if (cstate_en) 1169 min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank); 1170 if (pstate_en) 1171 min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank); 1172 min_ttu_vblank = min_ttu_vblank + t_calc_us; 1173 1174 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 1175 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 1176 1177 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start 1178 + min_dst_y_ttu_vblank) * dml_pow(2, 2)); 1179 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 1180 1181 DTRACE("DLG: %s: min_dcfclk_mhz = %3.2f", __func__, min_dcfclk_mhz); 1182 DTRACE("DLG: %s: min_ttu_vblank = %3.2f", __func__, min_ttu_vblank); 1183 DTRACE( 1184 "DLG: %s: min_dst_y_ttu_vblank = %3.2f", 1185 __func__, 1186 min_dst_y_ttu_vblank); 1187 DTRACE("DLG: %s: t_calc_us = %3.2f", __func__, t_calc_us); 1188 DTRACE( 1189 "DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x", 1190 __func__, 1191 disp_dlg_regs->min_dst_y_next_start); 1192 DTRACE( 1193 "DLG: %s: ref_freq_to_pix_freq = %3.2f", 1194 __func__, 1195 ref_freq_to_pix_freq); 1196 1197 /* ------------------------- */ 1198 /* Section 1.5.2.2: Prefetch, Active and TTU */ 1199 /* ------------------------- */ 1200 /* Prefetch Calc */ 1201 /* Source */ 1202 dcc_en = e2e_pipe_param->pipe.src.dcc; 1203 dual_plane = is_dual_plane( 1204 (enum source_format_class) e2e_pipe_param->pipe.src.source_format); 1205 mode_422 = 0; /* TODO */ 1206 access_dir = (e2e_pipe_param->pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */ 1207 bytes_per_element_l = get_bytes_per_element( 1208 (enum source_format_class) e2e_pipe_param->pipe.src.source_format, 1209 0); 1210 bytes_per_element_c = get_bytes_per_element( 1211 (enum source_format_class) e2e_pipe_param->pipe.src.source_format, 1212 1); 1213 vp_height_l = e2e_pipe_param->pipe.src.viewport_height; 1214 vp_width_l = e2e_pipe_param->pipe.src.viewport_width; 1215 vp_height_c = e2e_pipe_param->pipe.src.viewport_height_c; 1216 vp_width_c = e2e_pipe_param->pipe.src.viewport_width_c; 1217 1218 /* Scaling */ 1219 htaps_l = e2e_pipe_param->pipe.scale_taps.htaps; 1220 htaps_c = e2e_pipe_param->pipe.scale_taps.htaps_c; 1221 hratios_l = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio; 1222 hratios_c = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio_c; 1223 vratio_l = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio; 1224 vratio_c = e2e_pipe_param->pipe.scale_ratio_depth.vscl_ratio_c; 1225 1226 line_time_in_us = (htotal / pclk_freq_in_mhz); 1227 vinit_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit; 1228 vinit_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_c; 1229 vinit_bot_l = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot; 1230 vinit_bot_c = e2e_pipe_param->pipe.scale_ratio_depth.vinit_bot_c; 1231 1232 swath_height_l = rq_dlg_param->rq_l.swath_height; 1233 swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; 1234 dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; 1235 dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; 1236 meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; 1237 meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; 1238 1239 swath_height_c = rq_dlg_param->rq_c.swath_height; 1240 swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; 1241 dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; 1242 dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; 1243 1244 meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; 1245 vupdate_offset = e2e_pipe_param->pipe.dest.vupdate_offset; 1246 vupdate_width = e2e_pipe_param->pipe.dest.vupdate_width; 1247 vready_offset = e2e_pipe_param->pipe.dest.vready_offset; 1248 1249 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1250 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1251 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1252 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1253 1254 vstartup_start = e2e_pipe_param->pipe.dest.vstartup_start; 1255 1256 if (interlaced) 1257 vstartup_start = vstartup_start / 2; 1258 1259 if (vstartup_start >= min_vblank) { 1260 DTRACE( 1261 "WARNING_DLG: %s: vblank_start=%d vblank_end=%d", 1262 __func__, 1263 vblank_start, 1264 vblank_end); 1265 DTRACE( 1266 "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d", 1267 __func__, 1268 vstartup_start, 1269 min_vblank); 1270 min_vblank = vstartup_start + 1; 1271 DTRACE( 1272 "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d", 1273 __func__, 1274 vstartup_start, 1275 min_vblank); 1276 } 1277 1278 dst_x_after_scaler = 0; 1279 dst_y_after_scaler = 0; 1280 1281 if (e2e_pipe_param->pipe.src.is_hsplit) 1282 dst_x_after_scaler = pixel_rate_delay_subtotal 1283 + e2e_pipe_param->pipe.dest.recout_width; 1284 else 1285 dst_x_after_scaler = pixel_rate_delay_subtotal; 1286 1287 if (e2e_pipe_param->dout.output_format == dm_420) 1288 dst_y_after_scaler = 1; 1289 else 1290 dst_y_after_scaler = 0; 1291 1292 if (dst_x_after_scaler >= htotal) { 1293 dst_x_after_scaler = dst_x_after_scaler - htotal; 1294 dst_y_after_scaler = dst_y_after_scaler + 1; 1295 } 1296 1297 DTRACE("DLG: %s: htotal = %d", __func__, htotal); 1298 DTRACE( 1299 "DLG: %s: pixel_rate_delay_subtotal = %d", 1300 __func__, 1301 pixel_rate_delay_subtotal); 1302 DTRACE("DLG: %s: dst_x_after_scaler = %d", __func__, dst_x_after_scaler); 1303 DTRACE("DLG: %s: dst_y_after_scaler = %d", __func__, dst_y_after_scaler); 1304 1305 line_wait = mode_lib->soc.urgent_latency_us; 1306 if (cstate_en) 1307 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1308 if (pstate_en) 1309 line_wait = dml_max( 1310 mode_lib->soc.dram_clock_change_latency_us 1311 + mode_lib->soc.urgent_latency_us, 1312 line_wait); 1313 line_wait = line_wait / line_time_in_us; 1314 1315 line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal; 1316 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal; 1317 line_calc = t_calc_us / line_time_in_us; 1318 1319 DTRACE( 1320 "DLG: %s: soc.sr_enter_plus_exit_time_us = %3.2f", 1321 __func__, 1322 (double) mode_lib->soc.sr_enter_plus_exit_time_us); 1323 DTRACE( 1324 "DLG: %s: soc.dram_clock_change_latency_us = %3.2f", 1325 __func__, 1326 (double) mode_lib->soc.dram_clock_change_latency_us); 1327 DTRACE( 1328 "DLG: %s: soc.urgent_latency_us = %3.2f", 1329 __func__, 1330 mode_lib->soc.urgent_latency_us); 1331 1332 DTRACE("DLG: %s: swath_height_l = %d", __func__, swath_height_l); 1333 if (dual_plane) 1334 DTRACE("DLG: %s: swath_height_c = %d", __func__, swath_height_c); 1335 1336 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, (double) line_time_in_us); 1337 DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset); 1338 DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width); 1339 DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset); 1340 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, line_time_in_us); 1341 DTRACE("DLG: %s: line_wait = %3.2f", __func__, line_wait); 1342 DTRACE("DLG: %s: line_o = %3.2f", __func__, line_o); 1343 DTRACE("DLG: %s: line_setup = %3.2f", __func__, line_setup); 1344 DTRACE("DLG: %s: line_calc = %3.2f", __func__, line_calc); 1345 1346 dst_y_prefetch = ((double) min_vblank - 1.0) 1347 - (line_setup + line_calc + line_wait + line_o); 1348 DTRACE("DLG: %s: dst_y_prefetch (before rnd) = %3.2f", __func__, dst_y_prefetch); 1349 ASSERT(dst_y_prefetch >= 2.0); 1350 1351 dst_y_prefetch = dml_floor(4.0 * (dst_y_prefetch + 0.125), 1) / 4; 1352 DTRACE("DLG: %s: dst_y_prefetch (after rnd) = %3.2f", __func__, dst_y_prefetch); 1353 1354 t_pre_us = dst_y_prefetch * line_time_in_us; 1355 vm_bytes = 0; 1356 meta_row_bytes = 0; 1357 1358 if (dcc_en && vm_en) 1359 vm_bytes = meta_pte_bytes_per_frame_ub_l; 1360 if (dcc_en) 1361 meta_row_bytes = meta_bytes_per_row_ub_l; 1362 1363 max_num_sw_l = 0; 1364 max_num_sw_c = 0; 1365 max_partial_sw_l = 0; 1366 max_partial_sw_c = 0; 1367 1368 max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l; 1369 max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c; 1370 1371 get_swath_need(mode_lib, &max_num_sw_l, &max_partial_sw_l, swath_height_l, max_vinit_l); 1372 if (dual_plane) 1373 get_swath_need( 1374 mode_lib, 1375 &max_num_sw_c, 1376 &max_partial_sw_c, 1377 swath_height_c, 1378 max_vinit_c); 1379 1380 lsw_l = max_num_sw_l * swath_height_l + max_partial_sw_l; 1381 lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c; 1382 sw_bytes_ub_l = lsw_l * swath_width_ub_l * bytes_per_element_l; 1383 sw_bytes_ub_c = lsw_c * swath_width_ub_c * bytes_per_element_c; 1384 sw_bytes = 0; 1385 dpte_row_bytes = 0; 1386 1387 if (vm_en) { 1388 if (dual_plane) 1389 dpte_row_bytes = dpte_bytes_per_row_ub_l + dpte_bytes_per_row_ub_c; 1390 else 1391 dpte_row_bytes = dpte_bytes_per_row_ub_l; 1392 } else { 1393 dpte_row_bytes = 0; 1394 } 1395 1396 if (dual_plane) 1397 sw_bytes = sw_bytes_ub_l + sw_bytes_ub_c; 1398 else 1399 sw_bytes = sw_bytes_ub_l; 1400 1401 DTRACE("DLG: %s: sw_bytes_ub_l = %d", __func__, sw_bytes_ub_l); 1402 DTRACE("DLG: %s: sw_bytes_ub_c = %d", __func__, sw_bytes_ub_c); 1403 DTRACE("DLG: %s: sw_bytes = %d", __func__, sw_bytes); 1404 DTRACE("DLG: %s: vm_bytes = %d", __func__, vm_bytes); 1405 DTRACE("DLG: %s: meta_row_bytes = %d", __func__, meta_row_bytes); 1406 DTRACE("DLG: %s: dpte_row_bytes = %d", __func__, dpte_row_bytes); 1407 1408 prefetch_bw = (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us; 1409 flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param->total_flip_bw) 1410 / (double) dlg_sys_param->total_flip_bytes; 1411 t_vm_us = line_time_in_us / 4.0; 1412 if (vm_en && dcc_en) { 1413 t_vm_us = dml_max( 1414 dlg_sys_param->t_extra_us, 1415 dml_max((double) vm_bytes / prefetch_bw, t_vm_us)); 1416 1417 if (iflip_en && !dual_plane) { 1418 t_vm_us = dml_max(mode_lib->soc.urgent_latency_us, t_vm_us); 1419 if (flip_bw > 0.) 1420 t_vm_us = dml_max(vm_bytes / flip_bw, t_vm_us); 1421 } 1422 } 1423 1424 t_r0_us = dml_max(dlg_sys_param->t_extra_us - t_vm_us, line_time_in_us - t_vm_us); 1425 1426 if (vm_en || dcc_en) { 1427 t_r0_us = dml_max( 1428 (double) (dpte_row_bytes + meta_row_bytes) / prefetch_bw, 1429 dlg_sys_param->t_extra_us); 1430 t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us); 1431 1432 if (iflip_en && !dual_plane) { 1433 t_r0_us = dml_max(mode_lib->soc.urgent_latency_us * 2.0, t_r0_us); 1434 if (flip_bw > 0.) 1435 t_r0_us = dml_max( 1436 (dpte_row_bytes + meta_row_bytes) / flip_bw, 1437 t_r0_us); 1438 } 1439 } 1440 1441 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */ 1442 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */ 1443 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1444 DTRACE( 1445 "DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x", 1446 __func__, 1447 disp_dlg_regs->dst_y_after_scaler); 1448 DTRACE( 1449 "DLG: %s: disp_dlg_regs->refcyc_x_after_scaler = 0x%0x", 1450 __func__, 1451 disp_dlg_regs->refcyc_x_after_scaler); 1452 1453 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1454 DTRACE( 1455 "DLG: %s: disp_dlg_regs->dst_y_prefetch = %d", 1456 __func__, 1457 disp_dlg_regs->dst_y_prefetch); 1458 1459 dst_y_per_vm_vblank = 0.0; 1460 dst_y_per_row_vblank = 0.0; 1461 1462 dst_y_per_vm_vblank = t_vm_us / line_time_in_us; 1463 dst_y_per_vm_vblank = dml_floor(4.0 * (dst_y_per_vm_vblank + 0.125), 1) / 4.0; 1464 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1465 1466 dst_y_per_row_vblank = t_r0_us / line_time_in_us; 1467 dst_y_per_row_vblank = dml_floor(4.0 * (dst_y_per_row_vblank + 0.125), 1) / 4.0; 1468 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1469 1470 DTRACE("DLG: %s: lsw_l = %d", __func__, lsw_l); 1471 DTRACE("DLG: %s: lsw_c = %d", __func__, lsw_c); 1472 DTRACE("DLG: %s: dpte_bytes_per_row_ub_l = %d", __func__, dpte_bytes_per_row_ub_l); 1473 DTRACE("DLG: %s: dpte_bytes_per_row_ub_c = %d", __func__, dpte_bytes_per_row_ub_c); 1474 1475 DTRACE("DLG: %s: prefetch_bw = %3.2f", __func__, prefetch_bw); 1476 DTRACE("DLG: %s: flip_bw = %3.2f", __func__, flip_bw); 1477 DTRACE("DLG: %s: t_pre_us = %3.2f", __func__, t_pre_us); 1478 DTRACE("DLG: %s: t_vm_us = %3.2f", __func__, t_vm_us); 1479 DTRACE("DLG: %s: t_r0_us = %3.2f", __func__, t_r0_us); 1480 DTRACE("DLG: %s: dst_y_per_vm_vblank = %3.2f", __func__, dst_y_per_vm_vblank); 1481 DTRACE("DLG: %s: dst_y_per_row_vblank = %3.2f", __func__, dst_y_per_row_vblank); 1482 DTRACE("DLG: %s: dst_y_prefetch = %3.2f", __func__, dst_y_prefetch); 1483 1484 min_dst_y_per_vm_vblank = 8.0; 1485 min_dst_y_per_row_vblank = 16.0; 1486 if (htotal <= 75) { 1487 min_vblank = 300; 1488 min_dst_y_per_vm_vblank = 100.0; 1489 min_dst_y_per_row_vblank = 100.0; 1490 } 1491 1492 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); 1493 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); 1494 1495 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1496 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1497 1498 DTRACE("DLG: %s: lsw = %3.2f", __func__, lsw); 1499 1500 vratio_pre_l = get_vratio_pre( 1501 mode_lib, 1502 max_num_sw_l, 1503 max_partial_sw_l, 1504 swath_height_l, 1505 max_vinit_l, 1506 lsw); 1507 vratio_pre_c = 1.0; 1508 if (dual_plane) 1509 vratio_pre_c = get_vratio_pre( 1510 mode_lib, 1511 max_num_sw_c, 1512 max_partial_sw_c, 1513 swath_height_c, 1514 max_vinit_c, 1515 lsw); 1516 1517 DTRACE("DLG: %s: vratio_pre_l=%3.2f", __func__, vratio_pre_l); 1518 DTRACE("DLG: %s: vratio_pre_c=%3.2f", __func__, vratio_pre_c); 1519 1520 ASSERT(vratio_pre_l <= 4.0); 1521 if (vratio_pre_l >= 4.0) 1522 disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1; 1523 else 1524 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1525 1526 ASSERT(vratio_pre_c <= 4.0); 1527 if (vratio_pre_c >= 4.0) 1528 disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1; 1529 else 1530 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1531 1532 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1533 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1534 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1535 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); 1536 1537 disp_dlg_regs->refcyc_per_pte_group_vblank_c = 1538 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1539 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c); 1540 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13)); 1541 1542 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1543 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1544 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1545 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); 1546 1547 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1548 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ 1549 1550 /* Active */ 1551 req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; 1552 req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; 1553 meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; 1554 swath_width_pixels_ub_l = 0; 1555 swath_width_pixels_ub_c = 0; 1556 scaler_rec_in_width_l = 0; 1557 scaler_rec_in_width_c = 0; 1558 dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; 1559 dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; 1560 1561 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1562 / (double) vratio_l * dml_pow(2, 2)); 1563 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); 1564 1565 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1566 / (double) vratio_c * dml_pow(2, 2)); 1567 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17)); 1568 1569 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1570 / (double) vratio_l * dml_pow(2, 2)); 1571 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); 1572 1573 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ 1574 1575 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1576 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1577 / (double) dpte_groups_per_row_ub_l); 1578 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1579 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1580 1581 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c 1582 / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq 1583 / (double) dpte_groups_per_row_ub_c); 1584 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1585 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1586 1587 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1588 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1589 / (double) meta_chunks_per_row_ub_l); 1590 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1591 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1592 1593 if (mode_422) { 1594 swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */ 1595 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1596 } else { 1597 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1598 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1599 } 1600 1601 if (htaps_l <= 1) 1602 min_hratio_fact_l = 2.0; 1603 else if (htaps_l <= 6) { 1604 if ((hratios_l * 2.0) > 4.0) 1605 min_hratio_fact_l = 4.0; 1606 else 1607 min_hratio_fact_l = hratios_l * 2.0; 1608 } else { 1609 if (hratios_l > 4.0) 1610 min_hratio_fact_l = 4.0; 1611 else 1612 min_hratio_fact_l = hratios_l; 1613 } 1614 1615 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1616 1617 if (htaps_c <= 1) 1618 min_hratio_fact_c = 2.0; 1619 else if (htaps_c <= 6) { 1620 if ((hratios_c * 2.0) > 4.0) 1621 min_hratio_fact_c = 4.0; 1622 else 1623 min_hratio_fact_c = hratios_c * 2.0; 1624 } else { 1625 if (hratios_c > 4.0) 1626 min_hratio_fact_c = 4.0; 1627 else 1628 min_hratio_fact_c = hratios_c; 1629 } 1630 1631 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1632 1633 refcyc_per_line_delivery_pre_l = 0.; 1634 refcyc_per_line_delivery_pre_c = 0.; 1635 refcyc_per_line_delivery_l = 0.; 1636 refcyc_per_line_delivery_c = 0.; 1637 1638 refcyc_per_req_delivery_pre_l = 0.; 1639 refcyc_per_req_delivery_pre_c = 0.; 1640 refcyc_per_req_delivery_l = 0.; 1641 refcyc_per_req_delivery_c = 0.; 1642 refcyc_per_req_delivery_pre_cur0 = 0.; 1643 refcyc_per_req_delivery_cur0 = 0.; 1644 1645 full_recout_width = 0; 1646 if (e2e_pipe_param->pipe.src.is_hsplit) { 1647 if (e2e_pipe_param->pipe.dest.full_recout_width == 0) { 1648 DTRACE("DLG: %s: Warningfull_recout_width not set in hsplit mode", __func__); 1649 full_recout_width = e2e_pipe_param->pipe.dest.recout_width * 2; /* assume half split for dcn1 */ 1650 } else 1651 full_recout_width = e2e_pipe_param->pipe.dest.full_recout_width; 1652 } else 1653 full_recout_width = e2e_pipe_param->pipe.dest.recout_width; 1654 1655 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( 1656 mode_lib, 1657 refclk_freq_in_mhz, 1658 pclk_freq_in_mhz, 1659 full_recout_width, 1660 vratio_pre_l, 1661 hscale_pixel_rate_l, 1662 swath_width_pixels_ub_l, 1663 1); /* per line */ 1664 1665 refcyc_per_line_delivery_l = get_refcyc_per_delivery( 1666 mode_lib, 1667 refclk_freq_in_mhz, 1668 pclk_freq_in_mhz, 1669 full_recout_width, 1670 vratio_l, 1671 hscale_pixel_rate_l, 1672 swath_width_pixels_ub_l, 1673 1); /* per line */ 1674 1675 DTRACE("DLG: %s: full_recout_width = %d", __func__, full_recout_width); 1676 DTRACE("DLG: %s: hscale_pixel_rate_l = %3.2f", __func__, hscale_pixel_rate_l); 1677 DTRACE( 1678 "DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f", 1679 __func__, 1680 refcyc_per_line_delivery_pre_l); 1681 DTRACE( 1682 "DLG: %s: refcyc_per_line_delivery_l = %3.2f", 1683 __func__, 1684 refcyc_per_line_delivery_l); 1685 1686 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( 1687 refcyc_per_line_delivery_pre_l, 1688 1); 1689 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( 1690 refcyc_per_line_delivery_l, 1691 1); 1692 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); 1693 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); 1694 1695 if (dual_plane) { 1696 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( 1697 mode_lib, 1698 refclk_freq_in_mhz, 1699 pclk_freq_in_mhz, 1700 full_recout_width, 1701 vratio_pre_c, 1702 hscale_pixel_rate_c, 1703 swath_width_pixels_ub_c, 1704 1); /* per line */ 1705 1706 refcyc_per_line_delivery_c = get_refcyc_per_delivery( 1707 mode_lib, 1708 refclk_freq_in_mhz, 1709 pclk_freq_in_mhz, 1710 full_recout_width, 1711 vratio_c, 1712 hscale_pixel_rate_c, 1713 swath_width_pixels_ub_c, 1714 1); /* per line */ 1715 1716 DTRACE( 1717 "DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f", 1718 __func__, 1719 refcyc_per_line_delivery_pre_c); 1720 DTRACE( 1721 "DLG: %s: refcyc_per_line_delivery_c = %3.2f", 1722 __func__, 1723 refcyc_per_line_delivery_c); 1724 1725 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( 1726 refcyc_per_line_delivery_pre_c, 1727 1); 1728 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( 1729 refcyc_per_line_delivery_c, 1730 1); 1731 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); 1732 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); 1733 } 1734 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1735 1736 /* TTU - Luma / Chroma */ 1737 if (access_dir) { /* vertical access */ 1738 scaler_rec_in_width_l = vp_height_l; 1739 scaler_rec_in_width_c = vp_height_c; 1740 } else { 1741 scaler_rec_in_width_l = vp_width_l; 1742 scaler_rec_in_width_c = vp_width_c; 1743 } 1744 1745 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( 1746 mode_lib, 1747 refclk_freq_in_mhz, 1748 pclk_freq_in_mhz, 1749 full_recout_width, 1750 vratio_pre_l, 1751 hscale_pixel_rate_l, 1752 scaler_rec_in_width_l, 1753 req_per_swath_ub_l); /* per req */ 1754 refcyc_per_req_delivery_l = get_refcyc_per_delivery( 1755 mode_lib, 1756 refclk_freq_in_mhz, 1757 pclk_freq_in_mhz, 1758 full_recout_width, 1759 vratio_l, 1760 hscale_pixel_rate_l, 1761 scaler_rec_in_width_l, 1762 req_per_swath_ub_l); /* per req */ 1763 1764 DTRACE( 1765 "DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f", 1766 __func__, 1767 refcyc_per_req_delivery_pre_l); 1768 DTRACE( 1769 "DLG: %s: refcyc_per_req_delivery_l = %3.2f", 1770 __func__, 1771 refcyc_per_req_delivery_l); 1772 1773 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1774 * dml_pow(2, 10)); 1775 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1776 * dml_pow(2, 10)); 1777 1778 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1779 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1780 1781 if (dual_plane) { 1782 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( 1783 mode_lib, 1784 refclk_freq_in_mhz, 1785 pclk_freq_in_mhz, 1786 full_recout_width, 1787 vratio_pre_c, 1788 hscale_pixel_rate_c, 1789 scaler_rec_in_width_c, 1790 req_per_swath_ub_c); /* per req */ 1791 refcyc_per_req_delivery_c = get_refcyc_per_delivery( 1792 mode_lib, 1793 refclk_freq_in_mhz, 1794 pclk_freq_in_mhz, 1795 full_recout_width, 1796 vratio_c, 1797 hscale_pixel_rate_c, 1798 scaler_rec_in_width_c, 1799 req_per_swath_ub_c); /* per req */ 1800 1801 DTRACE( 1802 "DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f", 1803 __func__, 1804 refcyc_per_req_delivery_pre_c); 1805 DTRACE( 1806 "DLG: %s: refcyc_per_req_delivery_c = %3.2f", 1807 __func__, 1808 refcyc_per_req_delivery_c); 1809 1810 disp_ttu_regs->refcyc_per_req_delivery_pre_c = 1811 (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); 1812 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1813 * dml_pow(2, 10)); 1814 1815 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1816 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1817 } 1818 1819 /* TTU - Cursor */ 1820 hratios_cur0 = e2e_pipe_param->pipe.scale_ratio_depth.hscl_ratio; 1821 cur0_src_width = e2e_pipe_param->pipe.src.cur0_src_width; /* cursor source width */ 1822 cur0_bpp = (enum cursor_bpp) e2e_pipe_param->pipe.src.cur0_bpp; 1823 cur0_req_size = 0; 1824 cur0_req_width = 0; 1825 cur0_width_ub = 0.0; 1826 cur0_req_per_width = 0.0; 1827 hactive_cur0 = 0.0; 1828 1829 ASSERT(cur0_src_width <= 256); 1830 1831 if (cur0_src_width > 0) { 1832 unsigned int cur0_bit_per_pixel = 0; 1833 1834 if (cur0_bpp == dm_cur_2bit) { 1835 cur0_req_size = 64; /* byte */ 1836 cur0_bit_per_pixel = 2; 1837 } else { /* 32bit */ 1838 cur0_bit_per_pixel = 32; 1839 if (cur0_src_width >= 1 && cur0_src_width <= 16) 1840 cur0_req_size = 64; 1841 else if (cur0_src_width >= 17 && cur0_src_width <= 31) 1842 cur0_req_size = 128; 1843 else 1844 cur0_req_size = 256; 1845 } 1846 1847 cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0); 1848 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) 1849 * (double) cur0_req_width; 1850 cur0_req_per_width = cur0_width_ub / (double) cur0_req_width; 1851 hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* TODO: oswin to think about what to do for cursor */ 1852 1853 if (vratio_pre_l <= 1.0) { 1854 refcyc_per_req_delivery_pre_cur0 = hactive_cur0 * ref_freq_to_pix_freq 1855 / (double) cur0_req_per_width; 1856 } else { 1857 refcyc_per_req_delivery_pre_cur0 = (double) refclk_freq_in_mhz 1858 * (double) cur0_src_width / hscale_pixel_rate_l 1859 / (double) cur0_req_per_width; 1860 } 1861 1862 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1863 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1864 ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13)); 1865 1866 if (vratio_l <= 1.0) { 1867 refcyc_per_req_delivery_cur0 = hactive_cur0 * ref_freq_to_pix_freq 1868 / (double) cur0_req_per_width; 1869 } else { 1870 refcyc_per_req_delivery_cur0 = (double) refclk_freq_in_mhz 1871 * (double) cur0_src_width / hscale_pixel_rate_l 1872 / (double) cur0_req_per_width; 1873 } 1874 1875 DTRACE("DLG: %s: cur0_req_width = %d", __func__, cur0_req_width); 1876 DTRACE( 1877 "DLG: %s: cur0_width_ub = %3.2f", 1878 __func__, 1879 cur0_width_ub); 1880 DTRACE( 1881 "DLG: %s: cur0_req_per_width = %3.2f", 1882 __func__, 1883 cur0_req_per_width); 1884 DTRACE( 1885 "DLG: %s: hactive_cur0 = %3.2f", 1886 __func__, 1887 hactive_cur0); 1888 DTRACE( 1889 "DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f", 1890 __func__, 1891 refcyc_per_req_delivery_pre_cur0); 1892 DTRACE( 1893 "DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f", 1894 __func__, 1895 refcyc_per_req_delivery_cur0); 1896 1897 disp_ttu_regs->refcyc_per_req_delivery_cur0 = 1898 (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); 1899 ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13)); 1900 } else { 1901 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 0; 1902 disp_ttu_regs->refcyc_per_req_delivery_cur0 = 0; 1903 } 1904 1905 /* TTU - Misc */ 1906 disp_ttu_regs->qos_level_low_wm = 0; 1907 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1908 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1909 * ref_freq_to_pix_freq); 1910 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 1911 1912 disp_ttu_regs->qos_level_flip = 14; 1913 disp_ttu_regs->qos_level_fixed_l = 8; 1914 disp_ttu_regs->qos_level_fixed_c = 8; 1915 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1916 disp_ttu_regs->qos_ramp_disable_l = 0; 1917 disp_ttu_regs->qos_ramp_disable_c = 0; 1918 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1919 1920 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1921 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1922 1923 print__ttu_regs_st(mode_lib, disp_ttu_regs); 1924 print__dlg_regs_st(mode_lib, disp_dlg_regs); 1925 } 1926